Cmos Sequential Circuits

8/9/2019 Cmos Sequential Circuits

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Voltae transfer c!ara of bistatble ele"net

! bistable circuit $ a circuit having two stable states that represent % and &. !nother

common name for a bistable circuit is flip#flop. The cross#coupling of two inverters results in

a bistable circuit, that is, a circuit with two stable states, each corresponding to a logic state.

The circuit serves as a memory, storing either a & or a %.

SR #LIP#LOP

NOR $ASE% SR #LIP #LOP

The circuit consists of two '()S *)+ gates. )ne of the input terminals of

each*)+ gate is used to cross#couple to the output of the other *)+ gate,-hence, the circuit

can perform a simple memory function of holding its state.,while the second input enables

triggering of the circuit. S and + e/ternal triggering inputs are for allowing a change of state

from one stable operating mode to the other.

0ate level schematic and block diagram

Trut! table


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Circuit operation

The S+ flipflop has two complementary outputs, 1 and 1. y definition, the flipflop is

said to be in its set state when 1 is equal to logic 2 & 2 and 1 is equal to logic 2%.2

'onversely, the latch is in its reset state when the output 1 is equal to logic 2%2 and 1 is equal

to 2&.2

The operation of the '()S S+ flip circuit shown in Fig. can be e/amined in more

detail by considering the operating modes of the four n()S transistors, (I, (, (3, and

(4. If the set input -S is equal to logic high-5)6 and the reset input -+ is equal to logic

low-5)7, both of the parallel#connected transistors (l and ( will be on. 'onsequently, the

voltage on node 1 will assume a logic#low level of 5)78 %. !t the same time, both (3 and

(4 are turned off, which results in a logic#high voltage -5)6 at node 1. If the reset input -+

is equal to 5)6 and the set input -S is equal to 5)7, the situation will be reversed -(l and

( turned off 1is at logic high and (3 and (4 turned on#1 at logic low. 9hen both of the

input voltages are equal to logic low ,5)7o there are two possibilities. epending on the

previous state of the S+ latch, either ( or (3 will be on, while both of the trigger

transistors (I and (4 are off. This will generate a logic#low level of 5)78 ) at one of the

output nodes, while the complementary output node is at 5)6.

Hence to su""ari&e

If both input signals - S and +are equal to logic 2%,2 the S+ flipflop will operate

e/actly like the simple cross#coupled bistable element, it will preserve -hold either

one of its two stable operating points -states as determined by the previous inputs.

If the set input -S is equal to logic 2&2 and the reset input is equal to logic 2%,2 then

the output node 1 will be forced to logic 2 & 2 while the output node 1 is forced tologic 2%.2 This means that the S+ flipflop will be set, regardless of its previous state.


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If S is equal to 2%2 and + is equal to 2 ,2 then the output node 1 will be forced to 2%2

while 1 is forced to 2&.2 Thus, with this input combination, the flipflop is reset,

regardless of its previously held state.

If both of the inputs S and + are equal to logic &2 ,both output nodes will be forced to

logic 2%,2 which conflicts with the complementarity of 1 and 1. Therefore, this input

combination is not permitted during normal operation and is considered to be a not

allowed condition.

The static operation modes and voltage levels of the *)+#based '()S S+ flipflop circuit

are summari;ed in the following table.

NAN%' SR Latc! or flipflop


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The gate#level schematic and the corresponding block diagram representation of the *!*#

based S+ flipflop circuit are shown in Fig.. The small circles at the S and + input terminals

indicate that the circuit responds to active low input signals. *!*#based S+ flipflop circuit

reveals that in order to hold -preserve a state, both of the e/ternal trigger inputs must be

equal to logic 2 &.2 The operating point or the state of the circuit can be changed only by

pulling the set input to logic ;ero or by pulling the reset input to ;ero. 9e can observe that if

S is equal to 2%2 and + is equal to 2 &,2 the output 1 attains a logic 2 & 2 value and the

complementary output 1 becomes logic 2%.2 Thus, in order to setthe *!* S+ flipflop, a

logic 2%2 must be applied to the set -S input. Similarly, in order to reset the latch, a logic 2%2

must be applied to the reset -+ input. The conclusion is that the NAN%(base) SR flipflop


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respon)s to acti*e lo+ input sinals, as oppose) to t!e NOR(base) SR latc!, +!ic!

respon)s to acti*e !i! inputs. *ote that if both input signals are equal to logic 2%,2 both

output nodes assume a logic#high level, which is not allowed because it violates the

complementarity of the two outputs.

Cloc-e) SR Latc!

To facilitate synchronous operation, the circuit response can be controlled simply by adding a

gating clock signal to the circuit, so that the outputs will respond to the input levels only

during the active period of a clock pulse.

The gate#level schematic of a clocked *)+#based S+ latch is shown in Fig. It can be seen

that if the clock -'


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combination S 8 + 8 2&2 is not allowed in the clocked S+ latch. 9ith both inputs S and + at

logic 2 &,2 the occurrence of a clock pulse causes both outputs to go momentarily to ;ero.

9hen the clock pulse is removed, i.e., when it becomes 2%,2 the state of the latch is

indeterminate. It can eventually settle into either state, depending on slight delay differences

between the output signals. T!e circuit is strictl. le*el(sensiti*e )urin acti*e cloc-

p!ases, i/e/, an. c!anes occurrin/ in t!e S an) R input *oltaes +!en t!e C0 le*el is

e1ual to 2 3 2 +ill be reflecte) onto t!e circuit outputs. 'onsequently, even a narrow spike

or glitch occurring during an active clock phase can set or reset the latch, if the loop delay is

shorter than the pulse width.

Figure shows a '()S implementation of the clocked *)+#based S+ latch circuit, using two

simple !)I gates. *otice that the !)I#based implementation of the circuit results in a very

small transistor count.


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The *!*#based S+ latch can also be implemented with gating clock input, as shown in

Fig. It must be noted, however, that both input signals S and + as well as the clock signal '


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! different implementation of the clocked *!*#based S+ latch is shown in Fig. . 6ere,

both input signals and the '< signal are active high, i.e., the latch output 1 will be set when

'< 8 2 &,2 S 8 2 &,2 and + 8 2).2 Similarly, the latch will be reset when '< 8 2&,2 8 2),2

and + 8 2&.2 The latch preserves its state as long as the clock signal is inactive, i.e., when '


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logic 2%,2 the latch preserves its current state. If, on the other hand, both inputs are equal to 2

& 2 during the active clock phase, the latch simply switches its state due to feedback. In other

words, the =< latch does not have a not#allowed input combination. !s in the other clocked

latch circuits, the =< latch will hold its current state when the clock is inactive -'< 8 2%2.

The operation of the clocked =< latch is summari;e#d in the truth Table.

NOR $ASE% IMPLEMENTATION O# 60 LATCH


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Figure shows an alternative, *)+#based implementation of the clocked =< latch, and '()S

reali;ation of this circuit. *ote that the !)I#based circuit structure results in a relatively low

transistor count, and consequently, a more compact circuit compared to the all#*!*

reali;ation

9hile there is no not#allowed input combination for the =< latch, there is still a potential

problem. If both inputs are equal to logic 2 & 2 during the active phase of the clock pulse, the

output of the circuit will oscillate -toggle continuously until either the clock becomes

inactive -goes to ;ero, or one of the input signals goes to ;ero. To prevent this undesirable

timing problem, the clock pulse width must be made smaller than the input#to#output

propagation delay .

Master(Sla*e #lip(#lop

(ater slave flipflop consists of two latch stages in a cascaded configuration.


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Since the "aster an) t!e sla*e staes are effecti*el. )ecouple) fro" eac! ot!er +it! t!e

opposite cloc-in sc!e"e, t!e circuit is ne*er transparent , i.e., a change occurring in the

primary inputs is never reflected directly to the outputs. T!isvery important propert.clearly

separates t!e "aster(sla*e flip(flop fro" t!e latc! circuits

ecause the master and the slave stages are decoupled from each other, the circuit allows for

toggling when = 8 < 8 2&,2 but it eliminates the possibility of uncontrolled oscillations since

only one stage is active at any given time.

! *)+#based alternative reali;ation for the master#slave flip#flop circuit is shown in Fig.

The master#slave flip#flop circuit e/amined here has the potential problem of 2one"s

catching.2 9hen the clock pulse is high, a narrow spike or glitch in one of the inputs, for

instance a glitch in the = line -or < line, may set -or reset the master latch and thus cause an

unwanted state transition, which will then be propagated into the slave stage during the

following phase. This problem can be eliminated to a large e/tent by building an edge#

triggered master#slave flip#flop.

% LATCH


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The gate#level representation of the #latch is simply obtained by modifying the clocked

*)+#based S+ latch circuit. 6ere, the circuit has a single input , which is directly

connected to the S input of the latch. The input variable is also inverted and connected to

the + input of the latch. It can be seen from the gate#level schematic that the output 1

assumes the value of the input when the clock is active, i.e., for '< 8 2&.2 9hen the clock

signal goes to ;ero, the output will simply preserve its state. Thus, the '< input acts as an

enable signal which allows data to be accepted into the #latch.

The #latch finds many applications in digital circuit design, primarily for temporary

storage of data or as a delay element.

'onsider the circuit diagram given in Fig., which shows a basic two#inverter loop and two

'()S transmission gate -T0 switches.

The T0 at the input is activated by the '< signal, whereas the T0 in the inverter loop is

activated by the inverse of the '< signal, '


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! timing diagram shows the time intervals during which the input and the output signals

should be valid -unshaded.

The valid input must be stable for a short time before -setup time, tsetup and after -hold

time, thold the negative clock transition, during which the input switch opens and the loop

switch closes. )nce the inverter loop is completed by closing the loop switch, the output will

preserve its valid level. In the #latch design, the requirements for setup time and hold time

should be met carefully. !ny violation of such specifications can cause metastability

problems.

Figure shows a different version of the '()S #latch.


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The circuit contains two tristate inverters, driven by the clock signal and its inverse. The basic

operation principle of the circuit is the same as that shown in first figure. The first tri#state

inverter acts as the input switch, accepting the input signal when the clock is high. !t this

time, the second tristate inverter is at its high#impedance state, and the output 1 is following

the input signal. 9hen the clock goes low, the input buffer becomes inactive, and the second

tristate inverter completes the two#inverter loop, which preserves its state until the ne/t clock

pulse.

MASTER SLAVE NE 5ATIVE E%5E TRI55ERE% % #LIP #LOP

'onsider the two#stage master#slave flip#flop circuit shown in Fig.,which is constructed by

simply cascading two, #latch circuits. The first stage -master isidriven by the clock signal,

while the second stage -slave is driven by the inverted clock signal. Thus, the master stage is

positive level#sensitive, while the slave stage is negative level#sensitive.


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9hen the clock is, high, the master stage follows the input while the slave stage holds the

previous value. 9hen the clock changes from logic 2&2 to logic 2,2 the master latch ceases to

sample the input and stores the value at the time of the clock transition. !t the same time,

the slave latch becomes transparent, passing the stored master value 1mto the output of the

slave stage, 1.. The input cannot affect the output because the master stage is disconnected

from the input. 9hen the clock changes again from logic %2 to &,2 the slave latch locks in

the master latch output and the master stage starts sampling the input again. Thus, this circuit

is a negative edge#triggered flip#flop by virtue of the fact that it samples the input at the

falling edge of the clock pulse.

CMOS LO5IC S7STEMS

>sueodo n()S

ynamic '()S

'()S domino

'locked '()S

n#p '()S

?ipper '()S

Pseu)o nMOS

>seudon()S *!*3 structure

>seudon()S logic structure consists of n()S pull down n@w and a >()S pullup transistor

with its gate grounded.epletion load pull upt transistor of standard n()S logic ckts

replaced with a p()S transistor with its gate connected to ground so that it is always )*

forms a pseudo n()S logic structure.This a ratioe) circuit since 0ain ratio of n#driver


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transistors to p#transistor load -beta driver @beta load , is important to ensure adequate noise

margin.

%isa)*antaes of pseudo#n()S gate compared to a complementary '()S gate

Non&ero static po+er )issipation, since the always#on pmos load device conducts a

steady#state current when the output voltage is lower than 5. !lso,

5alue of VOLand the noise "arinsare now determined by the ratio of the pmos load

transconductance-Ap to the pull#down or driver transconductance-An

A)*antae

The clear advantage of pseudo#*()S is the reduced number of transistors

-*B& versus * for complementary '()S.

C+eason for low value of 5)7 ,and reduced noise margin

-*oise margin,*(785I7#5)7,5)78% for FD77 '()S but for pseudo n()s .96E* 5out is

low #5)7, ie 5in 85,nmos pulldown n@w is )* providing a path from output node to

ground,where as >()S pull up is always )* connecting 5 to o@p node.6ence 5)7 will

not be ;ero.-this is not the case with '()S since if pulldown n@w is )* pull will be

off .hence noise margin also will be low compared to complementary '()S.

Inorder to have a low value for 5)7 ratioing is necessary.

The value of 5)7 is obtained by equating the currents through the driver-*()S and load

->()Sdevices for 5in 8 5. !t this operation point, it is reasonable to assume that the

*()S device resides in linear mode -since the output should ideally be close to %5, while

the >()S load is saturated.

rain current in saturation Id>8 Ap-50S>#5T> 5S!T#5S!T

rain current in linear region Id*8 An-50S*#5T*5out#5

out

5out85)7508550S>8% # 58 #550S*85Id*8 # Id>

An-5#5T*5)7#5)78 # Ap-#5#5T> 5S!T#5

S!T

5T*85T>,*E07E'TI*0 6I6E+ >)9E+S

5)78 # Ap-#5#5T> 5S!T

An-5#5T*


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8 Ap5S!T

An

5)7 8 Gp'o/-9@7>5S!T

Gn'o/-9@7n

6ence to get low value of 5)7 >()S device should be si;ed much smaller than that

of *()S device.H

%.na"ic CMOS

!ctual logic is implemented in faster n()S logic and a p #transistor is used for non#

time critical precharging of output line so that output capacitance is charged to 5. The

circuit operation is based on first prechargingthe output node capacitance and subsequently,

evaluatingthe output level according to the applied inputs.

Prec!are

9hen '7< 8 %, the output node )ut is precharged to 5 by the >()S transistor

(p.uring that time, the evaluate *()S transistor (e is off, so that the pull#down path is

disabled.

E*aluation


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For '7< 8 &, the precharge transistor (p is off, and the evaluation transistor (e is turned

on. The output is conditionally discharged based on the input values and the pull#down

topology. If the inputs are such that the >*->ull own *etwork conducts, then a low

resistance path e/ists between )ut and 0* and the output is discharged to 0*. If the

>* is turned off, the precharged value remains stored on the output capacitance '7

A)*antae

ynamic '()S circuit technique allows us to significantly reduce the number of

transistors used to implement any logic function.

Li"itations

'harge sharing may be a problem unless the inputs are constrained not to change

during the period of clock

Single phase dynamic logic structures cannot be cascaded since owing to circuit

delays incorrect inputs to ne/t stage may be present when evaluation begins and

wrong output results.

)ne remedy is to employ a four phase clock in which actual signals are

derived clocks & 3 34 4& as shown in fig b. The basic circuit in fig a ismodified by the inclusion of a transmission gate as in fig c the function of which is to

samle the output during evaluate period and to hold the output state while the ne/t

stage logic evaluates. For this strategy to work ne/t stage must operate with

overlapping but later clock signals. Since there are four different derived clock signals

there are four different clocking configurations. Inorder to avoid erroneous evaluation

gate must be connected in allowable ne/t sequences set out in table below


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Cloc-e) CMOS8C'MOS 9LO5IC


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The logic is implemented in both n# and p transistors in form of a pull up p block and

a complementary n block pull down structure .6owever logic in this case is evaluated only

during on period of clock.! clocked inverter-tristate inverter forms part of this family.

Li"itation

)wing to e/tra transistors in series slow rise times and fall times can be e/pected.

CMOS %o"ino loic

!n e/tension to dynamic '()s 7)0I' ,a dynamic '()S logi stage followed by a

static inverter constitute '()S domino logic.This static inverting buffer allows for

cascading of logic structures using only a single phase clock without erroneous outputs.

#eatures

Such logic structures can have smaller area than conventional '()S logic

+equires less no:of transistors to implement logic function compared to conventional

'()S

>arasitic capacitances are smaller so that higher operating speeds are possible.

)peration is free of glitches since each gate can make only one & to % transition

)nly non inverting structures are possible because of presence of inverting buffer

Li"itations

'harge distribution is a problem in domino '()S

Eg !B06B-EBF-'B


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n(p CMOS8NORA9LO5IC

This is a variation of basic dynamic logic arrangement in which actual logic blocks are

alternatively n and p in a cascaded structure.The pre charge and evaluate transistors are fed

from clock and alternately and functions of top and bottom transistors are alternate

between precharge and evaluate. The precharge#and#evaluate timing of n()S logic stages is

accomplished by the clock signal , whereas the p()S logic stages are controlled by the

inverted clock signal, . The operation of the *)+! '()S circuit is as follows: 9hen the

clock signal is low, the output nodes of n()S logic blocks are precharged to 5 through

the p()S precharge transistors, whereas the output nodes of p()S logic blocks are pre#


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discharged to % 5 through the n()S discharge transistors, driven by .9hen the clock

signal makes a low#to#high transition -note that the inverted clock signal makes a high#to#low

transition simultaneously, all cascaded n()S and p()S logic stages evaluate one after

the other.

A%VANTA5Eof *)+! '()S logic

Static '()S inverter is not required at the output of every dynamic logic stage.

Instead, direct coupling of logic blocks is feasible by alternating n()S and p()S

logic blocks. *)+! logic is also compatible with domino '()S logic.

The second important advantage of *)+! '()S logic is that it allows pipelined

system architecture.

Li"itation

Suffer from charge sharing and leakage.

:ipper CMOS

?ipper '()S is identical with *)+!-np '()Swith the e/ception of the clock signals.

The ?ipper '()S clock scheme requires the generation of slightly different clock signals for

the precharge -discharge transistors and for the pull#down -pull#up transistors. In particular,

the clock signals which drive the p()S precharge and n()S discharge transistors allow

these transistors to remain in weak conduction or near cut#off during the evaluation phase,

thus compensating for the charge leakage and charge#sharing problems.

Scalin

The reduction of the si;e, i.e., the dimensions of ()SFETs, is commonly referred to

as scaling. It is e/pected that the operational characteristics of the ()S transistor will change

with the reduction of its dimensions. !lso, some physical limitations eventually restrict the

e/tent of scaling that is practically achievable. There are two basic types of si;e#reduction

strategies: full scaling -also called constant#field scaling and constantvoltage scaling. Scaling

of ()S transistors is concerned with systematic reduction of overall dimensions of the

devices as allowed by the available technology, while preserving the geometric ratios found


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in the larger devices. The proportional scaling of all devices in a circuit would certainly result

in a reduction of the total silicon area occupied by the circuit, thereby increasing the overall

functional density of the chip. To describe device scaling, we introduce a constant scaling

factor S J &. !ll hori;ontal and vertical dimensions of the large#si;e transistor are then

divided by this scaling factor to obtain the scaled device. The e/tent of scaling that isachievable is obviously determined by the fabrication technology and more specifically, by

the minimum feature si;e.

Scalin "o)elsand scaling factors

Constannt fiel) 8E9 scalin-full scaling# This scaling option attempts to preserve

the magnitude of internal electric fields in the ()SFET, while the dimensions are

scaled down by a scaling factor . To achieve this goal, all potentials must be scaled

down proportionally, by the same scaling factor.

Constannt Voltae 8V9 scalin# In constant#voltage scaling, all dimensions of

()SFET are reduced by a scaling factor. The power supply voltage and the terminal

voltages, on the other hand, remain unchanged.

Co"bine) *oltae an) fiel) scalin.

7 87ength of channel

9 89idth of chananel

8Thickness of channel

K 8Lunction depth


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To accomodtae these three models thwo scaling factors are used.&@M !* &@A. &@A is chosen

a scaling factor for supply voltage 5 and gate o/ide thickness . &@M# for all other linear

dimensions.For the constant field moldel A8M and for constant voltage moldel A8& is applied.

Effects of scalin(Scalin factors for )e*ice scalin

8O$TAIN E;PRESSION 8%ERIVE9 #OR EACH %EVICE PARAMETER


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! ()S transistor is called a short#channel device if its channel length is on the same order of

magnitude as the depletion region thicknesses of the source and drainLunctions. !lternatively,

a ()SFET can be defined as a short#channel device if the effective channel length 7 effis

appro/imately equal to the source and drain Lunction depth /L.

Velocit. satutation

The lateral electric field EOalong the channel increases, as the effective channel length is

decreased. 9hile the electron drift velocity 5din the channel is proportional to the electric

field for lower field values, this drift velocity tends to saturate at high channel electric fields.

'arrier velocity saturation actually reduces the saturation#mode current.

Mobilit. )eara)ation

In short#channel ()S transistors, the carrier velocity in the channel is also a function of the

normal -vertical electric#field component E/. Since the vertical field influences the

scattering of carriers -collisions suffered by the carriers in the surface region, the surface

mobility is reduced.This is mobility degradation.

Mo)ification of t!res!ol) *otae

Subt!res!ol) con)uction in s"all(eo"etr. MOS transistors(The channel current that

flows under these conditions -50S P 5tn is called the subthreshold current.

Punc!(t!rou!

The channel length is on the same order of magnitude as source and drain depletion region

thicknesses. For large drain#bias voltages, the depletion region surrounding the drain can

e/tend farther toward the source, and the two depletion regions can eventually merge. This

condition is termed punch#through the current rises sharply once punch#through occurs.

O>i)e brea-)o+n

!nother limitation on the scaling of thickness of o/ide to/ is the possibility of o/ide

breakdown. If the o/ide electric field perpendicular to the surface is larger than a certain

breakdown field, the silicon#dio/ide layer may sustain permanent damage during operation,

leading to device failure.

Hot carrier in=ection

This decrease in critical device dimensions to submicron ranges, accompanied by increasing

substrate doping densities, results in a significant increase of the hori;ontal and vertical

electric fields in the channel region. Electrons and holes gaining high kinetic energies in the

electric field -hot carriers may, however, be inLected into the gate o/ide, and cause


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permanent changes in the o/ide interface charge distribution, degrading the current#voltage

characteristics of the ()SFET

$iCMOS

'ombines ipolar and '()S transistors in a single integrated circuit. y retaining benefits of bipolarand '()S, i'()S is able to achieve 57SI circuits with speed#power#density performance.

The

superiority of the i'()S gate lies in the high current drive capability of the bipolar output

transistors, the ;ero static power dissipation, and the high input impedance provided by the ()SFET

configuration.

-STU%7 fabrication of $ICMOS STRUCTUREF+)( TEKT #$OT0AR

COMPARISON $?4 CMOS AN% $IPOLAR TECHNOLO5IES

CMOS $IPOLAR

7ow static power dissipation 6igh static power dissipation

6igh i@p impedance 7ow i@p impedance

6igh noise margin 7ow noise margin-low voltage swing logic

6igh packing density 7ow packing density

6igh delay sensitivity to load 7ow delay sensitivity to load

7ow output drive current 6igh output drive current

7ow gm-transconductance 7arge gm-transconductance

idirectional capability unidirectional

*early ideal switching device *on ideal switching device

A)*antaes of $iCMOS

i'()S devices offer high load current sinking and sourcing is required. The high current

gain of the *>* transistor greatly improves the output drive capability of a conventional

'()S device.

Improved speed over purely#'()S technology

7ower power dissipation than purely#bipolar technology -simplifying packaging and board

requirements

7atchup immunity

Fle/ible I@)s -i.e., TT7, '()S or E'7 compatible i'()S technology is well suited for

I@) intensive applications. E'7, TT7 and '()S input and output levels can easily be

generated

%ISA%VANTA5E

'ostlier due to added >rocessing 'omple/ity.!dditional masking steps than in '()S to

fabricate bipolar structure along with '()S

COMPARISON $?4 CMOS $IPOLAR AN% $iCMOS TECHNOLO5IES

'()S I>)7!+ i'()S

7ow static power dissipation 6igh static power dissipation 7ow static power dissipation

than ipolar

7ow speed-Slow switching 6igh speed Faster than '()S

7ow o@p current drive 6igh o@p current drive 6igh o@p current drive

6igh i@p impedance 7ow i@p impedance 6igh i@p impedance6igh noise margin-high o@p 7ow noise margin 6igh noise margin compared to


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voltage swing bipolar

Fabrication process simpler

compared to i'()S

Simpler fabrication Fabrication process is comple/

$iCMOS Loic ates

esigned with ()S circuits to implement the logic and bipolar transistors to drive output loads.

C!aractreristics of $iCMOS loic ates8+rite for in*erter,nan) an) nor9

The o@p logic levels will be god nd will be close to rail voltages

6igh i@p impedance

7ow o@p impedance

6igh current drive capability,occupies relatives smaller area

6igh noise margin

$iCMOS in*ereter

i'()S inverter circuit consists of two bipolartransistors T& and T with one n()S T3 and one

p()S transistor T4,both being enhancemnet mode devices.

OPERATION O# CIRCUIT

9ith 5in8% volts-0*,T3 is off so that T& will be non conductiong.but T4 is on and

supplies current to base of T which will conduct and act as current source to charge load '7

towards BQ 5)7TS-5. The )@> of inverter rise BQ volts less base to emitter voltage

5Eof T.

9ith 5in8BQ volts-5,T4 is off so that T will be non conductiong.but T3 is on and

supplies current to base of T& which will conduct and act as current sink to disccharge load

'7towards % 5)7TS-0*. The )@> of inverter will fall to % volts plus saturation voltage

5'Esat from collector to emitter of T&.

T& !* T will present low impedances when turned on into saturation and load '7 will be

charged or discharged rapidly.


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The o@p logic levels will be god nd will be close to rail voltages

Inverter has 6igh i@p impedance

Inverter has 7ow o@p impedance

Inverter has 6igh current drive capability,occupies relatives smaller area

Inverter has 6igh noise margin

LIMITATIONS O# $ASIC INVERETER CON#I5URATION

)wing to presence of ' path from 5 to 0* through T3 and T& ,this is not a ood

arrangement to implement since there will be a significant static current flow whenever5in8logic&.

Thre is no diharge path for current from base of either bipolar transistor when it is being

turned off.This will slow down action of circuit.

!n improved i'()S inverter 9IT6 *) ST!TI' 'D++E*T F7)9

' path through T3 and T& is eliminated but o@p voltage swing is now reduced since output cannot

fall below base to emitter voltage of T&.-this o@p volt is in effect base voltage of T& in this

arrangement.T& wil turn off if o@p volt fall below 5E )F T&.


31/33

'onsider the simple i'()S inverter circuit shown in figure which consists of two ()S transistors

and two" npn#type bipolar transistors which drive a large output capacitance 'load. The operation

concept of this circuit can be very briefly summari;ed as follows.

The complementary p()S and n()S transistors (> and (* supply base currents to the bipolar

transistors and thus act as 2trigger2 devices for the bipolar output stage. The bipolar transistor 1 & can

effectively pull up the output voltage in the presence of a large output capacitance, whereas 1 pulls

down the output voltage, similar to the well#known totem pole configuration. epending on the logic

level of the input voltage, either (* or (> can be turned on in steady state, therefore assuring a fully

complementary pushpull operation mode for the two bipolar transistors. In this very simplistic

configuration, two resistors are used to remove the base charge of the bipolar transistors when theyare in cut#off mode.

In this circuit resistors provide better improved o@p swing of voltage .

To reduce the turn#off times of the bipolar transistors during switching, two minimum#si;e n()S

transistors -( & and ( are usually added to provide the necessary base discharge path, instead of

the two resistors-resistors are space consuming. The resulting si/#transistor inverter circuit, shown in

Fig.,below is the "ost +i)el. use) con*entional $iCMOS in*erter confiuration/


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Con*entional $iCMOS in*erter/

$iCMOS NOR'

Figure shows the circuit diagram of a i'()S *)+ gate. 6ere, the base of the bipolar pull#up

transistor 1& is being driven by two series#connected >mos transistors. Therefore, the pull#up device

can be turned on only if both of the inputs are logic#low. The base of the bipolar pull#down transistor

1 is driven by two parallel#connected n()S transistors. Therefore, the pull#down device can be

turned on if either one or both of the inputs are logic#high. !lso, the base charge of the pull#up device

is removed by two minimum#si;e n()S transistors connected in parallel between the base node and

the ground. *otice that only one n()S transistor, (, is being used for removing the base charge

of 1, when both inputs are logic#low.


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$iCMOS NAN%'

Figure shows the circuit diagram of a i'()S *!* gate. In this case, the base of the bipolar

pull#up transistor 1 I is being driven by two parallel#connected >mos transistors. 6ence, the pull#up

device is turned on when either one or both of the inputs are logic#low. The bipolar pull#down

transistor 1, on the other hand, is driven by two series#connected n()S transistors between the

output node and the base. Therefore, the pull#down device can be turned on only if both of the inputs

are logic#high. For the removal of the base charges of 1& during turn#off, two series#connected n()S

transistors are used, whereas only one n()S transistor is utili;ed for removing the base charge of 1.

Cmos Sequential Circuits

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