KTH/ESDlab/HT 06/06/22 1 CMOS Arithmetic Circuits
Cmos Arithmetic Circuits
Nov 30, 2014
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KTH/ESDlab/HT 04/09/23 1
CMOS Arithmetic Circuits
KTH/ESDlab/HT 04/09/23 2
Multiplication of numbers
KTH/ESDlab/HT 04/09/23 3
Datapath circuit techniquesfor adders
KTH/ESDlab/HT 04/09/23 4
Binary adder
KTH/ESDlab/HT 04/09/23 5
Binary adder
KTH/ESDlab/HT 04/09/23 6
Special trick for reducing No of transistor
Cout = AB + CIN.(A + B)
SUM = ABCCN + C’OUT (A + B + CIN)
The advantage of these type realization is that transistor count is less as compared to earlier realization using expression of slide 5.
KTH/ESDlab/HT 04/09/23 7
CMOS full adder
KTH/ESDlab/HT 04/09/23 8
Mirror Adders
As discussed is class, Mirror adder circuit is having symmetrical N block and P block.
KTH/ESDlab/HT 04/09/23 9
Ripple carry adder
KTH/ESDlab/HT 04/09/23 10
Pipelined adder
KTH/ESDlab/HT 04/09/23 11
Carry bypass adder
KTH/ESDlab/HT 04/09/23 12
Carry bypass adder
KTH/ESDlab/HT 04/09/23 13
Linear carry select adder
KTH/ESDlab/HT 04/09/23 14
Linear carry select adder: critical path
KTH/ESDlab/HT 04/09/23 15
Carry look-ahead adder
KTH/ESDlab/HT 04/09/23 16
Carry look-ahead circuit structures
KTH/ESDlab/HT 04/09/23 17
Carry save (CSA) and carry propagate (CPA) adders
KTH/ESDlab/HT 04/09/23 18
Adder delays
KTH/ESDlab/HT 04/09/23 19
Adder delays summary
KTH/ESDlab/HT 04/09/23 20
Datapath circuit techniquesfor multipliers
KTH/ESDlab/HT 04/09/23 21
Multiplier definition
KTH/ESDlab/HT 04/09/23 22
Binary multiplication
KTH/ESDlab/HT 04/09/23 23
Indirect multiplication
KTH/ESDlab/HT 04/09/23 24
Array multiplier
KTH/ESDlab/HT 04/09/23 25
MxN array multiplier critical path
KTH/ESDlab/HT 04/09/23 26
Carry ripple vs. carry save array multiplier
KTH/ESDlab/HT 04/09/23 27
Carry save multiplier
KTH/ESDlab/HT 04/09/23 28
Adder cells in array multiplier
KTH/ESDlab/HT 04/09/23 29
Array multiplier floorplan
KTH/ESDlab/HT 04/09/23 30
Wallace tree multiplier
KTH/ESDlab/HT 04/09/23 31
Wallace tree multiplier
KTH/ESDlab/HT 04/09/23 32
Wallace tree multiplier
KTH/ESDlab/HT 04/09/23 33
Dadda tree multiplier
KTH/ESDlab/HT 04/09/23 34
Serial-serial multiplier
KTH/ESDlab/HT 04/09/23 35
Serial-parallel multiplier
KTH/ESDlab/HT 04/09/23 36
Parallel vs. serial multipliers
KTH/ESDlab/HT 04/09/23 37
Parallel vs. serial multipliers
KTH/ESDlab/HT 04/09/23 38
Multiplier performance
KTH/ESDlab/HT 04/09/23 39
Multiplier performance
KTH/ESDlab/HT 04/09/23 40
Multiplier summary
KTH/ESDlab/HT 04/09/23 41
Other datapath elements
KTH/ESDlab/HT 04/09/23 42
Binary shifter
KTH/ESDlab/HT 04/09/23 43
Barrel shifter
KTH/ESDlab/HT 04/09/23 44
4x4 barrel shifter
KTH/ESDlab/HT 04/09/23 45
Logarithmic shifter
KTH/ESDlab/HT 04/09/23 46
Power considerations in datapath structures
KTH/ESDlab/HT 04/09/23 47
Reducing supply voltage
KTH/ESDlab/HT 04/09/23 48
Reducing supply voltage
KTH/ESDlab/HT 04/09/23 49
Architecture trade-offs: reference datapath
KTH/ESDlab/HT 04/09/23 50
Parallel datapath
KTH/ESDlab/HT 04/09/23 51
Pipelined datapath
KTH/ESDlab/HT 04/09/23 52
Datapath architecture summary
KTH/ESDlab/HT 04/09/23 53
Glitching in NOR chain
KTH/ESDlab/HT 04/09/23 54
Glitching in RCA
KTH/ESDlab/HT 04/09/23 55
Switching activity in adders
KTH/ESDlab/HT 04/09/23 56
Switching activity in multipliers
KTH/ESDlab/HT 04/09/23 57
Layout strategy for datapath
KTH/ESDlab/HT 04/09/23 58
Layout strategy for datapaths
KTH/ESDlab/HT 04/09/23 59
Cell area: 2 vs. 3 metal layer process
KTH/ESDlab/HT 04/09/23 60
Summary
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