CMOS Analog Circuitshome.iitk.ac.in/~baquer/L20_Class_AB.pdfClass AB Buffer Amplifier B. Mazhari, IITK G-Number 83 C.W. Lu,” High-Speed Class AB Buffer Amplifiers with Accurate Quiescent

CMOS Analog Circuits

C fL20: Class AB amplifier (24.10.2013)

B Mazhari

G-NumberB. Mazhari, IITK56

B. MazhariDept. of EE, IIT Kanpur

Output Stage

+3.3V

v0321

vS

R = 1K-3.3V RL 1K

Low output Resistance; Rail-to-Rail voltage swing

Low distortion; High efficiency


CS Amplifier

VDD = 3.3V 3.3V

RD0

+3

-3

Vbias2

M2

(W/L)P

1kvO vO

2

(W/L)N

VSS = -3.3VvinvS Vbias1

-3.3V

M1

DDV 3DSQI mA33DD

DSQD

VI mAR

3DSQI mA


CD Amplifier

VDD = 3.3 V = 3 3DD

v

VDD = 3.3

m1VBias1

vin RSRL = 1K

vO

RL = 1K

vO

m2

Bias1

vin

VBias2

VSS =-3.3 VSS =-3.3

m2in

3.3 3 3I A3.3 ~ 33100biasI mA 3.3BiasI mA


Class A amplifiers3.3V

VDD

VBias2m

Vbias2

M2VBias1 RL=1k

vO

m2

vS Vbias1 M1

vO

1kvin

VSS

m1

S b as

-3.3V

In both CS and CD amplifiers the transistor remains ON and conductingIn both CS and CD amplifiers, the transistor remains ON and conductingthroughout out the ac cycle. To achieve this the bias current must be larger thanthe ac drain current.

d dI I i di I di i I Ids ds Bias dsI I i ds Biasi I L ds Biasi i I

0.5 0.5L o L DD BiasP v i V I o DDv V

IBias ids

1 Tss SS ds ss BiasP V I dt V I

T dd DD BiasP V I

G-NumberB. Mazhari, IITK60t

0T

sup0.25L

ply

PP

VDD

Amplifiers with negligible stand-by power dissipationIds

vO

VBias2m2 Even when no input is

applied, power is drawnIBias ids

v

VBias1

m1

RL

pp pfrom the supply.

tA ffi i t lifi ill t k f th lvin

VSS An efficient amplifier will take power from the supplyonly when power is to be delivered to the load.

Bi t t b !!Bias current must be zero !!

VBias1

vO

R

Ids 22 max

0

14

Tds L

L ds Li RP i dt R

T

vin

Bias1

V

m1

RL

ti

0

VSS tids

max1 Tss dsV i

max max0 785ds L oi R v


max

0

1 ss dsss SS ds

V iP V I dt

T

max max0.7854

ds L oSS SSV V

vO

How do we reduce distortion? VDD = 3.3

m2VBias2

VBias1

O

m1

RL

vO

RL

m2

vin

I vinVSS IL

IL

tt t

VDD = 3.3

m2VBias2

Each Transistor conducts forvO

RLvin

only half the cycle resulting inClass B operation

G-NumberB. Mazhari, IITK62VSS

m1VBias1

Class B push-pull amplifier

VDD = 3.3

Vm2

VBias2

vO

mRL

V

vin

V

m1VBias1

VSS

During positive cycle, M2 pushes current into the load, while during the


During positive cycle, M2 pushes current into the load, while during thenegative cycle, M1 pull current from the load and hence the name Push-Pullamplifier

VDD = 3.3

0Vm2

700/1Symmetrical nmos and pmos with identical

RLvin

m2

vO700/1

y pparameters and no body effect for nmos.

VSS

m1

L

0V

Cross-over distortion



Note the odd harmonics

VDD = 3.3

m20.7V

vO

RL

m2

vin

VSS

m1

L

-0.7V

P 24 WPsby~24 µW 2.14 49.1%@ 2.34.26

mW VmW

max0 785 ov 0.785SSV

For output swing of 3V, efficiency increase to 71.6%


c ease o 6%

VDD = 3.3

m20.8V

vO

RL

m2

vin

VSS

m1

L

-0.8V

P 2 92 WPsby~2.92mW

2.14 43.6%@ 2.24.9

mW VmW

For output swing of 3V, efficiency


yincrease to 68%

VDD = 3.3

0Vm2

700/1

m1

RLvin

0V

vO700/1

VDD = 3.3

VSS

vO

m20.7V

VSS

m1

RLvin

-0.7V

VDD = 3.3

VSS

vO

DD

m20.8V


VSS

m1

RLvin

-0.8V

Distortion can also be reduced by employing negative feedback

3.3V

M2

700/1

3 3V

M11k

vO

vS

-100100 700/1

-3.3V


0.5um nmos and pmos Tr.With body effect

VDD = 3.3

0Vm2

700/1

mRL

vin

vO700/1

VSS

m10V

Not the strong secondharmonic distortion aswell resulting fromunequal swings inpositive and negativep gdirections..


VDD = 3.3

m20.7V

vO

RL

m2

vin

VSS

m1

L

-0.86V

P 0Pstb~0


VDD = 3.3

m21.0V

vO

RL

m2

vin

VSS

m1

L

-1.16V

P 0 6 WPstb ~0.6mW


VDD = 3.3

1.0V

vO

m2

VSS

m1

RLvin

-1.16V

VSS


Class AB Push-Pull amplifier using CS stage

VDD = 3.3

m2VBias2

vO

m2

vO

RLvin

m1

L

VBias1

VSS


Symmetrical nmos and pmos with identical parameters and no body effect fornmos.

VDD = 3.3

2.6V 700/1

m2

vO

vin RL=1k

700/1

m2

VSS

m1-2.6V




VDD = 3.3

VBias2

vO

m2

m1

RL

VBias1

vin

VSS

VDD = 3.3

VBias2

VDD = 3.3

m2VBi 2

vO

m2m2VBias2

vO

m1

RL

VBias1

V

m1VBias1vin


VSS VSS

Need to address biasing

Biasing Of Class AB Output Stage

VBias2

VDD VDD

m2~ 0.7DDV

vO

m2Bias2

vin VBias3

m1

RL

VBias1

vOvin

VBias4

VSS m1

~ 0.7SSV

VSS m2VBias2

vO


m1VBias1vin

VDD VDD m2

VBias3

m2vOvin

as3

VBias4 vin VBias3m1

VSS

vO

VBias4

m1

VSS m2VBias2

m

vO


m1VBias1vin

VDD

VDD m2

DD

m2

vO

vin VBias3

vVBias3

m1

vO

VBias4

vOvin VBias4

VSS m1

VSS


VDD

m6 m14

vO

VBias3

VBias4

m7 m15

VSS

CS i St Class AB Output Stage


CS gain Stage Class AB Output Stage

Class AB Buffer Amplifier


C.W. Lu,” High-Speed Class AB Buffer Amplifiers with AccurateQuiescent Current Control



Class AB CMOS Pseudo-Source Buffer Amplifier

VDD

VDD

M6

M6

A1

_

+

V V

Vb1Vin Vout

A1

+ RL

Vin Vout

Vb2 A2

RL

_

M6A

Vb2

M6A

2

VSS VSS


M5A

VDD

VBias2M6

M1A M2A

Folded cascode LoadVBias2

M1A M2A

VoutVSS

VDD

M1 M2

M6AFolded cascode Load

Vin

M5

Folded cascode Load

VSS

VBias1

(a)


Positive error amplifier

M44 M45

M52

M44 M45

M54Vin-Vin+

Ibn

M42 M43

M55 M56

VBIAS

M40 M41


CMOS Analog Circuitshome.iitk.ac.in/~baquer/L20_Class_AB.pdfClass AB Buffer Amplifier B. Mazhari, IITK G-Number 83 C.W. Lu,” High-Speed Class AB Buffer Amplifiers with Accurate Quiescent

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