CM-5000 VPX ETHERNET SWITCH INTERFACE CONTROL DOCUMENT · OnTime Networks AS Type of document INTERFACE CONTROL DOCUMENT Distribution Product Date Reg.No. Rev Page OnTime Proprietary

OnTime Networks AS

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INTERFACE CONTROL DOCUMENT

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OnTime Proprietary CM-5000 2015-08-26 7

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PJK ØH

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CM-5000 VPX ETHERNET SWITCH INTERFACE CONTROL DOCUMENT

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1 Document information

Distribution Product Date Revision

7

OnTime Proprietary CM-5000 2014-08-26 Issued by

Approved

PJK ØH

Signatures for original release Author: _____________________________________ _________________________ Pål-Jørgen Kyllesø Date Approval: _____________________________________ _________________________ Øyvind Holmeide Date Document release: ________________________________ _________________________ Date

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Table of contents 1 DOCUMENT INFORMATION ......................................................................................... 2 2 DOCUMENT HISTORY ................................................................................................... 4 3 ABBREVIATIONS AND DEFINITIONS ......................................................................... 5

3.1 ABBREVIATIONS .................................................................................................................... 5 4 MANUFACTURER ............................................................................................................ 6 5 PRODUCT OVERVIEW ................................................................................................... 6

5.1 CM-5000 KEY FEATURES ....................................................................................................... 7

5.2 POWER SUPPLY ...................................................................................................................... 8 5.3 MANAGEMENT ...................................................................................................................... 8 5.4 COMPLIANCE ......................................................................................................................... 8 6 DESCRIPTION AND IDENTIFICATION OF PRODUCT ARTICLES ........................ 8 6.1 DESCRIPTION OF PART NUMBERS ............................................................................................ 9

7 TECHNICAL SPECIFICATION .................................................................................... 10 7.1 POWER SUPPLY .................................................................................................................... 10 7.2 MECHANICS ........................................................................................................................ 10 7.3 WEIGHT .............................................................................................................................. 10 7.4 HARDWARE BLOCK DIAGRAM .............................................................................................. 10

7.5 EQUIPMENT LABELING AND IDENTIFICATION ........................................................................ 11 7.6 MANAGEMENT .................................................................................................................... 11 7.6.1 SNMP .............................................................................................................................................................. 11 7.6.2 HTTP/HTTPS .................................................................................................................................................. 12 7.6.3 CLI .................................................................................................................................................................. 12 7.6.4 IPSetWeb ......................................................................................................................................................... 12

8 INTERFACE SPECIFICATIONS ................................................................................... 14 8.1 PINOUT P0 ........................................................................................................................... 15 8.2 PINOUT P1 ........................................................................................................................... 16 8.3 PINOUT P2 ........................................................................................................................... 17 8.4 CONFIGURATION MODE 1 – 16 X SGMII + 2 X XAUI + 2X 10GBASE-T ............................... 19

8.5 CONFIGURATION MODE 2 – 20 X SGMII+ 1 X XAUI + 1 X KR + 2 X 10GBASET .................... 20 8.6 CONFIGURATION MODE 3 – 24 X SGMII+ 2 X KR + 2 X 10GBASET ....................................... 21

8.7 CONFIGURATION MODE 4 – 24 X SGMII+ 4 X KR ................................................................. 22

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2 Document History Rev Date Description Note 07 2015-08-26 Version 0.7 Management info added. Power estimations added. 06 2015-08-19 Version 0.6 Pinout error in overview figure. Replaced figure 05 2015-08-18 Version 0.5 Product articles, interfaces section updated 04 2015-07-30 Version 0.4 Wrong color for the “Not used” section of Config op.4 03 2015-07-29 Version 0.3 Pinout descriptions added 02 2015-07-28 Version 0.2 Pinout updated 01 2015-06-22 Version 0.1

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3 Abbreviations and definitions

3.1 Abbreviations ATP Acceptance Test Procedure ATR Acceptance Test Report BMC Best Master Clock CPU Central Processing Unit DDP Declaration of Design and Performance ESS Environmental Stress Screening FAI First Article Inspection GMC Grand Master Clock GPI General Purpose Input GPIO General Purpose Input Output GPO General Purpose Output GPS Global Positioning System IP Ingress Protection MAC Media Access Controller MII Media Independent Interface OC Ordinary Clock PCB Printed Circuit Board PPS Pulse Per Second PTP Precision Time Protocol SC Slave Clock TC Transparent Clock FP Fat Pipe TP Thin Pipe UTP Ultra Thin Pipe

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4 Manufacturer OnTime Networks AS Frysjaveien 33C, 0884 Oslo, Norway Organization number: 989 524 879 Web: www.ontimenet.com Email: [email protected] Phone: +47 22090303 Fax: +47 22090310

5 Product overview OnTime Networks’ CloudberryMIL CM-5000 Series is a high-performance 3U VPX Gigabit Ethernet Switch line for embedded and harsh environment applications. The switch is compatible with the switch profile: SLT3-SWH-2F24U. The CM-5000-MIL 3U VPX Ethernet switch series is compliant with the latest VICTORY specification as an Infrastructure Switch, with a powerful set of networking features to implement highly advanced in-vehicle network architectures. VICTORY is short for Vehicular Integration for Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance/Electronic Warfare (C4ISR/EW) Interoperability. This single-slot switch solution provides the essential foundation to implement a VICTORY architecture in today’s modern networked and SWaP sensitive vehicles.

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5.1 CM-5000 key features

• Rugged 3U VPX Gigabit and 10GBE Ethernet Switch • Up to 24 Gigabit Ethernet Ports:

· 12 x 1000BASE-KX/SGMII · 16 x 1000BASE-KX/SGMII · 24 x 1000BASE-KX/SGMII

• Up to four 10-Gigabit Ethernet Ports: · 2 x XAUI and 2 x 10GBASE-T, or · 1 x XAUI, 1 x KR and 2 x 10GBASE-T, or · 2 x KR and 2 x 10GBASE-T, or · 4 x KR

• Conduction cooled • VITA 46, and VITA 65 compliant • Full Wire-speed performance • IEEE1588-2002/2008 (PTPv1/PTPv2) • System reference clock output (configurable) • Layer 3 switch with static IP routing • Network redundancy: RSTP/STP protocol • Network management: Web, telnet, CLI and SNMP v1/v2/v3 • IGMP snooping (IGMP v1/v2/v3) • Static multicast filters • 802.1Q VLAN switch with 32K MACs and 4K VLANs • 8 QoS Classes • Enhanced security • Port mirroring to aid in system development • Jumbo Frame Support to 9,600 bytes • Event notification: Syslog and SNMP trap • Policing with storm control and MC/BC protection • Link aggregation (IEEE 802.3ad)

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5.2 Power supply The VPX backplane connector supports the following main supplies: 5V

5.3 Management • CPU is manageable via all Ethernet ports in available in the VPX backplane • RS232 console in P2 User defined section. • Separate on-board Management port available as a mounting option

5.4 Compliance The switch board is compliant to the following standards:

• VITA 46.0 VPX Base Specification • ANSI/VITA 65-2010 OpenVPX System Specification

6 Description and identification of product articles CU-5012F0-12x1G-VPX 12x1000BASE-KX/SGMII, unmanaged

CM-5012F0-12x1G-VPX 12x1000BASE-KX/SGMII, managed

CU-5020F0-12x1G-VPX 20x1000BASE-KX/SGMII, unmanaged

CM-5020F0-16x1G-2x10G-2xXAUI-VPX 16x1000BASE-KX/SGMII, 2x10GBase-T,

2xXAUI, managed

CM-5020F0-20x1G-VPX 20x1000BASE-KX/SGMII, managed

CM-5022F0-20x1G-1x10G-1xXAUI-VPX 20x1000BASE-KX/SGMII, 1x10GBase-T, 1xXAUI, managed

CM-5023F0-20x1G-2x10G-1xXAUI-VPX 20x1000BASE-KX/SGMII, 2x10GBase-T, 1xXAUI, managed

CM-5024F0-20x1G-2x10G-1xXAUI-1xKR-VPX

20x1000BASE-KX/SGMII, 2x10GBase-T, 1xXAUI, 1x10GBase-KR, managed

CM-5028F0-20x1G-2x10G-2xKR-VPX 24x1000BASE-KX/SGMII, 2x10GBase-T, 2x10GBase-KR, managed

CM-5028F0-20x1G-4xKR-VPX 24x1000BASE-KX/SGMII, 4x10GBase-KR, managed

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6.1 Description of part numbers

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7 Technical Specification

7.1 Power supply The only power used is the 5v power supply Power consumption Idle (no links) <TBD> Typical 25W Maximum 31W

7.2 Mechanics 3U VPX board occupying 1 slot. 100 mm (H) x 160 mm (D)

7.3 Weight <TBD>

7.4 Hardware block diagram The main building blocks of the CM-5000 platform are shown below.

Figure 1, hardware block diagram

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7.5 Equipment labeling and identification

• Manufacturer: OnTime Networks • Product: CM-5000 series • Power led: Power • On led: On • Management • Console • Serial number: S/N XXXXXXXXXX

<IMAGE>

7.6 Management The CM5000 switch platform supports management based on:

• SNMP • HTTP and CLI for switch management • IPSetWeb for Management

See the Cloudberry PTP and Switch Management User Guide for details regarding the above management protocols and other supported protocols such as PTP, IGMP snooping and network redundancy (RSTP).

7.6.1 SNMP Management via the Simple Network management protocol is available on all switch ports unless the CPU is isolated via VLAN or other security protocols. SNMP settings can be configured via the Web interface. The switch supports the following MIBs:

• OnTime private MIB • RFC 2674 VLAN MIB • IEEE 802.1Q Bridge MIB 2008 • RFC 2819 RMON (Group 1, 2. 3 & 9) • RFC 1213 MIB II • RFC 1215 TRAPS MIB • RFC 4188 Bridge MIB • RFC 4292 IP Forwarding Table MIB • RFC 4293 Management Information Base for the Internet Protocol (IP) • RFC 5519 Multicast Group Membership Discovery MIB • RFC 4668 RADIUS auth. Client MIB

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• RFC 4670 RADIUS Accounting MIB • RFC 3635 Ethernet-like MIB • RFC 2863 Interface Group MIB using SMI v2 • RFC 3636 802.3 MAU MIB • RFC 4133 Entity MIB version 3 • RFC 4878 Link OAM MIB • RFC 3411 SNMP Management Frameworks • RFC 3414 User-based Security Model for SNMPv3 • RFC 3415 View-based access Control Model for SNMP • RFC 2613 SMON VLAN Statistics • RFC 2613 SMON – PortCopy • IEEE 802.1 MSTP MIB • IEEE 802.1AB LLDP-MIB • IEEE 802.3ad (LACP MIB included in a clause of the STD) • IEEE 802.1X (PAE MIB included in a clause of the STD) • TIA 1057 LLDP-MED ( MIB is part of the STD)

7.6.2 HTTP/HTTPS Management via Web is available on all switch ports if not disabled or the CPU is not isolated via VLAN or other security protocols.

7.6.3 CLI SSH Console is available on all switch ports if not disabled or the CPU is isolated via VLAN or other security protocols. A serial console is also available in the backplane. The login is the same whether SSH, telnet or Serial console is used. The default login credentials are as follows: IP Address: 192.168.10.1 User Name: admin Password: admin123 The CLI is documented in the user manual.

7.6.4 IPSetWeb IPSet is a Windows based tool for discovery and management of OnTime Switches. When enabled for scanning IPSet will automatically detect OnTime devices on your local network. Summary of features:

• Scan for devices • Set IP address • Configure multiple devices • Get time/firmware versions of multiple devices

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IPSetWeb after startup

Scan for devices Go to Options->Enable polling

Select the interface or all interfaces on which IPSet shall scan for devices. The detected devices will appear in the left tree structure:

Right click or double click on a device in order to manage the device. You will be asked for a login password and the web interface of the device will appear in the right section. The detailed management of the switch is described in the user manual.

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8 Interface specifications The VPX backplane connector is based on the OpenVPX switch profile: SLT3-SWH-2F24U, but four of the UTPs on P2 are changed to thin pipes.

Key

Control plane

2 Fat pipes XAUI

4 Ultra thin pipes for 10G KR or 1G SGMII

4 Ultra thin pipes for SGMII/1000BASE-KX

12 Ultra thin pipes for SGMII/1000BASE-KX

2 Thin pipes for 10G BASE-T

Key

S

E

S

E

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8.1 Pinout P0

Row G Row F Row E Row D Row C Row B Row A

1 VDD_VS1 VDD_VS1 VDD_VS1 No pad VDD_VS2 VDD_VS2 VDD_VS2



4 SM2 SM3 GND M12VAUX GND VPX_SYSRESETn VPX_NVMRO

5 GAP GA4 GND 3V3_AUX_IN GND VPX_SM_SCL VPX_SM_SDA

6 GA3 GA2 GND P12VAUX GND GA1 GA0

7 VPX_TCK GND VPX_TDO VPX_TDI GND VPX_TMS VPX_TRSTn

8 GND VPX_REFCLKN VPX_REFCLKP GND VPX_RESBUSN VPX_RESBUSP GND

Signal descriptions

Signal Direction Name Description

VPX_RESBUSN/P Output PPS_out Pulse per second output

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8.2 Pinout P1 Row G Row F Row E Row D Row C Row B Row A

1 NOT used GND SFP24_TxD_n SFP24_TxD_p GND SFP24_RxD_n SFP24_RxD_p

2 GND SFP23_TxD_n SFP23_TxD_p GND SFP23_RxD_n SFP23_RxD_p GND

3 VPX_VBAT GND SFP22_TxD_n SFP22_TxD_p GND SFP22_RxD_n SFP22_RxD_p


5 VPX_SYSCON GND SFP20_TxD_n SFP20_TxD_p GND SFP20_RxD_n SFP20_RxD_p




9 VPXP1SE4 GND SFPplusD_TxD_n SFPplusD_TxD_p GND SFPplusD_RxD_n SFPplusD_RxD_p

10 GND SFPplusC_TxD_n SFPplusC_TxD_p GND SFPplusC_RxD_n SFPplusC_RxD_p GND

11 VPXP1SE5 GND SFPplusB_TxD_n SFPplusB_TxD_p GND SFPplusB_RxD_n SFPplusB_RxD_p

12 GND SFPplusA_TxD_n SFPplusA_TxD_p GND SFPplusA_RxD_n SFPplusA_RxD_p GND

13 VPXP1SE6 GND SFP16_TxD_n SFP16_TxD_p GND SFP16_RxD_n SFP16_RxD_p




Signal descriptions – Single ended

Signal Wafer Direction Name Description

VPXP1SE4 9 Input FE_INT Interrupt from FE PHYs

VPXP1SE5 11 Output FE_1588CLK PTP Clk output to PHYs

VPXP1SE6 13 Input FE_PPSIN External PPS Input

Signal descriptions – Differential


SFP24 to SFP21 1-4 Input/Output XAUI Port 3 Fat pipe for XAUI (XAUI 3 Lane 0-3)

SFP20 to SFP17 4-8 Input/Output XAUI Port 2 Fat pipe for XAUI (XAUI 2 Lane 0-3)

SFPPlusD 9 Input/Output Port 36 Ultra thin pipe for 10G KR

SFPPlusC 10 Input/Output Port 35 Ultra thin pipe for 10G KR

SFPPlusB 11 Input/Output Port 34 Ultra thin pipe for 10G KR

SFPPlusA 12 Input/Output Port 33 Ultra thin pipe for 10G KR

SFP16 13 Input/Output Port 16 Ultra Thin pipe for SGMII/1000BASE-KX




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8.3 Pinout P2














13 VPXP2SE6 GND MxBN0 MxBP0 GND MxAN0 MxAP0

14 GND MxDN0 MxDP0 GND MxCN0 MxCP0 GND



Signal descriptions – single ended


VPXP2SE0 1 Output FE_MDC MDIO Interface Clock

VPXP2SE1 3 Bidirectional FE_MDIO MDIO Interface Data

VPXP2SE2 5 Output FE_232TX Serial console, output of switch

VPXP2SE3 7 Input FE_232RX Serial console, input of switch

VPXP2SE4 9 Output FE_SPI_CSn Frontend board SPI, Chip select

VPXP2SE5 11 Input FE_SPI_MISO Frontend board SPI, MISO

VPXP2SE6 13 Output FE_SPI_MOSI_SID Frontend board SPI, MOSI (*)

VPXP2SE7 15 Output FE_SPI_CLK Frontend board SPI, Clock

(*) This pin has dual functionality. The SID is read once at startup, then it is used as SPI interface to the frontend/mezzanine board.

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Signal descriptions – differential 8 Ultra thin pipes pipes for SGMII/1000BASE-KX: SFP1 to SFP12 2 Thin pipes for 10Gbase-T: MxA,MxB,MxC,MxD














MxA/B/C/D 0 13-14 Input/Output TBD Thin pipe for 10GBASE-T

MxA/B/C/D 1 15-16 Input/Output TBD Thin pipe for 10GBASE-T

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8.4 Configuration mode 1 – 16 x SGMII + 2 x XAUI + 2x 10GBASE-T Pinout P1


















Not used 2 x XAUI 4 x SGMII

Pinout P2


















2 x 10GBASE-T 12 x SGMII

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8.5 Configuration mode 2 – 20 x SGMII+ 1 x XAUI + 1 x KR + 2 x 10GBaseT Pinout P1


















Not used 1 x XAUI 8 x SGMII 1 x KR

Pinout P2



















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8.6 Configuration mode 3 – 24 x SGMII+ 2 x KR + 2 x 10GBaseT Pinout P1


















Not used 12 x SGMII 2 x KR

Pinout P2



















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8.7 Configuration mode 4 – 24 x SGMII+ 4 x KR Pinout P1


















12 x SGMII 4 x KR

Pinout P2


















Not used 12 x SGMII

CM-5000 VPX ETHERNET SWITCH INTERFACE CONTROL DOCUMENT · OnTime Networks AS Type of document INTERFACE CONTROL DOCUMENT Distribution Product Date Reg.No. Rev Page OnTime Proprietary

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