Application Report SLUA371 – September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x Lingyin Zhao........................................................................................................ PMP Portable Power ABSTRACT Design of the loop compensator is one of the key challenges in the circuit design of a switching charger. This application report presents the internal control loop operation of the bq2472x/3x as well as the external compensator design guideline. The modeling of the nonlinear behavior of a switching charger is based on the state space average model. A design example based on practical specifications is demonstrated. Contents 1 Buck-Type Charger Power Stage Small-Signal Model ........................................ 2 2 bq2472x/3x Control-Loop Model and Compensation Design ................................. 6 3 Design Example .................................................................................... 9 4 Reference .......................................................................................... 19 List of Figures 1 The Power Stage of a Buck-Type Charger ..................................................... 2 2 Three-Terminal Model of a PWM Switch in CCM .............................................. 2 3 Control-to-Output Small-Signal Model in CCM ................................................. 3 4 Three-Terminal Model of a PWM Switch in DCM .............................................. 4 5 Control-to-Output Small-Signal Model in DCM ................................................. 5 6 PWM and Error Amplifiers Block of bq2472x/3x................................................ 6 7 Simplified Control-Loop Block Diagram.......................................................... 7 8 A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions ... 8 9 A Type III Compensator ........................................................................... 8 10 Bode Plot of a Typical Type III Compensator ................................................... 8 11 Control-to-Output-Voltage Transfer Function .................................................. 10 12 Control-to-Charge-Current Transfer Function ................................................. 11 13 Control-to-Input-Current Transfer Function .................................................... 12 14 Transfer Function of G vd , the Compensator and the Entire Voltage Loop Gain .......... 13 15 Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)................................. 14 16 Output-Voltage Loop Gain T V (CCM) ........................................................... 15 17 Charge-Current Loop Gain T is (CCM) .......................................................... 16 18 Input-Current Loop Gain T ii (CCM) .............................................................. 17 19 Output-Voltage Loop Gain T V (DCM) ........................................................... 18 20 Input-Current Loop Gain T ii (DCM) ............................................................. 19 SLUA371 – September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 1 Submit Documentation Feedback
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Application ReportSLUA371–September 2006
Closed-Loop Compensation Design of a SynchronousSwitching Charger Using bq2472x/3x
Lingyin Zhao........................................................................................................ PMP Portable Power
ABSTRACT
Design of the loop compensator is one of the key challenges in the circuit design of aswitching charger. This application report presents the internal control loop operation ofthe bq2472x/3x as well as the external compensator design guideline. The modeling ofthe nonlinear behavior of a switching charger is based on the state space averagemodel. A design example based on practical specifications is demonstrated.
Contents1 Buck-Type Charger Power Stage Small-Signal Model ........................................ 22 bq2472x/3x Control-Loop Model and Compensation Design ................................. 63 Design Example .................................................................................... 94 Reference .......................................................................................... 19
List of Figures
1 The Power Stage of a Buck-Type Charger ..................................................... 22 Three-Terminal Model of a PWM Switch in CCM .............................................. 23 Control-to-Output Small-Signal Model in CCM ................................................. 34 Three-Terminal Model of a PWM Switch in DCM .............................................. 45 Control-to-Output Small-Signal Model in DCM ................................................. 56 PWM and Error Amplifiers Block of bq2472x/3x................................................ 67 Simplified Control-Loop Block Diagram.......................................................... 78 A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions ... 89 A Type III Compensator ........................................................................... 810 Bode Plot of a Typical Type III Compensator................................................... 811 Control-to-Output-Voltage Transfer Function.................................................. 1012 Control-to-Charge-Current Transfer Function ................................................. 1113 Control-to-Input-Current Transfer Function .................................................... 1214 Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain .......... 1315 Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)................................. 1416 Output-Voltage Loop Gain TV (CCM)........................................................... 1517 Charge-Current Loop Gain Tis (CCM) .......................................................... 1618 Input-Current Loop Gain Tii (CCM).............................................................. 1719 Output-Voltage Loop Gain TV (DCM)........................................................... 1820 Input-Current Loop Gain Tii (DCM) ............................................................. 19
SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 1Submit Documentation Feedback
1 Buck-Type Charger Power Stage Small-Signal Model
Q2
VIN
ISL
Q1
RC2 Z
L
RL VORSNS
C2
IL
RC1
C1
1.1 Continuous Conduction Mode (CCM) Small-Signal Model
Q1
Q2
ca
p
(a) a PWM Switch
a c
p
1 D1I dC
^
(b) Small-Signal Model
Vap
Dˆd
Buck-Type Charger Power Stage Small-Signal Model
A typical stage of a synchronous buck-type switching battery charger is shown in Figure 1.
Figure 1. The Power Stage of a Buck-Type Charger
The small-signal model is obtained from the relationships among the perturbation in average terminalquantities at a given dc operating point. The model is different under continuous conduction mode (CCM)and discontinuous conduction mode (DCM).
The average values of the switch network terminal waveforms can be determined in terms of the converterstate variables and the converter independent inputs. The basic assumption is made that the natural timeconstants of the converter network are much longer than the switching period Ts. This assumptioncoincides with the requirement for small switching ripple. The resulting averaged model predicts thelow-frequency behavior of the system, while neglecting the high-frequency switching harmonics [1]. Thethree-terminal model for a PWM switch network in CCM is illustrated in Figure 2.
Figure 2. Three-Terminal Model of a PWM Switch in CCM
To perform the CCM small-signal analysis, the PWM switch in the buck converter is substituted with thethree-terminal model in CCM and Vin is shorted, as shown in Figure 3.
2 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback
To perform the DCM small-signal analysis, the PWM switch in the buck converter is substituted with thethree-terminal model in DCM and Vin is shorted, as shown in Figure 5.
Figure 5. Control-to-Output Small-Signal Model in DCM
In a buck converter operating in DCM, the following equations can be obtained:
The open-loop, control-to-output-voltage transfer function is given as:
The open-loop, control-to-input-current transfer function is given as:
in which,
SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 5Submit Documentation Feedback
2 bq2472x/3x Control-Loop Model and Compensation Design
2.1 bq2472x/3x Control-Loop Model
bq2472x/3x Control-Loop Model and Compensation Design
The PWM and error amplifiers block of bq2472x/3x is illustrated in Figure 6. It consists of three feedbackloops: output-voltage loop, charge-current loop, and input-current loop (DPM loop). However, only one ofthem dominates at one time. The simplified control-loop block diagram is depicted in Figure 7.
Figure 6. PWM and Error Amplifiers Block of bq2472x/3x
6 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback
Tv Gvd FG A(s) FM (44)T is Gisd FG A(s) FM (45)T ii Giid FG A(s) FM (46)
bq2472x/3x Control-Loop Model and Compensation Design
Figure 7. Simplified Control-Loop Block Diagram
In Figure 7, FG is the feedback gain whose value depends on which loop is operating.
For the output-voltage loop,
in which grd and gv are the resistor divider gain and the voltage amplifier gain, respectively. For thecharge-current loop,
in which RSNS and gSR are the charge-current-sense resistor value and the charge-current amplifier gain,respectively. Tdamp1 is the transfer function of the network added to damp the high-frequency harmonicsfor this loop. It contains a pole at 60 kHz and another at 150 kHz.
For the DPM loop,
in which RSNA and gAC are the adapter input current-sense resistor value and the input current amplifiergain, respectively. Tdamp2 is the transfer function of the network added to damp the high-frequencyharmonics for this loop. It contains a pole at 60 kHz and another at 150 kHz.
In Figure 7, A(s) is the compensator transfer function and FM is the control voltage to duty-cycle transferfunction. To generate a PWM drive signal, the control voltage Vc is compared with a ramp waveform, asshown in Figure 6. The ramp peak voltage Vp = Vcc/10. Thus, the value of FM can be obtained as:
The three loop gains are given by
SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 7Submit Documentation Feedback
bq2472x/3x Control-Loop Model and Compensation Design
From Equation 13 and Equation 14, it can be seen that the power stage CCM open-loop transfer functionsare basically a three-pole-two-zero system. A typical Bode plot of the converter control to output gainunder CCM conditions is shown in Figure 8. However, it can be simplified as a double-pole systembecause ωz1, ωz2, and ωp1 are normally located at high frequencies where the average model is not validany longer.
Figure 8. A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions
A Type III compensator is a promising candidate for this application. The typical realization of a Type IIIcompensator is demonstrated in Figure 9. Its typical frequency response is depicted in Figure 10.
Figure 9. A Type III Compensator
Figure 10. Bode Plot of a Typical Type III Compensator
8 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback
An integrator is needed for a high dc gain. Two zeroes need to be put below the loop gain crossoverfrequency fc to compensate the excessive phase lag due to the integrator and the power stage complexpole pair. In order to attenuate the high-frequency noise, two high frequency poles are added to ensurethe magnitude of the loop gain keeps decreasing after the 0-dB crossover. The two poles must be placedbelow half of the switching frequency.
The transfer function of the compensator is given as:
Because ωz1, ωz2 are higher than half of the switching frequency, place the two high-frequency poles at0.5fs:
Set a crossover frequency fc (voltage loop) of 10 kHz – 20 kHz. Select K = 2500 to make fc≈ 15 kHz withabout 60° phase margin. Normally, a phase margin greater than 40° is desirable. The transfer function ofGvd, the compensator and the entire voltage loop gain Tv are shown in Figure 14.
Figure 14. Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain
SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 13Submit Documentation Feedback
Figure 15 shows the typical Li-ion battery equivalent circuit model used for the small-signal analysis. lt isapproximately correct for charged state from 100% of SOC to 20% of SOC. Impedance varies frommanufacturer to manufacturer up to two times and from cell to cell up to ±15%. For a discharged statebelow 20% of SOC, the impedance starts to increase rapidly. The particular value the impedance reachesdepends on manufacturer, but it can be roughly modeling by multiplying R1 and R2 by 3.
Figure 15. Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)
Plot the output-voltage loop gain, and check the stability and bandwidth with a 3s2p battery load, asshown in Figure 16.
Plot the charge-current and input-current loop gains, and check the stability and bandwidth. The entirecharge-current and input-current loop gains Tis and Tii are shown in Figure 17 and Figure 18, respectively.
14 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback
Plot the output-voltage and input-current loop gains, and check the stability and bandwidth. The entireoutput-voltage and input-current loop gains Tv and Tii are shown in Figure 19 and Figure 20, respectively.
Figure 19. Output-Voltage Loop Gain TV (DCM)
18 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback
From the transfer function Bode plots obtained, it is seen that this compensator design offers adequatephase margins and bandwidths for all three loops. If not, the parameters (K, ωz1_com, ωz2_com) can beadjusted to get a reasonable design.
1. R. W. Erickson, D. Maksimvić, Fundamentals of Power Electronics (Second Edition), Kluwer AcademicPublishers, Sixth Printing 2004.
2. Fred C. Lee, Modeling and Control Design of DC/DC Converters, CPES Lecture Notes, Virginia Tech,2004.
SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 19Submit Documentation Feedback
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