Clock Talk LIVE Schedule – Presentation will begin shortly Tuesday, Sept 15th IEEE 1588 Timing Solutions for Non-Telecom Applications Tuesday, Sept 29th Clock Jitter Demystified and Jitter Requirements for 56/112 SerDes Tuesday, Oct 13th Design Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes Tuesday, Oct 27th Stop Guessing, Use Silicon Labs’ Timing Tools to Build Your Clock Tree Tuesday, Nov 10th Optimize Timing Solutions for High Speed FPGA and Application Processor Designs Tuesday, Nov 17th PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained Tuesday, Dec 1st Timing Solutions for 5G O-RAN Systems Tuesday, Jan 12th AEC-Q100 Timing Products for Automotive Applications Tuesday, Jan 26th Timing Solutions for Open-Compute Systems 1 Register for the series at: https://www.silabs.com/clock-talk
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Transcript
Clock Talk LIVE Schedule – Presentation will begin shortly
Tuesday, Sept 15th IEEE 1588 Timing Solutions for Non-Telecom Applications
Tuesday, Sept 29th Clock Jitter Demystified and Jitter Requirements for 56/112 SerDes
Tuesday, Oct 13thDesign Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes
Tuesday, Oct 27thStop Guessing, Use Silicon Labs’ Timing Tools to Build Your Clock Tree
Tuesday, Nov 10thOptimize Timing Solutions for High Speed FPGA and Application Processor Designs
Tuesday, Nov 17th PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained
Tuesday, Dec 1st Timing Solutions for 5G O-RAN Systems
Tuesday, Jan 12th AEC-Q100 Timing Products for Automotive Applications
Tuesday, Jan 26th Timing Solutions for Open-Compute Systems
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Register for the series at: https://www.silabs.com/clock-talk
ALL PCIe Signal Integrity specs are automatically measured by the Tool
▪ If single-ended waveforms are used as inputs
What is new on the PCIe Clock Jitter Tool
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Time Domain or Phase Domain Inputs
Automatic Noise Folding Correction
Mid-Bus Probing Capability
Scope Noise Correction
Phase Noise Analyzer Oscilloscope
Time Domain or Phase Domain Jitter Measurement
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“Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 MHz (at 300 MHz absolute frequency) below the Nyquist frequency.”
PCI-SIG GEN5 Table 8-18, note 2
Phase Noise Analyzer
Oscilloscope
The Silabs Clock Jitter accepts both• Time-Domain capture from your oscilloscope• Phase-Domain measurement from your PNA
Both are valid, but they are fundamentally different measurements:
The Silabs Clock Jitter automatically applies the noise folding correction• The user can select the number of folds → PCI-SIG recommends 3
It is done in 3 steps:1. Noise floor detection and flat extension 2. Folding of the high-frequency noise in band 3. Addition of the folded noise power to the raw
PNA measurement
Raw phase noise
Mid-Bus Probing Capability
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PCB
Ref Clock Ref Clock Receiver
Closest probing point to the load at Mid-Bus
Mid-Bus Probing Load Probing
Automatically sets the threshold that allows jitter measurements even with
significant reflections
Clock Trace
Via
The Silabs Clock Jitter can adjust the threshold when it is not possible to probe at load• Probing a mid-bus can distort the signal, causing multiple 0V crossing whiting a single period
To avoid erroneous period calculations the tool:• Allows the user to manually shift the threshold used to detect edges• Has an internal algorithm that looks for the optimal threshold location to optimize jitter
measurement
Scope Noise Correction
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ADC
SCOPE
*
Ref Clock Scope Voltage Noise
Vo
ltag
e
Time
Original Ref Clock
Ref Clock + Scope Noise
Threshold
Scope Noise = Instrument added Jitter
New Method that allows you to measure and correct the Scope noise contribution to the final RMS jitter!
The Silabs Clock Jitter offers a new method to estimate and correct added jitter oscilloscope measurements
• All ADCs add voltage noise to their readings → Quantization Noise, Input referred Noise etc.• That noise, when near the threshold voltage, will add jitter to the measurement• For Gen4/5 devices, the typical scope noise is significant when compared to the devices real jitter
The new instrument noise correction automatically calculates the add scope jitter from a grounded measurement, and corrects that value from a Ref. Clock jitter measurement
Scope Noise Removal: Experimental Data
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The Silabs Clock Jitter offers a new method to estimate and correct added jitter oscilloscope measurements
• All ADCs add voltage noise to their readings → Quantization Noise, Input referred Noise etc.• That noise, when near the threshold voltage, will add jitter to the measurement• For Gen4/5 devices, the typical scope noise is significant when compared to the devices real jitter (~40%)
0.000
0.050
0.100
0.150
0.200
0.250
0.300
0.350
0.400
0.450
0 1 2 3 4 5 6
PC
Ie G
en5
Max
RM
S H
F (p
s)
Device
MSO 50 SSOFF
MSO 50 SSOFF SNR
MSO PRB SSOFF
MSO PRB SSOFF SNR
PN 0 FOLD
PN 3 FOLD
DSA 50 SSOFF
DSA 50 SSOFF SNR
PCIe Gen5 Limit
Silabs PCIe Clock Jitter Tool Scope Noise Removal
Si52200 Si5332 EX NO Si5332 EX O0 Si5332 IX NO Si5332 IX O0
Summary
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1. Complete Signal Integrity Measurements
2. Jitter Measurements
a) Time Domain versus Phase Domain Jitter Measurement
b) Noise Folding
c) Mid-Bus Probing
d) Scope Noise Removal
Clock Talk:PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained
TUES, NOV 17TH AT 9:00 CST/16:00 CETWEDS, NOV 18TH AT 10:30 HKT
▪ Download ClockBuilder Pro HERE
▪ CBPro Tools & Support for In-System Programming
▪ Command Line Interface (CLI) User’s Guide
▪ ClockBuilder Pro Field Programmer (CBPROG-DONGLE) product page