CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 1 CIS 501: Computer Architecture Unit 3: Technology & Energy Slides developed by Joe Devietti, Milo Martin & Amir Roth at UPenn with sources that included University of Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood
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CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 1
CIS 501: Computer Architecture
Unit 3: Technology & Energy
Slides developed by Joe Devietti, Milo Martin & Amir Roth at UPennwith sources that included University of Wisconsin slides
by Mark Hill, Guri Sohi, Jim Smith, and David Wood
Paper Review #1
1. Why do the chips become less cost effective per component for both very large and very small numbers of components per chip?
2. One of the potential problems which Moore raises (and dismisses) is heat. Do you agree with Moore's conclusions?
3. A popular misconception of Moore's law is that it states that the speed of computers increases exponentially. Explain what Moore's law actually says based on this paper.
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 2
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 3
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 4
“But it won’t happen with integrated circuits. Since integrated electronic structures are two dimensional, they have a surface available for cooling close to each center of heat generation.”
“In fact, shrinking dimensions on an integrated structure makes it possible to operate the structure at higher speed for the same power per unit area.”
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 5
• Try to minimize defects• Process margins• Design rules
• Minimal transistor size, separation
• Or, tolerate defects• Redundant or “spare” memory
cells• Can substantially improve yield
Defective:
Defective:
Slow:
Correct:
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 14
Cost Implications of Defects
• Chips built in multi-step chemical processes on wafers• Cost / wafer is constant, f(wafer size, number of steps)
• Chip (die) cost is related to area• Larger chips means fewer of them
• Cost is superlinear in area• Why? random defects• Larger chip, more chance of defect
• Result: lower “yield” (fewer working chips)
• Wafer yield: % wafer that is chips• Die yield: % chips that work• Yield is increasingly non-binary - fast vs slow chips
Manufacturing Cost
• Chip cost vs system cost• Cost of memory, storage, display, battery, etc.
• Cost vs price• Relationship complicated; microprocessors not
commodities • Specialization, compatibility, different
cost/performance/power• Economies of scale
• Unit costs: die manufacturing, testing, packaging, burn-in• Die cost based on area & defect rate (yield)• Package cost related to heat dissipation & number of pins
• Fixed costs: design & verification, fab cost• Amortized over “proliferations”, e.g., Core i3, i5, i7 variants• Building new “fab” costs billions of dollars today• Both getting worse; trend toward “foundry” & “fabless”
models
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 15
Transistor Switching Speed
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 16
A Transistor Analogy: Computing with Air
• Use air pressure to encode values • High pressure represents a “1” (blow)• Low pressure represents a “0” (suck)
• Valve can allow or disallow the flow of air• Two types of valves
17
High (On) High (Off)
N-Valve P-Valve
Low (On)Low (Off)
hole
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Pressure Inverter
18
High
Low
Out
N-Valve
P-Valve
In
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Pressure Inverter (Low to High)
19
High
Low
Low
N-Valve
P-Valve
High
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Pressure Inverter
20
High
Low
N-Valve
P-Valve
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Pressure Inverter (High to Low)
21
Low
High
Low
High
N-Valve
P-Valve
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Analogy Explained
• Pressure differential electrical potential (voltage)• Air molecules electrons• Pressure (molecules per volume) voltage• High pressure high voltage• Low pressure low voltage
• Air flow electrical current• Pipes wires• Air only flows from high to low pressure• Electrons only flow from high to low voltage• Flow only occurs when changing from 1 to 0 or 0 to 1
• Valve transistor• The transistor: one of the century’s most important
inventions
22CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
Transistors as Switches
• Two types• N-type• P-type
• Properties• Solid state (no moving parts)• Reliable (low failure rate)• Small (14nm channel length)• Fast (<0.1ns switch latency)
23
N-Valve
P-Valve
N-MOSFET
P-MOSFET
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 24
Complementary MOS (CMOS)
• Voltages as values• Power (VDD) = “1”, Ground = “0”
• Two kinds of MOSFETs• N-transistors
• Conduct when gate voltage is 1• Good at passing 0s
• P-transistors• Conduct when gate voltage is 0• Good at passing 1s
• CMOS• Complementary n-/p- networks form boolean logic (i.e.,
gates)• And some non-gate elements too (important example:
RAMs)
power (1)
ground (0)
inputoutput
n-transistor
p-transistor
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 25
Basic CMOS Logic Gate• Inverter: NOT gate
• One p-transistor, one n-transistor• Basic operation• Input = 0
• P-transistor closed, n-transistor open
• Power charges output (1)• Input = 1
• P-transistor open, n-transistor closed
• Output discharges to ground (0)
01
1 0
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy
26
Another CMOS Gate Example
• What is this? Look at truth table• 0, 0 1• 0, 1 1• 1, 0 1• 1, 1 0• Result: NAND (NOT AND)• NAND is “universal”
• What function is this?
BA
A
B
output
B
A
A B
output
A strange gate
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 27
B
A
output
B
A
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 28
Technology Basis of Transistor Speed• Physics 101: delay through an electrical component
∝ RC• Resistance (R) ∝ length / cross-section area
• Slows rate of charge flow• Capacitance (C) ∝ length * area / distance-to-
other-plate• Stores charge
• Voltage (V)• Electrical pressure
• Threshold Voltage (Vt)• Voltage at which a transistor turns “on”• Property of transistor based on fabrication technology
• Switching time ∝ (R * C) / (V – Vt)
• Two kinds of electrical components• CMOS transistors (gates, sources, drains)• Wires
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 29
10I
10
10
Resistance
• Channel resistance• Wire resistance
• Negligible for short wires• Linear in length for long wires
1
1
01
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 30
• nonplanar (or “3D”) transistors• trigate: multiple sources/drains/gates• FinFET: gate is wrapped around the channel
• lower leakage, faster switching times• Intel’s trigate design released in mid-2012 (Ivy
Bridge)• other fabs not yet thereCIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 33
http://en.wikipedia.org/wiki/File:Trigate.jpg
Dennard Scaling
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 34
“Design of ion-implanted MOSFET's with very small physical dimensions”Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlancIEEE Journal of Solid-State Circuits, October 1974
Dennard Scaling
• stopped in ~2005 due to leakage concerns• V close to Vt, transistors never really “on” or “off”• gate-oxide leakage due to very small oxide thickness
• quantum-mechanical electron tunneling• Moore’s Law still in effect!
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 35
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 36
Wire GeometryPitch
Width
LengthHeight
• Transistors 1-dimensional for design purposes: width
• Wires 4-dimensional: length, width, height, “pitch”• Longer wires have more resistance (slower)• “Thinner” wires have more resistance (slower)• Closer wire spacing (“pitch”) increases capacitance
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 37
Increasing Problem: Wire Delay
• RC Delay of wires• Resistance proportional to: resistivity * length / (cross
section)• Wires with smaller cross section have higher resistance• Resistivity (type of metal, copper vs aluminum)
• Capacitance proportional to length• And wire spacing (closer wires have large capacitance)• Permittivity or “dielectric constant” (of material
between wires)
• Result: delay of a wire is quadratic in length• Insert “inverter” repeaters for long wires• Why? To bring it back to linear delay… but repeaters still
add delay• Long wires are relatively slow compared to
transistors• And take a relatively longer time to cross relatively larger
chips
Technology Scaling Trends
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Moore’s Law: Technology Scaling
• Moore’s Law: aka “technology scaling”• Continued miniaturization (esp. reduction in channel
area(cost)/transistor– Reduces transistor reliability• Literally: DRAM density (transistors/area) doubles every 18
months• Public interpretation: performance doubles every 18
months• Not quite right, but helps performance in several
ways…
channel
source drain
gate
Moore’s Effect #1: Transistor Count
• Linear shrink in each dimension• 180nm, 130nm, 90nm, 65nm, 45nm, 32nm, 22nm, 14nm,
…• Each generation is a 0.7x linear shrink
• older generation was 1.414x larger• Shrink each dimension (2D)
• Results in 2x more transistors (1.414*1.414) per area
• Generally reduces cost per transistor
• More transistors can increase performance• Job of a computer architect: use the ever-increasing
number of transistors• Today, desktop/laptop processor chips have 1B+
transistors CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 40
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 41
Moore’s Effect #2: RC Delay
• First-order: speed scales proportional to gate length• Has provided much of the performance gains in the past
• Scaling helps wire and gate delays in some ways…+ Transistors become shorter (Resistance), narrower
(Capacitance)+ Wires become shorter (Length Resistance)+ Wire “surface areas” become smaller (Capacitance)
• Hurts in others…– Transistors become narrower (Resistance)– Gate insulator thickness becomes smaller (Capacitance)– Wires becomes thinner (Resistance)
• What to do?• Take the good, use wire/transistor sizing to counter the bad• Exploit new materials: Aluminum Copper, metal gate, high-
K
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 42
Moore’s Effect #3: Cost
• Mixed impact on unit integrated circuit cost + Either lower cost for same functionality… + Or same cost for more functionality – Difficult to achieve high yields
– Increases startup cost• More expensive fabrication equipment• Takes longer to design, verify, and test chips
– Process variation across chip increasing• Some transistors slow, some fast• Increasingly active research area: dealing with this
problem
Moore’s Effect #4: Psychological
• Moore’s Curve: common interpretation of Moore’s Law• “CPU performance doubles every 18 months”• Self fulfilling prophecy: 2X every 18 months is ~1% per
week• Q: Would you add a feature that improved performance
20% if it would delay the chip 8 months?• Processors under Moore’s Curve (arrive too late) fail
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 43
Moore’s Law in the Future• Won’t last forever, approaching physical limits
• “If something must eventually stop, it can’t go on forever”• But betting against it has proved foolish in the past• Perhaps will “slow” rather than stop abruptly
• Transistor count will likely continue to scale• “Die stacking” is on the cusp of becoming mainstream• Uses the third dimension to increase transistor count
• But transistor performance scaling?• Running into physical limits• Example: gate oxide is less than 10 silicon atoms thick!
• Can’t decrease it much further• Power is becoming the limiting factor
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 44
Power & Energy
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Power/Energy Are Increasingly Important
• Battery life for mobile devices• Laptops, phones, cameras
• Tolerable temperature for devices without active cooling• Power means temperature, active cooling means cost• No room for a fan in a cell phone, no market for a hot cell
phone
• Electric bill for compute/data centers• Pay for power twice: once in, once out (to cool)
• Environmental concerns• IT accounts for growing fraction of electricity consumption
Energy & Power • Energy: measured in Joules or Watt-seconds
• Total amount of energy stored/used• Battery life, electric bill, environmental impact• Instructions per Joule (car analogy: miles per gallon)
• Power: energy per unit time (measured in Watts) • Related to “performance” (which is also a “per unit time”
metric)• Power impacts power supply and cooling requirements
(cost)• Power-density (Watt/mm2): important related metric
• Peak power vs average power• E.g., camera: power “spikes” when you actually take a
picture• Joules per second (car analogy: gallons per hour)
• Two sources:• Dynamic power: active switching of transistors• Static power: leakage of transistors even while inactiveCIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 47
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 48
Recall: Tech. Basis of Transistor Speed• Physics 101: delay through an electrical component
∝ RC• Resistance (R) ∝ length / cross-section area
• Slows rate of charge flow• Capacitance (C) ∝ length * area / distance-to-
other-plate• Stores charge
• Voltage (V)• Electrical pressure
• Threshold Voltage (Vt)• Voltage at which a transistor turns “on”• Property of transistor based on fabrication technology
• Switching time ∝ (R * C) / (V – Vt)
CIS 501: Comp. Arch. | Prof. Joe Devietti | Technology & Energy 49
Dynamic Power
• Dynamic power (Pdynamic): aka switching or active power• Energy to switch a gate (0 to 1, 1 to 0)• Each gate has capacitance (C)
• Charge stored ∝ C * V• Energy to charge/discharge a capacitor ∝ C * V2
• Time to charge/discharge a capacitor ∝ V• Result: frequency ∝ V
• Pdynamic ≈ N * C * V2 * f * A• N: number of transistors• C: capacitance per transistor (size of transistors)• V: voltage (supply voltage for gate)• f: frequency (transistor switching freq. ∝ clock freq.)• A: activity factor (not all transistors may switch this
cycle)
0
1
Reducing Dynamic Power• Target each component: Pdynamic ≈ N * C * V2 * f * A
• Reduce number of transistors (N)• Use fewer transistors and gates