Circuits & 2-adic Integers · 1 Circuits & 2-adic Integers Digital Synchronous Circuit. 2-adic Integers. Arithmetic Circuits. LHC Application. Jean Vuillemin. École Normale Supérieure

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Circuits & 2-adic Integers

Digital Synchronous Circuit2-adic IntegersArithmetic CircuitsLHC Application

Jean VuilleminÉcole Normale Supérieure de Paris

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Synchronous Binary SignalsEBM Images @1GHz

1 μm

Binary Values Discrete Time

Synchronous Transitions

1 νs

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Synchronous Gates1

2t t

t t t t t t

t t t t t t

t t t t

a aa b a b a ba b a b a ba b a b

¬ = −⊕ = + −∪ = + −∩ =

Register

0 10, t to o i+= =

Boolean Gates

0 11, t to o i+= =

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Half Adder

2t t t t t t t

t t t t t

s a b a b a br a b a b= ⊕ = + −= ∩ =

( , , ) ( , ){

}

halfAdd a b c s rs a br a b

== ⊕= ∩

: 2t t t tt a b s r∀ + = +

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Digital Synchronous Circuit• Syntax

• Compose In, And,Xor, Reg• Feed-forward Boolean Gates & Clocked feed-back• Hierarchical Netlist

• Semantics• All variables have binary values at all times• Zero delay: Not, And,Xor Unit delay: Reg• All transitions happen at clock signal

• Global clock• Isochronous distribution through entire chip• Clock period can be constant or variable• Clock period exceeds all transition delays

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Binary Integers

2 2n k kk

k k n

n B∈

= =∑ ∑

1 nkk n B∈ ⇔ =

0 1 2 4 8 16 1¬ = + + + + + = −

( 1)n n¬ = − +

{ }0 1 2 3 3

0 0 0 0 0 {}1 0 0 0 0 {0}0 1 0 0 0 {1}1 1 0 0 0 {0 1}0 0 1 0 0 {2}1 0 1 0 0 {0 2}0 1 1 0 0 {1 2}

012345678

1 1 1 0 0 {0 1 2}0 0 0 1 0 {3}

n n n nk

nB B B B B k nn > ∈ { }0 1 2 3 3

1 1 1 1 1 {}0 1 1 1 1 {0}1 0 1 1 1 {1}0 0 1 1 1 {0 1}1 1 0 1 1 {2}0 1 0 1 1

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{0 2}1 0 0 1 1 {1 2}0 0 0 1 1 {0 1 2}1 1 1 0 1 {3

345

}

6789

n nk

n n nB B B B B nkn >

−−−−−−−

∈¬¬¬¬¬

¬−¬−

¬¬

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2-adic Addition

1 1 1 0 1 01 0 1 1 1 0

abcs

12t t t t ta b c s c ++ + = +

01 …0

11

10

11

11

+

0

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Magic Masks

0

0

: 101010102 : 01010101μμ+

2 22

1(1 0 )1 2

k k

k kμ ∞ −= =

+

11 4 160 3

μ = + + + = −

03 1μ = −

1 2 3 4 5

1 0 1 0 1 1/31 1 0 0 1 1/51 1 1 1 0 1/1

01

72

k k k k k kB B B Bk B μ− − − − −

−−−

2 2n n nk k

n n k

Bμ ¬

∉

= =∑ ∑

0

0

0

: 101010102 : 010101013 : 11111111

μμμ

+=

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0 10, t to o i+= =

2 2t tt to o i i= =∑ ∑

2-adic Gates

2 2

2 2

t tt t

t tt t

a a b b

s s r r

= =

= =

∑ ∑∑ ∑

: 2t t t tt a b s r∀ + = +

2o i=

2a bs r+ =+

O’

' 1 2o i= +

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Serial Increment

1 22

c rx c y r

= ++ = +

0 1

: 1

2t t

t t t t

tc c rx c y r

+

∀ ∈= =+ = +

N2 2

2 2

t tt t

t tt t

t tt t

x x y y

c c r r∈ ∈

∈ ∈

= =

= =

∑ ∑∑ ∑N N

N N

1y x= +

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One & Two’sComplement

11

11

x xx x

x xx x

− = +¬− = +¬+ = −¬− = ¬−

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Full Adder( , , ) ( , )

{ ( , ) ( , )( , ) ( , )

}

fullAdd a b c s rp g halfAdd a bs d halfAdd c gr g d

===

= ⊕

2a b c s r+ + = +

p a b g a bs c p d c p

r g d

= ⊕ = ∩= ⊕ = ∩

= ⊕

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a b p gc p s dr g d

+ = ++ = +

= +

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Parallel Adder

0 2 2 2 2k k k Nk k k N

k N k N k N

c a b s c< < <

+ + = +∑ ∑ ∑

0 0 0 0 1

1 1 1 1 2

22

a b c s ca b c s c+ + = ++ + = +

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Serial Adder

c= 2ra+b+c=s+2r s=a+b

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Beyond Addition

( )

2

2 223

(01)

a x axa

a x∞

= +

= −

= ×

2y b by x

= +=

2

31 1(10)3

b x axb

∞

= +

=

=

1616

Large Hadron Collider

> 100 TB/s

~ 100 GB/s

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Transition Radiation TrackerRegion of interest

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Linear Hough Transform

L

h∈∑p L

(L) = p

LH = Lmax max { ( )}h

maxL

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Input Receiver

FHT

Bit Reverse

Max Column

Max Rows

Adders &

Line Delay

Network

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Trade Time For Space

Z=4 : 2b/cycle

Z=2 : 1b/cycle

Z=√2 : 0.5b/cycle

Energy is #1 design criteria for both hard & soft,hence minimal computation at minimal speed!

kka a Z=∑0 1( 2 ) ka a a Z= +∑

2 1 22 2 2k kk ka a a += +∑ ∑

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Questions!