Circuit Design for a 2.2 GByte/s Memory Interface Stefanos Sidiropoulos Work done at Rambus Inc with A. Abhyankar, C. Chen, K. Chang, TJ Chin, N. Hays, J. Kim, Y. Li, G. Tsang, A. Wong, D. Stark Increasing Chip I/O Bandwidth Computers: Main memory: SDRAM100 (100 Mbps) RDRAM (0.8-1.1 Gbps) Peripherals: PCI (66 Mbps) Infiniband (2.5 Gbps) Networks: Physical Front End: LAN: Fast-Eth (100 Mbps) Gigabit-Eth (1Gbps) WAN: OC-12 (625 Mbps) OC-48 (2.4 Gbps) Switch Fabric: 625 Mbps 2.5 Gbps
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Circuit Design for a 2.2 GByte/s MemoryInterface
Stefanos Sidiropoulos
Work done at Rambus Inc with A. Abhyankar, C. Chen, K.Chang, TJ Chin, N. Hays, J. Kim, Y. Li, G. Tsang, A. Wong,
D. Stark
Increasing Chip I/O Bandwidth
Computers:Main memory:
SDRAM100 (100 Mbps) RDRAM (0.8-1.1 Gbps)
Peripherals:PCI (66 Mbps) Infiniband (2.5 Gbps)
Networks:Physical Front End:
LAN: Fast-Eth (100 Mbps) Gigabit-Eth (1Gbps)
WAN: OC-12 (625 Mbps) OC-48 (2.4 Gbps)
Switch Fabric:625 Mbps 2.5 Gbps
Outline
OverviewTiming Methods
Signaling Methods
Timing Circuits
Signaling Circuits
Results
Main Issues
Drive and capture signals at the correct timeBit times are as small as 2-3 gate delays
Send and receive signals robustlyNoise is a large fraction of the signal
Tx RxChannel
PCB, Coax, Fiber
< 400-mV
< 1-ns
1 0 0 1 0 1
Timing Architectures
Synchronous:
Same frequency and phaseConventional busses
Conventional Memories
Mesochronous:
Same frequency, unknownphase
Fast memories/busses
MP networks
Interconnection networks
Plesiochronous:
Almost the same frequencyNetwork front-end
Router core
t t
F0
tA tB
F0tA≠≠≠≠ tB
F1 F2F1≈≈≈≈ F2
Synchronous Systems
On-chip clock is a multiple of system clock:
Synthesize on-chip clock frequency
On-chip clock phase varies:
Cancel clock buffer delay
PLL/DLLCKX
CKC
DI
CKX
DI
CKC
on-chip logic
Mesochronous Systems
Position on-chip sampling clock at the optimal point i.e. maximize “timing” margin
PLL/DLL
ref
data
CKSRC
rcvr
logic
CKRCV
CKSRC
data
CKRCV
D0 D1 D2 D3
Plesiochronous Systems
Recover incoming data fundamental frequency
Position sampling clock at the “optimal” point
DIN
CRC
CKR
rcvrlogic D0 D1DIN
CKR
Signaling
Send and receive the data impaired by noise:Independent noise sources: