CIC Referenced Flow for Cell-based IC Design

Microsoft Word - Design and Implementation ASIC Methodology Using0512 .doc

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(Version)
functiontimingpowerDRC CIC
Cell-Based Design Flow Logic SynthesisPlace&RouteLayout Merging
Tape out
CIC Cell Library 1 The CIC Cell-Based Design Flow Overview 2 RTL Verification
2.1 RTL Code 2.2 Code Coverage Analysis 2.3 RTL Simulation
3 Gate-level Pre-layout Verification 3.1 To Generate Gate-level Netlist Using Logic Synthesis Tool 3.2 Gate-level Simulation 3.3 Gate-level Power Analysis 3.4 Formal Verification
4 Gate-level Post-layout Verification 4.1 To Generate GDSII & Gate-level Netlist Using APR Tool 4.2 RC Extraction 4.3 Gate-level STA & Simulation 4.4 Gate-level Power Analysis 4.5 Formal Verification 4.6 DRC/LVS
5 Circuit-level Verification 5.1 Replace True Layout 5.2 DRC/LVS 5.3 Circuit Extraction 5.4 Circuit-level STA & Simulation
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2-1 RTL Code..................................................................................................................... 5 2-2 RTL Simulation............................................................................................................ 7 2-3 Code Coverage Analysis .............................................................................................. 8
4 Gate-level Post-layout Verification .................................................................................. 14 4-1 To Generate GDSII & Gate-level Netlist Using APR Tool........................................ 15 4-2 RC Extraction............................................................................................................. 16 4-3 Gate-level STA & Simulation .................................................................................... 17 4-4 Gate-level Power Analysis......................................................................................... 17 4-5 Formal Verification .................................................................................................... 18 4-6 DRC/LVS ................................................................................................................... 19
5 Circuit-level Verification.................................................................................................. 20 5-1 Replace True Layout .................................................................................................. 20 5-2 DRC/LVS ................................................................................................................... 21 5-3 Circuit Extraction....................................................................................................... 21 5-4 Circuit-level Simulation............................................................................................. 21
CIC
codingLogic synthesisPlace&RouteLayout Merge
, function
timingpowerDRC CIC Cell-Based
Design Flow Logic SynthesisPlace&RouteLayout Merging Tape out
CIC Cell
Library IC
RTL Code
Logic synthesis
RTL simulation
5
IC
(Hardware Description Language) VHDL[1]
Verilog HDL[2] RTL Design Flow

2-1 RTL Code

Function Unit
Function
VHDL RTL Code Verilog
RTL Code
abx VHDL <=
+ ALU RTL
Code ALU component
RTL Code by Verilog
RTL Code gtlt
eql B 4bits
Verilog VHDL RTL Code
RTL Code
[2]HDL
RTL Level



module comparator(gt, lt , eq , A, B); output gt, lt , eql input [3:0] A, B; assign gt = (A>B); assign lt = (A<B); assign eq = (A= =B); endmodule
SIGNAL a, b : std_logic_vector(2 DOWNTO 0); SIGNAL x : std_logic_vector(5 DOWNTO 0); x <= a + b;
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3. if-else if-else case



(Waveform)
(Function Verification)
Place&Route
(Source Code Level)
1. (Vector Format)


1. module module
Test Bench clk reset
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2. Test Bench moduleTest Bench
t_clk t_reset clk
reset x Test Bench Test Bench
t_x




RTL Level Place&Route Test Bench
9
100 Test Bench 70
Code Coverage 70/100 = 70% 70%
70% 30%
Code Coverage 1. Function coverage Function 2. Statement coverage Statement
3. Condition coverage Condition
TrueFalse… 4. Path coverage Path 5. Entry/exit coverage Function call return

Pre-layout Cell-Based Design Flow Front-End
RTL Code Logic Synthesis ASIC Layout Gate-level
Netlist Layout Logic Synthesis
Function Logic SynthesisGate-level SimulationPower Analysis
Formal Verification
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Logic SynthesisFront-End DesignRTL
RTL CodeLogic SynthesisCompiler Design
?(Process)(Standard-Cell)

ConstraintTiming
?Cell
Cell
SimulationLogic SynthesisCIC
11
Multi-Supply (Power Intent) Compiler Design
Support Low Power Library Compiler Design
Low Power
Compiler DesignTesting
Circuit[7] Low Power Testing
Gate-level Netlist
3-2 Gate-level Simulation
Code [5] Layout
Function Pre-layout Simulation Gate-level Simulation
Gate-level Simulation
Gate-level NetlistSDF RTL Simulation Test Bench STA
Timing Period sdf Simularor Cell
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Net Delay Time Simulation Model Standard Cell Behavior ModelMemory
Behavior ModelARM Processor Model PLI
Low Power Design PLI [6] Simulator
Waveform Format Function
Function Debug [4]
Gate-level Pre-Layout Simulation
3-3 Gate-level Power Analysis


Pattern on/off Switch Activity Power Analysis
Power Analysis Library Lib
Library IP Cell Macro Power Information lib Power
Analysis lib Cell / Macro
Gate-level Netlist Gate-level Simulation Switch Activity [6]
Pre-Layout Power Analysis WLM
[9]Clock Tree Synthesis Layout
Pre-layout Power Analysis
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Gate-level Netlist
3-4 Formal Verification
Function Function Debug Tool[8]
Formal Verification
Formal Verification Function
Golden RTL Code
Gate-level Netlist (Revised Code) Library Testing
CircuitConstraintsMaskToolKey Point(Key
Point Primary Input / OutputFlip-FlopLatchBlack Box ) Logic Equivalence
Check Tool Schematic

Gate-level Netlist APR(Auto Placement & Route) Auto-layout
ASIC Layout GDSII Post-layout Gate-level Netlist Layout
Function Post-layout RC ExtractionGate-level Simulation
Power AnalysisFormal VerificationDRC/LVS
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mux2 U3 (.S(A),.I1(T1),.I2(T2), .Z(X);
mux2 U3 (.S(A),.I1(T1),.I2(T2), .Z(X);
4-1 To Generate GDSII & Gate-level Netlist Using APR Tool
APR(Auto Placement & Route)Back-End Design
Pre-layout Gate-level NetlistPost-layout GDSII & Gate-level Netlist
APRFloorplanGate-level Netlist
Standard Cell LibraryIO Pad LibraryTechnology File(APR ToolP&RRule)
Macro(MemoryARM Processor)FloorplanDie
MeshPlacementTiming Constraint(APR Tool
captbl)PlacementAPRConstraintCell
PerformancePlacementClock Tree Synthesis(CTS)
Clock SignalbalanceFlip-FlopClock SkewClock
Routing OptimizationRoutingP&R
ViolationPost-layout GDSIIGate-level NetlistAPR
Design Macro Timing
Power Mesh P/G Cell Metal
Stripe IR Drop Electro-Migration(EM)
Layout Layout
Solution CIC [12]
Auto Placement & Route Flow
4-2 RC Extraction
Timing Optimization Timing
Report Tool Layout
RC Table Tool Net DelayRC Table TLU+ capTbl
Library Table unit Metal RC Tool
Net Net Delay Layout
Tool Net Delay
WLM Report Timing Layout
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sdf Post-layout Gate-level Simulation
4-3 Gate-level STA & Simulation
Layout Function Layout Function
Signal Pin floating CTS Layout
Gate-level Post-layout Simulation Function Pre-layout
Simulation Gate-level Netlist sdf Layout Test
Bench Period Layout STA
Power Analysis Data Preparation v.s. Data Output
4-4 Gate-level Power Analysis
Layout Power Mesh CellMacro
Power Mesh Robust IR Drop ( 10%
) EM Violations Layout Power Analysis
Power Analysis P/G Cell Input Transition
Time( Cell Power Consumption Input Transition Output Capacitance
)Net Switch ActivitySwitch Activity
Layout Gate-level Netlist Pattern Simulation Switch
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Activity Tool Power Analysis Power Analysis
IR Drop MapElectro-Migration Map
1.2VMax IR Drop 39.58mV 3.27%( 10%) Power Mesh
Metal Technology File 1um
(b) EM Map Worst EM 3.89mA/um Metal3
Metal3 19.3mA/um Power Mesh EM
Violation Power Analysis CIC
[10][11][12]
(a) (b) Power Analysis Output(a)IR Drop Map(b)Electro-Migration Map
Example for Max Current Density
4-5 Formal Verification
Post-layout Gate-level Simulation Layout
Function Function Debug Tool[8]
Formal Verification
Formal Verification Layout Function

4-6 DRC/LVS
Design Rule Check(DRC) Layout Foundry
Max or Min WidthAreaInside/Outside Spacing Rule
Rule Layout GDSII Layout (
VirtuosoLaker) DRC Layout
Rule
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Layout (b)LVS (a)
Transistor LVS Full-Custom Flow Library Standard
Cell Cell LVS
LVS Cell-Based Flow Cell Black Box
Black Box DRC/LVS
CIC [10][11]
5 Circuit-level Verification
Post-layout Verification System PVS
LPE Transistor-level Netlist
Transistor-level Simulation
spice fast spice event driven
transition table


CIC GDSII
Gate-level Post-layout
Verification Metal Density Metal
Density


Circuit-level Simulation IO



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[1] CIC – VHDL. [2] CIC – Verilog. [3], “ Post-layout Verification System(PVS) Post-layout Simulation”,
PDS-031218-00-002.pdf. , pp. 1-5, Dec 2003. [4] CIC – Nanosim. [5],”Logic Synthesis with Design Compiler,” CIC 2008 [6],”Power Optimization / Analysis with Synopsys Tool Power Compiler and
PrimePower,”CIC 2006 [7],”Design for Testability with TurboBist-Memory, DFT Compiler and TetraMAX,”
CIC 2008 [8],”Advanced Debugging with Verdi,” CIC 2008 [9],”A Timing Closed Approach for Block Implementation of a 300MHZ DCT/IDCT
Processor,”CIC 2005 [10],”Cell-Based IC Physical Design and Verification with SOC Encounter,” CIC
2008 [11],”Cell-Based IC Physical Design and Verification with Astro,” CIC
2008 [12],”Automatic Floorplan and Power Network Synthesis / Analysis with Synopsys
Tool : JupiterXT,”CIC 2006