Ciarán O’ Mara - Student ID: 15154394 · 1 Module: Digital Systems 1 EE4522 Lab: 3 Student name: Ciarán O’ Mara Student ID: 15154394 Lab Purpose Analyse, build and test a 3-

EE4522 - Lab 2A

Ciarán O’ Mara - Student ID: 15154394

Lab purpose

1. Installation of circuit simulator Simetrix.

2. Download the user manual.

3. Schematic entry and transient simulation.

Procedure

1. Download the Simetrix circuit simulator from their website.

2. Download the user manual from their website.

3. Follow the lab PDF to draw and configure the schematic.

4. Configure the simulator to transient and run the system.

5. Draw the truth table to ensure the schematic was correctly simulated.

Analysis of Digital Circuit

The digital circuit consist of 5 NAND gates.

There are two square wave inputs x and y.

Y has a frequency which is twice the frequency of X.

In simple terms y reaches a digital HIGH twice within the 1second whereas x is only

high once.

There is an output F which is an accumulation of all 5 gates.

In the sketch diagram below it is clear as to how the output is generated and

confirms that it was correctly simulated.

Fig 1. Schematic Diagram

The output, F is a combination of both the x and y signals.

The spike to a LOW @time 500ms is due to the fact that both input signals are

changing from HIGH to LOW and visa versa in that split second.

This causes the output to appear to spike to a LOW instantaneously.

Conclusion

The results of the simulation were as expected and confirmed with use of a truth table.

Creating the schematic and simulating the Digital Circuit was very straight forward and no

problems were met in the process.

Fig 2. Simulated Input & Output Signals

Fig 3. Truth Table & Simulation Table

Module: Digital Systems 1 EE4522

Lab: 2

Student name: Ciarán O’ Mara

Student ID: 15154394

Lab Purpose

Prototype digital circuit (XOR function using NAND)

Usage of prototyping facilities (HP-1 system)

Comparison of measurement results with simulation.

Lab Procedure

Get wires, capacitors and logic chips.

Study the circuit diagram and digital designer platform information before building the

circuit.

Ensure power is off and begin to build the circuit step by step.

Test circuit by flicking both switches to on and then both to off, no LED should light.

Then test one switch on and one switch off the LED should light.

If the circuit doesn’t work debug the circuit using the logic probe.

This is the circuit diagram drawn out. The truth table indicates the output in a digital sense. If only one

of the switches is switched to the on position a constant 5v is generated as a result of the gate

configuration at the 10th pin of the second UI

which is connected to an LED and then to

ground. This LED is like a digital signal, when

it’s on it signifies a 1 or %v and when it’s off

in indicates a 0 or 0V.

Inputs Output

X Y F

0 0 0

1 0 1

0 1 1

1 1 0

Fig. 1. Circuit Schematic Fig. 2. Truth Table

The output voltage is not exactly the 5V that is theoretically expected. This could be due to the fact

that the circuit poses a tiny resistance. Tiny voltage dividers could then reduce the output as a result.

However, a logic high exists inside a scale or a logic

level. This is where a range of voltages where a logic

HIGH exists. At the other end of the scale there’s a

range where a logic LOW exists. The undefined part

in the middle is where the signal is neither HIGH nor

LOW.

Therefore, the output HIGH signal in most cases just

has to be contained within the HIGH part of the logic

level. The readings taken in the lab are well inside the

logic HIGH and logic LOW parts of the logic scale.

The digital designer has three breadboards, LED indicators and switches. This makes it easy to build

and debug the circuit. 5 NAND gates are needed to build the circuit however each U1 chip contains

only 4 NAND gates, therefore two U1 chips are needed. The capacitors are used to generate a constant

smooth DC output.

F = 1 F = 0

4.98V 0.4mV

Component Quantity

U1 74HC00 X2

Capacitor X2

HP1 Digital Designer X1

Wire X23

Fig. 3. Example of a logic level

Fig. 4. HIGH & LOW voltage

outputs at F

Fig. 5. BOM (Build of materials)

Conclusion

At first the circuit didn’t work correctly. After a couple of minutes debugging it was

clear that there was a single wire connection missing.

The circuit then worked correctly, i.e. the LED will only light when one of the two

switches is flicked to the on position.

The output voltage when F=1 was not exactly 5V this could be due to the fact that

the circuit has a small resistance and tiny voltage dividers could have an effect on the

5V output.

Fig. 6. Circuit on Digital Designer

1


Lab: 3



Lab Purpose

Analyse, build and test a 3- input parity generator

Sum-of-products. Product-of-sums.

Compare measurement results versus simulation

Lab Procedure

Get wires, capacitor and logic chip.

Study the circuit diagram and digital designer platform information before building the circuit.

Ensure power is off and begin to build the circuit step by step.

Test circuit by flicking the three switches to the different possible positions. The LED should

only light when an odd amount of switches are on.

Then improve the circuit, utilising the left over gates to turn the odd parity generator into an

even parity generator.

If the circuit doesn’t work debug the circuit using the logic probe.

Build of Materials

Part Quantity

74HC86 1

10uF Capacitor 1

Power Supply 1

Digital Designer 1

Wires -

XOR GATE TRUTH F= XY=X'Y+XY'

An exclusive OR gate is an or gate but will only give a 1 at its output when either X is a 1 or Y is a but

not when both are. The 74HC86 contains 4 XOR which is one more than is needed to create an even

and odd parity generator. An OR gate can also be used to create an inverter.

Fig 1. Build of Materials

2

ODD-PARITY GENERATOR - F = ((XY) Z)

The odd parity generator consists of two XOR gates where the output of the first gate is fed into one

of the inputs to the second gate. The inputs are controlled by three switches. The table below displays

the output F all possible combinations of the three switches.

Odd-parity function

F = (X’Y’Z)+(X’YZ’)+(X’YZ)+(XYZ) Sum of the Products - Maxterms

F = (X+Y+Z)(X+Y’+’Z)(X’YZ’)(X’Y’Z) Product of the Sums - Minterms

An odd-parity 4-bit packet would consist of the 3 inputs such as X, Y and Z and the output F being the

most significant bit in this example being the parity bit to ensure that there’s an odd number of bits

in the 4-bits. This can be used to a certain degree of accuracy to verify transmitted data. One will be

able to tell whether there is an odd even number of bits in the data based on whether a 1 was added

to the left or not. (examples - 1011, 1101, 0001 etc.)

Example:

Input – 101

Expected Output – 1101

Actual output – 1101

X Y Output

0 0 0

0 1 1

1 0 1

1 1 0

Odd-Parity Truth Table

X Y Z F

0 0 0 0

0 0 1 1

0 1 1 0

0 1 0 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Fig 2. Diagram of IC

Fig 4. Simetrix odd-parity generator schematic

Fig 5. Odd-parity truth table

3

In this example based on the fact that an odd parity generator is being used and the parity bit is a 1,

we can tell that the data being transmitted has an even number of 1s

This method of data verification will not work in the case of certain bits flipping an error will not be

returned. For example, if the input is 010 and the expected output is 0010, however the third and

second bit flip resulting in 0110 this will not return an error as there is still an even number of bits and

the parity bit indicates that there should be an odd amount. If the most significant bit flips, there you

will also have a problem.

EVEN-PARITY GENERATOR – F = ((XY) Z)’

The Even parity generator consists of two XOR gates which creates an odd-parity generator. Using an

inverter this can be changed into an Even-parity generator. A third XOR gate be turned into an inverter

by connecting one of the inputs to 5V and the other to the output of the odd-parity generator.

Even-parity function

F = (X’Y’Z’)+(X’YZ)+(X’YZ’)+(X’Y’Z) Sum of the Products - Maxterms

F = (X+Y+Z’)(X+Y+’Z)(X’YZ)(X’Y’Z’) Product of the Sums – Minterms

A 4-bit even packet is the same as the first odd-parity packet except the most significant bit is added

to ensure there’s an even number of bits in the packet. (example - 1100, 1001, 0101 etc.)

Example:

Input – 111

Expected Output – 1111

Actual output – 1111

Even-Parity Truth Table

X Y Z F

0 0 0 1

0 0 1 0

0 1 1 1

0 1 0 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

Fig 6. Simetric even-parity generator schematic

Fig 7. Even-parity truth table

4

The fact that the first bit is a 1 and an even parity bit is being used in this example one can tell that

the packet has an odd number of bits as a 1 was added to make it even.

The same problem as the odd parity bit could be encountered i.e. if certain bits were flipped no error

would appear and the data transmitted would appear correct even though it has lost or gained bits.

74HC86

X Y Z

F_Odd-Parity

F_Even-Parity

GRD

5V

Fig 8. Simetrix simulation results

Fig 9. Circuit diagram created using Fritzing

5

Conclusion

The odd-parity logic circuit worked as expected and can be useful in verifying the data transfer

of bits.

An XOR gate can be used as an inverter just by connecting one of it’s legs to power and the

other to the signal that you wish to invert.

The product of the sums and sums of the product are used to create the Boolean function for

the logic circuit.

F_odd-parity F_even-parity

Fig 10. Odd and Even parity outputs from lab X

Z Y

1


Lab: 4



Lab Purpose

Design of a 2-bit binary to 7-segment decoder

Prototype and test the circuit. Debug if necessary.

Model and simulate.

Lab Procedure

The first step in this lab was to design the circuit with use of a truth table and k-maps for each

of the outputs.

Using the seven segment display construct a truth table for the for possible combinations.

The table should be constructed so that the binary input will display it’s decimal conversation

on the seven segment display at the output (remembering that a 0 will turn the LED on as the

component is already connected to power).

Draw the k-maps out for the seven different letters write the expressions and simplify with DE

Morgan’s theorem where necessary so that a minimum amount of components will be used.

Combine the expression to draw the circuit diagram.

Build the circuit systematically starting a a and finishing at g debugging as you go to ensure

the final circuit will work as intended.

Connect the outputs to the LEDs through a resistor.

Test the circuit for each of the 4 configurations.

Build of Materials

Part Quantity

74HC08 1

74HC04 1

74HC32 (Not used) 1

7 segment display 1

10uF Capacitor 2

330Ω Resistors 7

Power Supply 1

Digital Designer 1

Wires -


2

De Morgan’s Theorem

In the lab we were given 3 different ICs each consisting of different logic gates (AND, OR & Invertors).

When design the circuit it’s useful to take into consideration how much materials are being used.

With the use of De Morgan’s theorem the expression for each of the outputs can be converted to a

form where only an AND gate is needed. This means that there is no need to use the OR gate and both

material and money is being saved. (F=u+v ⇒ F'=u'v' ⇒ F=(u'v')'.)

Used Not Used

74HC08 consists of 4 AND gates 74HC32 Consists of 4 OR gates

74HC04 Consists of 5 Inverters

7 Segment display

The circuit has two inputs, 11 being the highest number, 3 in decimal terms. The

function of the digital circuit design is to decode the binary input to light the 7

segment display according to the binary input.

As shown in the figure below the display is connected to power. This means that

to get a segment to light up its pin must be a digital 0 or a LOW.

Each pin must be dealt with separately however as shown below segment b is

constantly on therefore always connected to ground. Also since segment a and

d are on and off at the same time they can be connected to the same output

with a gate to boast the output to power two segments. All segments must also

be connected through a 330Ω resistor.

Fig 2. Logic ICs used and not used

Fig 3. 7 Segment Pins

3

Testing using Logic Lab

The circuit was drawn and on ‘The Logic Lab’ by neuroproductions. This gives a very visual idea of how

the circuit is operating while also acting as a tool to test the configurations.

The outputs were inverted so that the LEDs would light as the segments in the display need a 0 yet yet

the LEDs in the Logic Lab need a 1 to light. Otherwise the circuit is the same as the one built in the lab.

Circuit Diagram tested using Logic Lab

Inputs - (X,Y)/(0,0) Output - 0000001 Inputs - (X,Y)/(0,1) Output - 1001111

Inputs - (X,Y)/(1,0) Output - 0010010 Inputs - (X,Y)/(1,1) Output -

Fig 4. Basic Circuit Schematic and Generated outputs

a

b

c

d

e

f

g

a

b

c

d

e

f

g

a

b

c

d

e

f

g

a

b

c

d

e

f

g

X

Y

X

Y

X

Y

X

Y

Fig 5. Table of Logic Lab simulated outputs

4

Lab Results

Designing the Circuit

The circuit was designed with the aid of a truth

table and then k-maps. K-maps are used to group

outputs together which in turn leads to simplify

the circuit. A culmination of all of the expressions

gathered for each segment can then be added

together after they have been further simplified

using De Morgan’s theorem and fabricated.

Especially in the cases of an and d an Or gate can

be used as shown in the SIMetrix schematic

below to essentially give each segment its own

output

Fig 6. Results generated in the Lab

Fig 7. Truth Table and K-maps

5

This figure shows the final circuit designed using

k-maps. The one OR gate that was needed was

changed to an AND gate with the use of De

Morgan’s theorem. The SIMetrix diagram given

for the lab has the same outputs however it uses

an OR gate as well as two AND gates while also

using OR gates to boost the output

Conclusion

The circuit worked as expected and the circuit was minimised and simplified using a truth table

k-maps and De Morgan’s theorem.

With regard to the outputs a resistor was needed to ensure there was not too much current

flowing through the segments. Also OR gates were used to essentially boost the output where

the same signal was going to two segments.

The designed circuit works as a very simple 7-segment decoder as intended.

Fig 8. Final Circuit

Fig 9. SIMetrix simulation

Fig 10. Fritzing Circuit Diagram

74HC04 74HC08

X

Y

Power Ground

1


Lab: 5



Lab Purpose

Design a 2-bit magnitude comparator.

Simplify the design using K-maps. Model. Simulate.

Part I: Prototype and test the magnitude comparator.

Part II: Prototype an LED brightness control circuit.

Use digital scope to visualise dynamic digital signals.

Lab Procedure

Draw truth table with inputs w(A1), x(A0), y(B1) and z(B0) so that the output F is high when

A>=B.

Draw the K-maps with the max-terms (take F’ as the output) since there are less max-terms

than min-terms to group terms and simplify the circuit. Use De Morgan’s theorem if the circuit

needs to be further simplified.

Simulate the designed circuit to ensure out works as expected before building.

Connect and the output to the gate of a transistor, the source to ground and then the drain

to a resistor to an LED to 5V.

Build and test the circuit running through all 2^4 inputs while debugging using the test probe.

Use the B inputs of the 2-bit magnitude comparator as the inputs to control the LED’s

brightness. Wire up the remaining A inputs to two 74LS74s a per the diagram below.

Connect a signal generator at 1KHz to the 74LS74s.

Test the second circuit running through the 4 combinations observing the LED’s brightness

vary from 25% to 100%.

Build of Materials

Part Quantity

74HC11 1

74HC27 1

74LS74 2

LED 1

10uF Capacitor 1

220Ω Resistor 1

Pnp transistor 1

Digital Designer 1

Wires -


2

Component Overview

BS107 N-Channel MOSFET Transistor

The drain of the transistor is connected to a resistor an LED and

then 5V, the source to ground. Simply put when a HIGH signal

appears at the gate pin, the characteristics of the semiconductor

changes so that it now conducts and allows a current to flow

from the drain to the source

Flip flop d-type latch

The d-type latch serves to divide the clock by two,

meaning the output of the first latch going to X is 500Hz.

The pin D on the first latch is connected to the clock on

the second latch. The output at D is inverted and at 500Hz

meaning the output of the second latch going to W is an

inverted signal at 250Hz.

74HC11 consists of 3 AND gates 74HC27 Consists of 3 NOR gates

74LS74 Magnitude Comparators

Fig 2. Table of ICs

Fig 3. BS107 B-Channel

MOSFET

Fig 4. Flip flop d-type latch

3

Part 1 (Magnitude Comparator)

The first part of the lab entails designing and building a magnitude comparator. The circuit is designed

and simplified using a truth table and a k-map. Essentially the magnitude comparator outputs a High

when A>=B. This is signified by an LED that turns on when the output is High i.e. when A>=B.

The min terms from the truth table are copied to a

k-map, to minimise the digital circuit. Since there

are more ones than zeroes, it would be more

efficient to look at the k-map with respect to the

zero terms, generate a function and then invert that

function.

Generated function – (YW’)+(W’X’Z)+(X’YZ)

There is 3 AND gates and 3 NOR gates available to

use. NOR gates can be used as inverters, they can

be used to invert the signals W and X and then the

final function output.

The k-map was used to minimise the

function looking at the 0 terms constructing

a function and then inverting it. This

approach is quicker than looking at all the

ones since there are more of them.

The first step is to look for groups of 4 which

in this case is denoted by YX’. Then the two

groups of two. It is observed that min-term

3 is captured by all three term however this

is the most minimised function for A>=B.

Truth Table

W(A1) X(A0) Y(B1) Z(B0) F

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 1

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Fig 5. Truth for function F=(A>=B)

Fig 6. K-map

4

After the circuit is drawn it’s

modelled in Simetrix. This

allows you to check whether

the function that you

designed using the truth

table and k-map works for

every combination of the

inputs. This simulated

waveform output in Simetrix

checked against the truth

table will tell you whether or

not the function that you’ve

generated is correct or not.

Fig 7. Simetrix logic circuit schematic

Fig 8. Wiring diagram drawn with Fritzing

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5

Part 2 (LED Brightness Control)

The second part of the lab includes building an LED brightness control circuit. The circuit is built of the

magnitude comparator circuit. Two d-type latches are connected to the A inputs. It essentially

incorporates PWM (Pulse with modulation) using it to control the brightness of an LED. This is a better

option than using a variable resistor method as there is no power dissipation. If the clock is set to a

low frequency in this circuit the LED can visibly be seen as the signal goes high and low.

The circuit is simulated in Simetrix which

gives a wave output the all the signals

generated by W,X,Y and Z. It’s clear that X is

half the clock frequency and W is half that

of X which means that it’s a quarter of the

clock frequency.

The percentage of combinations where

A>=B when B is 00 is 100% of them. This

means that the output F is constantly on.

The percentage of combination where

A>=B when B is 01 is 75% therefore the LED

is on for 75% of the time and since the LED

is going of for 12.5% of the time twice in a

cycle very fast the naked eye sees the LED

at 75% brightness.

The same logic applies for 10 and 11.

Fig 9. LED brightness control circuit

Fig 10. Simulated results in Simetrix

6

Conclusion

The function that was designed using the truth table and the k-maps worked as per the

specifications.

Both circuits worked as intended when tested for all possible input combinations.

The oscilloscope readings mirrored those seen when the circuit was simulated in Simetrix.

The pulse with modulation method is a lot more efficient than the variable resistor as there is

no power dissipation resistor.

Fig 11. Circuit from lab Fig 12. Oscilloscope readings

from lab

00 – 100%

01– 75%

10 – 50%

11 – 25%


Lab: 6



Lab Purpose

Prototype a 2-bit plus carry-in ripple-carry adder.

Use a BCD-to-7-segment driver to display 3-bit result.

Test, debug and document results.

Measurement of up and down propagation delay CIN to COUT.

Lab Procedure

Prepare for the lab before the scheduled lab time by studying the half adders and

understanding how the propagation of the carry works

Complete a truth table for the expected output based on the some of the two bit packages A

and B

Gather all the component needed to build the circuit and plan building your circuit on the

digital designer.

After the circuit is built first test the LCD decoder is giving the expected output by connecting

pins A, B and C to switches.

Then connect them to the outputs of the carry in ripple adder. Debug the circuit ensuring that

the output mirrors that of the truth table that you prepared before the lab.

Finally use the oscilloscope to measure the propagation delay of the carry in ripple adder

Build of Materials

Part Quantity

74HC08 1

74HC32 1

74LS47 1

7 segment LCD 1

330Ω Resistors 7

Oscilloscope 1

Digital Designer 1

Wires -

Build of materials

Truth Table

The truth table describes the basis of the lab. There’s

two, two bit binary packages and a carry bit as an

input. The half adders add both the most significant

and least significant bit of each binary package A and B

as well as rippling the carry bit to the next half adder

and recombine them on output to output a 3 bit

output package consisting of C0, S1 and S0.

The truth table is represented in signal form in the

figure below. This gives a visual representation of how

the inputs change systematically and how the output

responds.

The carry bit is part of the output packet. This 3 bit

packet is then fed into the LCD coder where the output

of the decoder is read on the LCD for the user to debug

the circuit.

The carry in ripple full adder consists of two half adder

connected together. The half adder adds a single bit of

each package together. The sum of the bits is then

added to the output binary packet.

A1 A0 B1 B0 C1 C0 S1 S0

0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 1

0 0 0 1 0 0 0 1

0 0 0 1 1 0 1 0

0 0 1 0 0 0 1 0

0 0 1 0 1 0 1 1

0 0 1 1 0 0 1 1

0 0 1 1 1 1 0 0

0 1 0 0 0 0 0 1

0 1 0 0 1 0 1 0

0 1 0 1 0 0 1 0

0 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1

0 1 1 0 1 1 0 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 1

1 0 0 0 0 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 0 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 0 1 0 0

1 0 1 0 1 1 0 1

1 0 1 1 0 1 0 1

1 0 1 1 1 1 1 0

1 1 0 0 0 0 1 1

1 1 0 0 1 1 0 0

1 1 0 1 0 1 0 0

1 1 0 1 1 1 0 1

1 1 1 0 0 1 0 1

1 1 1 0 1 1 1 0

1 1 1 1 0 1 1 0

1 1 1 1 1 1 1 1

Truth Table

Full Adder

Timing graph of adder (excluding the instantaneous spikes)

Simetrix Analysis

The Simetrix simulation shows how the outputs change with regard to the different combinations of

inputs. The instantaneous spikes seen in the time graph are caused by two of the inputs changing from

a high to a low therefore being undefined digitally momentarily. The theoretical graph gives a greater

insight into the workings of the how the digital carry in ripple adder works.

LCD and Decoder

The LCD part of the circuit consists of 4 bit 7 segment decoder and an LCD. The decoder is an IC chip

that has 4 inputs, 3 of which are used in this lab (The final input D being grounded) and the 7 outputs

to the LCD which are connected to the LCD pins through 330 ohm resistors.

Circuit Diagram

Measure CI to CO Propagation Delay

The final part of the lab consisted of measuring the delay due to the ripple of the carry bit. First the

inputs are set as follows B1=1, B0=0, A1=0, A0=1 with the LCD displaying a 4. The carry input C1 is then

connected to a pulser Push to make button. This means when the pulser button is pressed the carry

out button is changed from a zero to a 1 which means it’s rippled through the adder system.

Advantages and Disadvantages

The carry in ripple adder has both disadvantages and advantages.

The main advantage is the fact that it’s a simple system to understand and implement as well as being

saleable, i.e. multiple half adders can be added to each other to add any amount of bits.

The major disadvantage with this type of adder is the fact that the carry bit must propagate along each

half adder meaning that it will take time to produce a final result as well as outputting an incorrect

result momentarily.

Theoretical delay (rising) 30ns

Theoretical delay (falling) 25ns

Experimental delay (rising) 36ns

Experimental delay (falling) 23ns

Combination to measure delay

Conclusion

The carry in ripple adder worked as expected with some debugging by splitting the circuit into various

part and pin pointing the problem of the 4 not displaying initially.

The carry in ripple adders main disadvantage is the ripple delay. On the flip side it’s clear that the

system could be extended with ease and without much planning.

It’s very important to plan a digital circuit such as this carry in ripple adder otherwise you’ll run into

problems in building the circuit.

The values for the ripple delay were slightly off and a lot of noise was present in the waves. This could

be due to the fact that the

Circuit built in lab

1


Lab: 7



Lab Purpose

Relaxation oscillator, counter, decoder circuit.

Synchronous binary counter with preset.

Modulo-6 counter.

3-to-8-line decoder, driving 6 LEDs.

Lab Procedure / Summary

Read the lab document before the scheduled lab time to give you a better understanding of

the operation of the digital system.

Collect all the components needed to build the circuit as shown in the build of materials table

below.

Build the circuit as shown in the circuit diagram paying careful attention to ensure that pins A

through to D are grounded on the 74HC193 to avoid the inputs drifting randomly and causing

subtle problems.

Observe the 7 segment display and ensure that the segments are lighting up one by one

excluding g and pausing for 2 clock cycles between f and a (approx. 0.5 of a second).

To get rid of this delay connect Y6 i.e. the pin that will be low when the binary counter reaches

110, to the LOAD pin on the 74HC193. This will essentially reset the counter.

Finally connect the scope to Y6 of U3 and try to quantify the duration of its low period, i.e. the

time taken for the counter to reset.

Build of Materials

Part Quantity

74HC074 1

74HC193 1

74HC138 1

7 segment LCD 1

220Ω Resistor 1

100uF capacitor 1

100nF capacitor 3

Oscilloscope 1

Digital Designer 1

Wires -

Figure 1. Build of Materials

2

74HC193 – Binary counter

The 74HC194 is a 4-bit binary counter. Its flexible

component in terms of the control the user has over the

count when designing the circuit. In the case of this

circuit we’re implementing the counter as one which

count 000 through to 111 or 0 to 7 in decimal annotation.

This count is then fed into a 7 segment decoder which is

discussed below. The output of the relaxation oscillation

circuit i.e. the square wave signal is fed to the clock UP

input of the counter. The clock down is pulled high to 5V. This

causes the clock to count up changing by a bit on every rising

clock edge.

The clear is tied to ground since the counter is never cleared. Pins A through to D are also tied low.

This allows you to connect the output of Y6 to the LOAD pin. This means that every time Y6 is low

(which is not connected to any segment) the LOAD pin ‘loads’ A through to D i.e. 0000 to QA through

to QD. This means that there’s no longer a period of just under half a second (two full cycles) to wait

before segment a is lit again.

3-8 Line Decoder

This decoder is set up in this circuit so that the

decimal annotation of the binary input is taken

and the equivalent output pin (Y0 – Y7) is tied

low. In this case Y6 and Y7 are not used so when

the binary output values are both 6 and 7 no

segment is lit up so there appears to be a pause

which last 2 clock cycles. This is corrected by

connecting Y6 to the LOAD pin in the binary

counter which ‘loads’ the values in the pins A to

D which is 0000.

As seen below the decoder is configured as it is

in the circuit to enable one of the outputs to

output 0 one pin at a time which means one

segment at a time will be lit. at a time. The internal schematic diagram for the decoder is shown below

consisting of AND gate and inverters. The inputs E1, E2 and E3 are configure to output a one since the

output goes to one of the four pins of each gate. Taking the example where A0, A1 and A2 are 0 all

the inputs are inverted and fed to the remaining three pins of the AND gate at Y0 meaning the gate

outputs a 1 which is then inverted so that the output at Y0 when the input is 000 is a low, lighting up

the segment a.

A2 A1 A0 Decoder Output Pin

Low

0 0 0 Y0

0 0 1 Y1

0 1 0 Y2

0 1 1 Y3

1 0 0 Y4

1 0 1 Y5

1 1 0 Y6

1 1 1 Y7

Figure 2. Binary counter

Figure 3. Truth table to show when Yx is low

Figure 4. Decoder digital schematic

3

The 7 segment display is powered by a 5V power supply. There is no need for a resistor to be

connected to each pin as there’s a 220ohm resistor connected to the power supply which is sufficient

to limit the amount of current flowing through each segment.

Initial Frequency = 1/ (0.73*10,000*0.0001) = 1.4Hz

Increasing the clock frequency by about three orders of magnitude.

Increased frequency = (1.4*10^3) =1400Hz

This gives the effect that the 7 segment display is displaying a zero even though each segment is

displayed one by one. This is because the human eye perceives it as a zero.

Y0 is used as the trigger so that the oscilloscope shows the complete duration from Y0 to Y5 and then

the trigger on Y6.

Experimental Plots on oscilloscope

This plot shows the improved circuit. The green

channel represents Y0 which goes low (lighting the

LED) once every six cycles.

Figure 5. Circuit Diagram

Figure 6. Oscilloscope screenshots Y0

4

This shows how long it takes for the LOAD pin to reset the input to 000. When measured with the

cursors on the oscilloscope it was measured at about 58 nano seconds.

Conclusion

The circuit worked as expected, the segments lit up in a clockwise pattern from a to f with a

pause after f. When the frequency was increased it gave the impression that the display was

displaying a zero.

The LOAD pin along with pins A, B, C and D can be used to reset the counter or alternatively

start the counter from a given number.

The oscilloscope screenshots taken in the lab confirm my understanding of the digital

relaxation circuit.

Figure 7. Oscilloscope screenshots reset delay

Figure 8. Circuit bench setup in Lab

Ciarán O’ Mara - Student ID: 15154394 · 1 Module: Digital Systems 1 EE4522 Lab: 3 Student name: Ciarán O’ Mara Student ID: 15154394 Lab Purpose Analyse, build and test a 3-

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