C.I 74HC00

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1. General description

The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC

standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC00; 74HCT00 provides a quad 2-input NAND function.

2. Features and benefits

Input levels:

For 74HC00: CMOS level

For 74HCT00: TTL level

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

74HC00; 74HCT00Quad 2-input NAND gate

Rev. 5 25 November 2010 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC00N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT00N

74HC00D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT00D

74HC00DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT00DB

74HC00PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT00PW

74HC00BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 3 0.85 mm

SOT762-1

74HCT00BQ

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74HC_HCT00 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 5 25 November 2010 2 of 16

NXP Semiconductors 74HC00; 74HCT00Quad 2-input NAND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

mna212

1A1Y

1B

1

23

2A2Y

2B

4

56

3A3Y

3B

9

108

4A4Y

4B

12

1311

mna246

31

2&

64

5&

89

10&

1112

13&

mna211

A

B

Y

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14

74HC0074HCT00

1A VCC

1B 4B

1Y 4A

2A 4Y

2B 3B

2Y 3A

GND 3Y

001aal323

1

2

3

4

5

6

7 8

10

9

12

11

14

13

001aal324

74HC0074HCT00

GND(1)

Transparent top view

2Y 3A

2B 3B

2A 4Y

1Y 4A

1B 4B

GND

3Y

1A

VCC

6 9

5 10

4 11

3 12

2 13

7 8

1 14

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

1A to 4A 1, 4, 9, 12 data input

1B to 4B 2, 5, 10, 13 data input

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6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = dont care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

1Y to 4Y 3, 6, 8, 11 data output

GND 7 ground (0 V)

VCC 14 supply voltage

Table 2. Pin description continued

Symbol Pin Description

Table 3. Function table[1]

Input Output

nA nB nY

L X H

X L H

H H L

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA

IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V[1] - 20 mA

IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA

ICC supply current - 50 mA

IGND ground current 50 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation[2]

DIP14 package - 750 mW

SO14, (T)SSOP14 and

DHVQFN14 packages

- 500 mW

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8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC00 74HCT00 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VI input voltage 0 - VCC 0 - VCC V

VO output voltage 0 - VCC 0 - VCC V

Tamb ambient temperature 40 +25 +125 40 +25 +125 C

t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74HC00

VIH HIGH-level

input voltage

VCC = 2.0 V - 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V - 2.4 - 3.15 - 3.15 - VVCC = 6.0 V - 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage

VCC = 2.0 V - 0.8 - - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 - - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 - - 1.8 - 1.8 V

VOH HIGH-level

output voltage

VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V - 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V - 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V - 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V - 5.81 - 5.34 - 5.2 - VVOL LOW-level

output voltage

VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 0 - - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V - 0 - - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 - - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 - - 0.33 - 0.4 V

II input leakage

current

VI = VCC or GND;

VCC = 6.0 V

- - - - 1 - 1 A

ICC supply current VI = VCC or GND; IO = 0 A ;

VCC = 6.0 V

- - - - 20 - 40 A

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10. Dynamic characteristics

CI input

capacitance

- 3.5 - - - - - pF

74HCT00

VIH HIGH-level

input voltage

VCC = 4.5 V to 5.5 V - 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage

VCC = 4.5 V to 5.5 V - 1.2 - - 0.8 - 0.8 V

VOH HIGH-level

output voltage

VI = VIH or VIL; VCC = 4.5 V

IO = 20 A - 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA - 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage

VI = VIH or VIL; VCC = 4.5 V

IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V

IO = 5.2 mA; VCC = 6.0 V - 0.15 - - 0.33 - 0.4 V

II input leakage

current

VI = VCC or GND;

VCC = 6.0 V

- - - - 1 - 1 A

ICC supply current VI = VCC or GND; IO = 0 A ;

VCC = 6.0 V

- - - - 20 - 40 A

ICC additional

supply current

per input pin;

VI = VCC 2.1 V; IO = 0 A ;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

- 150 - - 675 - 735 A

CI input

capacitance

- 3.5 - - - - - pF

Table 6. Static characteristics continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

Table 7. Dynamic characteristics

GND = 0 V; CL = 50 pF; for load circuit seeFigure 7.

Symbol Parameter Conditions 25 C 40 C to +125 C Unit

Min Typ Max Max

(85 C)

Max

(125 C)

74HC00

tpd propagation delay nA, nB to nY; see Figure 6[1]

VCC = 2.0 V - 25 - 115 135 ns

VCC = 4.5 V - 9 - 23 27 ns

VCC = 5.0 V; CL = 15 pF - 7 - - - ns

VCC = 6.0 V - 7 - 20 23 ns

tt transition time see Figure 6 [2]

VCC = 2.0 V - 19 - 95 110 ns

VCC = 4.5 V - 7 - 19 22 ns

VCC = 6.0 V - 6 - 16 19 ns

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[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W):

PD = CPD VCC2 fi N + (CL VCC2 fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CL VCC2 fo) = sum of outputs.

11. Waveforms

CPD power dissipation

capacitance

per package; VI = GND to VCC [3] - 22 - - - pF

74HCT00

tpd propagation delay nA, nB to nY; see Figure 6[1]

VCC = 4.5 V - 12 - 24 29 ns

VCC = 5.0 V; CL = 15 pF - 10 - - - ns

tt transition time VCC = 4.5 V; see Figure 6[2] - - - 29 22 ns

CPD power dissipation

capacitance

per package;

VI = GND to VCC 1.5 V

[3] - 22 - - - pF

Table 7. Dynamic characteristics continued

GND = 0 V; CL = 50 pF; for load circuit seeFigure 7.

Symbol Parameter Conditions 25 C 40 C to +125 C Unit

Min Typ Max Max

(85 C)

Max

(125 C)

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. Input to output propagation delays

001aai814

nA, nB input

VI

GND

VOH

VOL

nY output

tTHL tTLH

VM

VM

VX

VY

tPHL tPLH

Table 8. Measurement points

Type Input Output

VM VM VX VY

74HC00 0.5VCC 0.5VCC 0.1VCC 0.9VCC

74HCT00 1.3 V 1.3 V 0.1VCC 0.9VCC

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Test data is given in Table 9.

Definitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 7. Load circuitry for measuring switching times

001aah768

tW

tW

tr

trtf

VM

VI

negative

pulse

GND

VI

positive

pulse

GND

10 %

90 %

90 %

10 %

VM VM

VM

tf

VCC

DUT

RT

VI VO

CL

G

Table 9. Test data

Type Input Load TestVI tr, tf CL

74HC00 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL

74HCT00 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL

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12. Package outline

Fig 8. Package outline SOT27-1 (DIP14)

UNIT Amax.

1 2 (1) (1)b1 c D(1)ZE e MHL

REFERENCESOUTLINE

VERSION

EUROPEAN

PROJECTIONISSUE DATE

IEC JEDEC JEITA

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-199-12-27

03-02-13

Amin.

Amax.

bmax.

wMEe1

1.73

1.13

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.050.2542.54 7.62

8.25

7.80

10.0

8.32.24.2 0.51 3.2

0.068

0.044

0.021

0.015

0.77

0.73

0.014

0.009

0.26

0.24

0.14

0.120.010.1 0.3

0.32

0.31

0.39

0.330.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

MH

c

(e )1

ME

A

L

sea

tingp

lane

A1

w Mb1

e

D

A2

Z

14

1

8

7

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

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Fig 9. Package outline SOT108-1 (SO14)

UNITA

max.A1 A2 A3 bp c D

(1) E(1) (1)e HE L Lp Q Zywv

REFERENCESOUTLINE

VERSION

EUROPEAN


IEC JEDEC JEITA

mm

inches

1.750.25

0.10

1.45

1.250.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.81.27

6.2

5.8

0.7

0.6

0.7

0.3 8

0

o

o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

X

w M

AA1

A2

bp

D

HE

Lp

Q

detail X

E

Z

e

c

L

v M A

(A )3

A

7

8

1

14

y

076E06 MS-012

pin 1 index

0.0690.010

0.004

0.057

0.0490.01

0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.150.05

1.05

0.0410.244

0.228

0.028

0.024

0.028

0.0120.01

0.25

0.01 0.0040.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

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Fig 10. Package outline SOT337-1 (SSOP14)

UNIT A1 A2 A3 bp c D(1) E (1) e HE L Lp Q Zywv

REFERENCESOUTLINE

VERSION

EUROPEAN


IEC JEDEC JEITA

mm0.21

0.05

1.80

1.650.25

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.20.65 1.25 0.2

7.9

7.6

1.03

0.63

0.9

0.7

1.4

0.98

0

o

o0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-199-12-27

03-02-19

(1)

w Mbp

D

HE

E

Z

e

c

v M A

X

A

y

1 7

14 8

AA1

A2

Lp

Q

detail X

L

(A )3

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

A

max.

2

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Fig 11. Package outline SOT402-1 (TSSOP14)

UNIT A1 A2 A3 bp c D(1) E (2) (1)e HE L Lp Q Zywv

REFERENCESOUTLINE

VERSION

EUROPEAN


IEC JEDEC JEITA

mm0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.30.65

6.6

6.2

0.4

0.3

0.72

0.388

0

o

o0.13 0.10.21


Notes


2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-15399-12-27

03-02-18

w Mbp

D

Z

e

0.25

1 7

14 8

AA1

A2

Lp

Q

detail X

L

(A )3

HE

E

c

v M A

XA

y

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

A

max.

1.1

pin 1 index

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Fig 12. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1 EhbUNIT ye

0.2

c

REFERENCESOUTLINE

VERSION

EUROPEAN


IEC JEDEC JEITA

mm3.1

2.9

Dh

1.65

1.35

y1

2.6

2.4

1.15

0.85

e1

20.30

0.18

0.05

0.000.05 0.1


SOT762-1 MO-241 - - -- - -

0.5

0.3

L

0.1

v

0.05

w

0 2.5 5 mm

scale

SOT762-1DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1

c

detail X

yy1 Ce

L

Eh

Dh

e

e1

b

2 6

13 9

8

71

14

X

D

E

C

B A

02-10-17

03-01-27

terminal 1

index area

AC

C

Bv M

w M

E(1)

Note


D(1)

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13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

LSTTL Low-power Schottky Transistor-Transistor Logic

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT00 v.5 20101125 Product data sheet - 74HC_HCT00 v.4

Modifications: Figure note [1] of Figure 5: changed.

74HC_HCT00 v.4 20100111 Product data sheet - 74HC_HCT00 v.3

74HC_HCT00 v.3 20030630 Product data sheet - 74HC_HCT00_CNV v.2

74HC_HCT00_CNV v.2 19970826 Product specification - -

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15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term short data sheet is explained in section Definitions.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL http://www.nxp.com.

15.2 DefinitionsDraft The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warranty and liability Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (inc luding - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

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contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial saleof NXP Semiconductors.

Right to make changes NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use in automotive applications This NXP

Semiconductors product has been qualified for use in automotiveapplications. The product is not designed, authorized or warranted to be

suitable for use in medical, military, aircraft, space or life support equipment,

nor in applications where failure or malfunction of an NXP Semiconductors

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equipment or applications and therefore such inclusion and/or use is at the

customers own risk.

Applications Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customers sole responsibility to determine whether the NXP

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products planned, as well as for the planned application and use ofcustomers third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customers applications or products, or the application or use by customers

third party customer(s). Customer is responsible for doing all necessary

testing for the customers applications and products using NXP

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the products or of the application or use by customers third party

customer(s). NXP does not accept any liability in this respect.

Limiting values Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

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applying the customers general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short ] data sheet Development This document contains data from the object ive specification for product development.

Preliminary [short ] data sheet Quali fication This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

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Export control This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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NXP B.V. 2010. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 25 November 2010

Document identifier: 74HC_HCT00

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section Legal information.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Contact information. . . . . . . . . . . . . . . . . . . . . 15

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

C.I 74HC00

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