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Chng 3: Tp lnh my tnh
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Chng 3: Ni dung chnh Gii thiu v tp lnh Khun dng v cc thnh phn ca lnh Cc dng ton hng lnh Cc ch a ch Mt s dng lnh thng dng
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Gii thiu chung Lnh l mt t nh phn m thc hin mt thao tc
c nh ngha trc ca VXL Lnh c lu trong b nh
Lnh c c t b nh vo CPU thc hin Mi lnh c chc nng ring ca n
Lnh c chia thnh cc nhm: chuyn d liu, tnhton, iu kin v r nhnh,
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Gii thiu chung Qu trnh thc hin/ chy lnh c chia thnh cc pha hay
giai on. Cc lnh c thc hin trong 4 pha: c lnh IF(Instruction Fetch): lnh c c t b nh vo CPU Gii m lnh ID(Instruction Decode): CPU gii m lnh Chay lnh IE(Instruction Execution): CPU thc hin lnh Ghi WB(Write Back): kt qu lnh (nu c) c ghi vo thanh ghi
hoc b nh
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Chu k thc hin lnh Chu k thc hin lnh l khong thi gian m CPU
thc hin xong mt lnh Mt chu k thc hin lnh gm cc pha thc hin lnh
Mt pha thc hin lnh c th gm vi chu k my Mt chu k my gm vi chu k nhp ng h
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Chu k thc hin lnh Mt chu k lnh c th gm c: Chu k nhn lnh Chu k c b nh (memory read)
Chu k ghi b nh (memory write) Chu k c vo/ ra (I/O read) Chu k ghi vo/ra (I/O write) Chu k chp nhn ngt (interrupt acknowledge)
Bus ri (bus idle)
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Khun dng lnh
Khun dng lnh thng thng bao gm 2 phn: M lnh (opcode): mi lnh u c ring mt m a ch cc ton hng: s lng ton hng ph thuc vo
lnh
Opcode Addresses of Operands
Opcode Source addr. Destination addr.
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3 a ch ton hng Khun dng: opcode addr1, addr2, addr3 addr1, addr2, addr3: 1 thanh ghi hoc 1 v tr trong b nh
V d1. ADD R
1
, R2
, R3
; R2
+ R3
R1
R2 cng R3 sau kt qu a vo R1
Ri l cc thanh ghi CPU
2. ADD A, B, C; M[B]+M[C]M[A]
A, B, C l cc v tr trong b nh
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2 a ch Khun dng: opcode addr1, addr2 addr1, addr2: 1 thanh ghi hoc 1 v tr trong b nh
V d1. ADD R1, R2; R1 + R2 R1
R1 cng R2 sau kt qu a vo R1
Ri l cc thanh ghi CPU
2. ADD A, B; M[A]+M[B]M[A]
A, B l cc v tr trong b nh
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1 a ch Khun dng: opcode addr addr: 1 thanh ghi hoc 1 v tr trong b nh
Khun dng ny s dng Racc (thanh ghi tch ly) mc nh cho a ch th 2
V d1. ADD R1; R1 + Racc Racc
R1 cng Racc sau kt qu a vo Racc
Ri l cc thanh ghi CPU
2. ADD A; M[A]+Racc Racc
A l v tr trong b nh
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1.5 a ch Khun dng: opcode addr1, addr2 addr1: thanh ghi, addr2: v tr trong b nh hoc ngc li Kt hp gia cc ton hng thanh ghi v v tr b nh
V d1. ADD R
1, B; M[B] + R
1 R
1
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0 a ch c thc hin trong cc lnh m thc hin cc thao
tc ngn xp: push & pop
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Cc ch a ch Ch a ch l cch thc m cc ton hng c t chc
Mt s ch a ch tiu biu:
Ch a ch tc th
Ch a ch trc tip
Ch a ch gin tip qua thanh ghi
Ch a ch gin tip qua b nh
Ch a ch ch s
Ch a ch tng i
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Ch a ch tc th
Gi tr ca ton hng ngun c sn trong lnh (hng s)
Ton hng ch c th l thanh ghi hoc mt v tr b nh
V d:
LOAD R1, #1000; 1000 R1gi tr 1000 c ti vo thanh ghi R1
LOAD B, #500; 500M[B]
Gi tr 500 c ti vo v tr B trong b nh
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Ch a ch trc tip/ tuyt i
Mt ton hng l a ch ca mt v tr trong b nh cha d liu
Ton hng kia l thanh ghi
V d:
LOAD R1, 1000; M[1000] R1gi tr lu trong v tr 1000 b nh c ti vo thanh ghiR1
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Ch a ch gin tip
Mt thanh ghi hoc mt v tr trong b nh c s dng lu a ch ca ton hng
Gin tip thanh ghi:
LOAD Rj ,(Ri); M[Ri] RjTi gi tr ti v tr b nh c a ch c lu trong Ri vo thanh ghi Rj
Gin tip b nh:
LOAD Ri , (1000); M[M[1000]] RiGi tr ca v tr b nh c a ch c lu ti v tr 1000 vo Ri
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Ch a ch gin tip
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Ch a ch ch s a ch ca ton hng c c bng cch cng thm hng s vo ni dung ca mt thanh ghi, l
thanh ghi ch s
V d
LOAD Ri, X(Rind ); M[X+Rind ] Ri
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Ch a ch tng i a ch ca ton hng c c bng cch cng thm hng s vo ni dung ca mt thanh ghi, l
thanh ghi con m chng trnh PC
V d
LOAD Ri, X(PC); M[X+PC] Ri
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Tng kt cc ch a chCh a ch ngha V d Thc hin
Tc th Gi tr ca ton hng c cha tronglnh
LOAD Ri, #1000 Ri 1000
Trc tip a ch ca ton hng c cha trong
lnh
LOAD Ri, 1000 RiM[1000]
Gin tip thanhghi
Gi tr ca thanh ghi trong lnh l a chb nh cha ton hng
LOAD Ri, (Rj) RiM[Rj]
Gin tip bnh
a ch b nh trong lnh cha a ch bnh ca ton hng
LOAD Ri, (1000) RiM[M[1000]]
Ch s a ch ca ton hng l tng ca hng s(trong lnh) v gi tr ca mt thanh ghich s
LOAD Ri, X(Rind) RiM[X+ Rind]
Tng i a ch ca ton hng l tng ca hng sv gi tr ca thanh ghi con m chngtrnh
LOAD Ri, X(PC) RiM[ X+ PC]
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Mt s dng lnh thng dng Cc lnh vn chuyn d liu
Cc lnh s hc v logic
Cc lnh iu khin
Cc lnh vo/ ra
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Lnh vn chuyn d liu
Chuyn d liu gia cc phn ca my tnh
Gia cc thanh ghi trong CPU
MOVE Ri, Rj ; Rj -> Ri
Gia thanh ghi CPU v mt v tr trong b nh
MOVE Rj,1000; M[1000] -> Rj
Gia cc v tr trong b nh
MOVE 1000, (Rj) ; M[Rj] -> M[1000]
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Mt s lnh vn chuyn d liu thng dng
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Lnh s hc v logic Thc hin cc thao tc s hc v logic gia cc thanh ghi v ni dung b nh
V d:
ADD R1, R2, R3; R2 + R3 -> R1
SUBSTRACT R1, R2, R3; R2 R3 -> R1
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Mt s lnh logic thng dng
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Lnh iu khin/ tun t
c dng thay i trnh t cc lnh c thc hin:
Cc lnh r nhnh (nhy) c iu kin
Cc lnh r nhnh (nhy) khng iu kin
CALL v RETURN
c tnh chung ca cc lnh ny l qu trnh thc hin lnh ca chng lm thay i gi tr PC
S dng cc c ALU xc nh cc iu kin
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Mt s lnh iu khin thng dng
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Cc lnh vo/ ra
c dng truyn d liu gia my tnh v cc thit b ngoi vi
Cc thit b ngoi vi giao tip vi my tnh thng qua cc cng. Mi cng c mt a ch dnh ring
Hai lnh I/O c bn c s dng l cc lnh INPUT v OUTPUT
Lnh INPUT c dng chuyn d liu t thit b ngoi vi vo ti b vi x l
Lnh OUTPUT dng chuyn d liu t VXL ra thit b u ra
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Cc v dCLEAR R0; R0 0M OVE R 1, # 10 0; R1 100
CLEAR R2; R2 0
LOOP:
ADD R0, 1000(R2); R0R0+ M[R2+1000]
INCREMENT R2; R2 R2+1
DECREMENT R1; R1 R1-1
BRANCH_IF>0 LOOP; go to LOOP if R1>0
STORE 2000, R0; M[2000] R0
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Kim tra1. Cho on lnh sau:
ADD R2, (R0);
SUBSTRACT R2, (R1);
MOV 500(R0), R2;
LOAD R2, #5000;
STORE 100(R2), R0;
Bit R0=1500, R1=4500, R2=1000, M[1500]=3000, M[4500]=500
Hy ch ra gi tr ca thanh ghi v ti v tr trong b nh qua mi lnh thc hin.
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Kim tra2. Cho on lnh sau:
MOVE R0, #100;
CLEAR R1;
CLEAR R2;
LAP:
ADD R1, 2000(R2);ADD R2, #2;
DECREMENT R0;
BRANCH_IF>0 LAP;
STORE 3000, R1;
a. Hy gii thch ngha catng lnh
b. Ch ra ch a ch catng lnh (i vi cc lnhc 2 ton hng)
c. on lnh trn thc hincng vic g?