\Setting CMOS Environment for I _ VLSI Design ; A Thesis Presented to The Faculty of the College of Engineering and Technology Ohio University In Partial Fulfillment of the Requirements for the Degree Master of science BY Chih-Ping Chung,# 4 November, 19 89
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\Setting CMOS Environment for I _
VLSI Design ;
A Thesis Presented to
The Faculty of the College of Engineering and Technology
Ohio University
In Partial Fulfillment
of the Requirements for the Degree
Master of science
BY
Chih-Ping Chung,# 4
November, 19 89
ACKNOWLEDGEMENTS
I would like to especially thank Dr. Janusz A. Starzyk
for his inspiration and encouragement to set up CMOS
environment for VLSI design. I also thank the members of my
committee, Dr. Robert A. Curtis, Dr. Henryk J. Lozykowski
and Dr. John D. Gillam, for their invaluable assistance. My
deepest appreciation goes to Mr. Wu-Kai Lee and Mr. Randy Yu
for their efforts and CAD support. Also, thanks to Mr.
Gerald Blackburw and Miss. Elis for their patient
inspiration.
Finally, my great appreciation and acknowledgement goes
to my wife Hsiao-yen Leen and my parents for their endless
support, devotion and love, without which this job could not
CHAPTER 2 . TECHNOIXGY UPGRADE FOR VALID WORKSTATION FROM nMOS TO CMOS ............................. 3 2.1 Introduction ............................... 3 2.2 Comparison between NMOS and CMOS
CMOS(Comp1ementary Metal Oxide Silicon) is the fastest
growing process technology in recent years. This is due to
the two key features of the CMOS technology: higher circuit
density combined with lower power. CMOS has the greatest
impact in low power and medium speed applications such as
industrial control, medical analyzers and most of the
automatic test equipment. CMOS products will continue to be
a popular choice in many designs. The advanced CMOS process
provides higher performance, better noise margin and lower
power consumption than nMOS. Moreover, the feature size of
CMOS has been scaling down continuously. l1 Ten years ago, a
CMOS feature size of 5 to 7.5um was state-of-the-art
technology. By the end of 1986, lum CMOS technology was
available and used increasingly to produce commercial VLSI
chips,It [Masakazu 881. Therefore, it is vital to make this
new technique available to students so that their
qualifications can match the needs of industry.
I1Verification and validation of a design are an even
more difficult challenge, [Mukherjee 861 . The development of powerful circuit design tools and software systems are
the keys to the success of VLSI technology. There are many
kinds of design tools, which are presently used and
developed for integrated-circuit chips, such as Layout
Editors (LED) , Graphics Editors (GED) , circuit extractors and
2
Layout verification System(LVS). All the principle VLSI
design tools at E.C.E. Department are available on Valid
workstations except LVS which is a layout verification tool.
It is an important design tool for VLSI design.
The purpose of this thesis is to set up and test a
complete CMOS VLSI environment on Valid workstations. The
work on this thesis was organized around three major goals:
Goal I: Upgrade old nMOS to advanced CMOS technology
In order to upgrade Valid workstations from nMOS to
CMOS, there were two steps to be done.
1) Setting up CMOS technology and color map files
2) Developing design rules checker program(DRC) for
CMOS technology rules
Goal 11: Installation of LVS in SCALD system
To run Compare 1.3L version on Valid workstations, an
Extract program and special CMOS library was necessary
to be set up.
Goal 111: Designing an example (PD512)
A circuit PD512 was developed as a design example from
functional partitioning through circuit simulation to
LVS . Chapter 2 illustrates how to do an upgrade from nMOS to
CMOS for Valid workstations, and develops CMOS design rules.
How to develop CMOS Extract program and to design a layout
for LVS are described in Chapter 3. Chapter 4 gives a design
example. Finally, further improvements and conclusions are
described in Chapter 5.
C!HAEl%R 2. TECHNOIDGY UPGRADE FOR VALID
WORKSTATION FROM nMOS TO CMOS
2.1 Introduction:
Transistors in nMOS technology with electrons as
majority carriers are called n-channel devices (nM0~) . Holes are majority carriers in p-channel devices (PMOS) . When PMOS and nMOS devices are fabricated on the same substrate, these
devices are called CMOS devices. Since PMOS and nMOS devices
are made on the same substrate, latch-up and die size are of
important concern. At present, there are several approaches
to prevent CMOS from latch-up by making p+ and n+ guard
rings and by using EPI-substrate wafers to achieve smaller
die size for CMOS technology. Furthermore, CMOS circuits
have other advantages over nMOS circuits such as lower power
dissipation and higher noise margin. Therefore, CMOS has
become a very important technology for VLSI.
To upgrade Valid tools from nMOS to CMOS, it is
necessary to change technology and color map files. Since
the CMOS fabrication process is much more complex than nMOS,
CMOS circuits need more layers in these files. The 1.8um
CMOS EPROM process is chosen to produce design rules. For
CMOS EPROM technology 13 layers are typically needed, for
very high speed products, two more layers are required such
as a second metal and via contact.
4
2.2 Comparison between nMOS and CMOS technologies
In nMOS technology p-type high-resistivity silicon
wafers are used as the substrate material. In CMOS
technology special regions must be created for PMOS
transistors. These regions are called wells or tubs. For
this CMOS EPROM process, an n-well is created in a p-type
substrate wafer. comparison between nMOS and CMOS is
described in detail.
1. nMOS technology:
nMOS technology uses enhancement mode transistors with
a positive threshold voltage, and depletion mode transistors
with a negative threshold voltage. These transistors are
used as drivers, loads, and pass transistors to design
functional blocks.
2. CMOS technology:
CMOS technology uses enhancement mode transistors as
drivers, depletion mode transistors as pass transistors, and
complementary transistors as loads.
Since nMOS and CMOS use different mode transistors as
loads, their transfer characteristics are also different.
Fig.2.l shows a transfer characteristic for an inverter when
an nMOS depletion transistor is used as a load. Fig.2.2
shows a transfer characteristic for an invertor with an nMOS
enhancement transistor used as a load. Finally Fig. 2.3
shows a transfer curve with a PMOS transistor used as load.
GND
I I I
I I
I I I I I I I
Non-zero output I I I I I I I
Fig. 2.1 Inverter and its transfer characteristic with nMOS depletion transistor as a load
Fig. 2.2 Inverter and its transfer characteristic with nMOS enhancement transistor as a load
GND I v s s
Fig. 2.3 Inverter and its transfer characteristic with PMOS transistor as a load
8
From Figs.2.1, 2.2 and 2.3, we can summarize the
results of comparisons between nMOS and CMOS inverters as
follows:
a) Noise margin:
There is non-zero output for nMOS and zero output for
CMOS when input is high. Therefore, CMOS has higher noise
margin than nMOS.
b) Power dissipation:
The current of an nMOS inverter flows all the time for
logical 1 inputs, however, current of a CMOS inverter flows
only during logic transition, therefore, CMOS has zero
static power dissipation.
With the new improvements in maskmaking, it is possible
to fabricate devices smaller and smaller in size. The nMOS
circuits become very dense. Maximum power dissipation become
the limiting factor for high density nMOS VLSI chips. In
order to reduce the dc power dissipation, obtain higher
noise margin, and high density of VLSI devices, CMOS is the
obvious choice.
2.3 CMOS technology:
2.3.1 Introduction
An n-well CMOS process, which is currently the most
popular process in CMOS fabrication, will be discussed in
this section. CMOS technology provides both n-channel and p-
channel MOS transistors on the same chip. nMOS transistors
are designed in the p-type substrate, while PMOS transistors
9
are built in the n-well. A simple n-well CMOS fabrication
sequence is shown in Fig.2.4 and a set-up procedure for
layout and design rule checking is discussed in Sections
2.3.3 and 2.3.4.
2.3.2 Description of n-well fabrication process
As an illustration of the fabrication process, a CMOS
inverter example is described. The first step is to define
the n-well regions. To form them, the phosphorus is
implanted into these regions at high-temperature cycle.
After n-well implant, the active regions are defined
for MOS source and drain regions. The formation of active
regions are accomplished through local oxidation of silicon
(Locos process). In this process thick regions of silicon
dioxide are grown on the silicon substrate to provide
isolation between nMOS and PMOS transistors. The thickness
of the field oxide is about 5000 A.
The gate oxides are grown only in the open areas of the
active region. In general, the thickness of the oxide layer
is about 250A. The gate oxides will affect the threshold
voltage of the MOS transistors. When field and gate oxide
growth is finished, the polysilicon deposition will be
made.
Usually the chemical vapor deposition(CVD) process is
used to deposit the polysilicon (poly) layer over the entire
wafer. Poly is used, not only as a gate, but also for
interconnections. We use the dry etching process to remove
1 Formation of n-well regions I *
Formation of the active regions
Field and gate oxide growth
Deposit the polysilicon layer 1 +
N diffusion &
I + P diffusion
I * I CVD deposition of SiO2
Contact cuts I I
Metal l izat ion
I Passivat ion I Packaging
Fig. 2.4 CMOS fabrication sequence
11
the undesired poly which is outside of the gate regions and
the interconnecting patterns. After the thin gate oxide is
etched, we use a n+ mask (n-select mask) to define source
and drain regions of nMOS transistors and implant phosphorus
to obtain low-resistance source and drain regions. In the
same manner, we define the p+ source and drain regions of
PMOS transistors.
The p+ source and drain regions of PMOS transistors are
defined by a negative of the n-select mask. Boron is used as
the dopant in the process step instead of phosphorus, when
completing the implant of p+ and n+ source/drain.
We use a CVD technique to deposit SiOZ over the entire
wafer as an insulating layer.
In order to expose the n+ and p+ areas and connect them
to outside metal, we use a contact mask to define contact
cuts in the insulating layer.
The metallization mask is used to define the
interconnection pattern. Then, the evaporation process is
used to deposit aluminum over the entire wafer, and the
undesired metal is removed by etching.
Passivation is used in the final step of the wafer
fabrication, in order to protect the wafer surface from
contaminants and scratches.
We see from the above discussion that ten layers of
masks are needed for device fabrication in a typical CMOS
process. Layer data is either drawn directly or generated
indirectly from logic operations in Valid CAD systems. The
details are described in 2.3.3.
2.3.3 CMOS colormap and technology files for Valid
workstations
In general, colormap and technology files are needed
only for layout drawing. To create a layout drawing, we need
to specify all the layers. "A technology file defines
various masks and symbolic layers in a cell. This file also
defines the color, fill pattern, and outline pattern used to
display each layer, and references a colormap file that sets
each layer's color^^, (Valid layout EDITOR REFERENCE MANUAL).
Colormap and technology files will be discussed next.
a) Colormap file:
Colormap file determines colors of all layers on the
screen. The red, green and blue colors are the three basic
colors. The color of combination layers is determined by the
intensities of the red, green, and blue color. The intensity
values ranges from 0 (off) to 255 (maximum intensity) . We can change the color of layers by using PED(Pa1ette Editor
Display). The format of the colormap file is:
[red green blue color number]
Color number is associated with technology file, the colors
of different layers are shown below:
The p active layer would be in yellow on a color
graphics.termina1.
The n active layer is in green
The polysilicon layer (poly2) is in red
The metal layer is in blue
The contact cut is cross
The n-well layer is dashed line
An example of CMOS color map file is presented below:
[red, green, blue, color member]
178 94 183 1
0 200 0 2
250 100 0 3
Column 1 is red, column 2 is green and column 3 is
blue, number 178 is intensity value of red, 94 is intensity
value of green, 183 is intensity value of blue, 1 is color
number corresponding to the color number of technology file.
To change the color of a layer, we can call up the PED
display by entering this command:
PED
Then select the EDIT command from the PED display (Fig.2.5)
and select the layer to edit. There are several ways to pick
layers:
1. Pick layers from the layer menu
2. Select one or more layers from the active palette
3. Type layer names at the keyboard
To obtain the desired color, we need to adjust the intensity
values of red, green and blue. When you want to exit from
14
PED, use the QUIT command. A physical CMOS color map file is
shown in Appendix A-1.
b) Technology file:
Different mask symbolic layers and the unit sizes are
described in a technology file. The first line of the file
is the name of the technology such as nMOS, CMOS etc. The
second line is the name of the colormap file to be used with
the technology. The third line contains three numbers
separated by spaces. The first number specifies the number
of centimicrons such as 100 for microns and 254 for mils
(lmil =25.4um) . Most companies use micron instead of mils
in current development. The second number is the grid
spacing and the third number is the grid interval in this
technology. Each layer in the technology file is described
888 100 0.10 2 po ly l 0 s o l i d 1 "wire-width" = "2" " p r e f i x " = "PI:" , pf f f f f s t i p p l e 2 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0 "wire-width" = "2"
n a c t i v e 0 s o l i d 2 "wire = "2" Wprefix" = " "
metal 0 s o l i d 4 n u i r e = " 2 " "pre f ix" = " M : "
p a c t i v e 0 s o l i d 8 "wire-width" = "2" " p r e f i x " = " "
poly2 0 s o l i d 16 "wire-width" = "0.6" " p r e f i x " = "P2:" , c o n t a c t f f f f c r o s s 32 "wire-width" = "2" " p r e f i x " = " "
d e p l e t i o n f 9 f 9 empty 16 "wi re -wid th" = " 2 " " p r e f i x " r " "
nwell c5c5 empty 8 "wire width" = "2" " p r e f i x " = " " , c e l l f0 f0 empty 4 "wire widthn = "2" " p r e f i x n = "" , pad i f 0 0 empty 16 9
s a c i f f f empty 16
a c t i v e f f f f . t i p p l e 4 240 240 240 420 810 1008 c007 0 0 c007 1008 810 420 240 240 240 , pplus f f f f s t i p p l e 8 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080 > nplus f f f f s t i p p l e 16 f f f f O O O O O O O f f f f O O O O O O O
hvim f f f f s t i p p l e 2 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080
mhvim f f f f s t i p p l e 8 f f f f O O O O O O O f f f f 0 0 0 0 0 0 0
p f i e l d f f f f s t i p p l e 1 240 240 240 420 810 1008 coo7 0 0 coo7 1008 810 420 240 240 240
e r r o r s f f f f s t i p p l e 8 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0 .
To define a set of design rules for 1.8 micron N-WELL
CMOS EPROM process technology. The rules are capable of
handling up to 10% linear shrink.
2.0 Drawn layers:
Layer name Description GDS layer
n-WELL 1
Active Both n+ and p+ diffusion 41
N Active n+ diffusion region 2
P Active p+ diffusion region 12
Cell Implant EPROM cell threshold adjustment 5
Poly I Used as the floating gate 6
Depl Implant To open up depletion transistor 7
Poly I1 Control gate and peripheral gate 11
SAE Etch protection during self align 42
poly etch
P+ Implant Open up p diffusion area
Contact
Metal
Pad
3.0 Remaining layers:
Layer name Description GDS layer
Active Merge of n active and p active 41
P-f ield Oversizing n-WELL by 3.5u/side 21
N+ Implant Same data as P+ Implant 14
4.0 Mask set required and alignment sequence:
Mask name
n-WELL
Active
p-f ield
Cell implant
POLY I
Depletion implant
POLY I1
SAE
n+ implant
p+ implant
Contact
Metal
Pad
P.R. Field
D
C
C
D
C
D
C
D
C
D
D
C
D
Align to
major flat
1
1
5.0 Generalized layout rules
Assumption:
5.0.1 The drawn dimension equals the physical
dimension on the wafer. There is dimension
skew for some layers to compensate for
process/etching bias.
5.0.2 Direct misalignment on stepper---------- 0 . 5 ~
Indirect misalignment on stepper-------- 0 . 7 ~
5.0.3 All units listed below are in microns.
5.0.4 Design greater than the minimum is
preferred, whenever a more conservative
layout will not impact the chip size.
5.0.5 Any deviation from these design rules must
be fully documented for review at the time
of the composite review.
5.1 N-WELL LAYER
5.1.1 Minimum width 5.1.2 Minimum spacing
N-WELL
N-WELL
5.2 ACTIUE LAYER
5.2.1 Minimum width 5.2.2 Minimum spacing
5.2.2.1 Low voltage 5.2.2.2 High voltage 5.2.2.3 Medium high voltage
5.2.3 N+ diffusion outside well to well 5.2.4 N+ diffusion inside well to well 5.2.5 P+ diffusion outside well to well 5.2.6 P+ diffusion inside well to well
I : t I I
I I I I
LOW 5.2.2.1 I I L..\.....=.........I
High 5.2.2.2 Medium 5.2.2.3
5.3 CELL IMPLANT LAVER
5.3.1 Minimum ouerlap of POLY 2 gate 1 .O
5.3.2 Minimum ouerlap of diffusion (ACTIUE) 2.0
5.3.3 Minimum spacing to unrelated diffusion 2 .O
AGUOVE
\/
1 I
POLY 2
*\ IMPLANT
YYYYY
5.381 ; Y I Y
Y
Y
le, X
8 5.3.2 Y
Y Y Y l Y Y Y Y Y Y Y Y Y Y Y Y Y Y l Y Y Y l l Y l Y
~YYYYYY.Y'!YYYYYYYY.LYYY!'YYY.YYYY
5.4 POLY 1 LAYER
5.4.1 Minimum gate length for natiue transistor 5.4.2 Minimum spacing 5.4.3 Minimum POLY I extension onto field 5.4.4 Minimum spacing of POLY I on field to
unrelated diffusion 5.4.5 Minimum spacing of extended POLY I onto
field to diffusion 5.4.6 Minimum ouerlap of diffusion at drain side
in memory core 5.4.7 Minimum diffusion extension from POLY I 5.4.8 Minimum ouerlap of channel in core 5.4.9 Minimum POLY I width
. . ~ C T I UE POLY I-r 'x .. .*\
C A E
5.5 DEPLETION IMPLANT LAYER
5.1.1 Minimum oveerlap of gate in the direction of current flow 2 .O
5.5.2 Minimum spacing to unrelated diffusion 2.0
POLY 2
5.6 POLY2 LAYER 5.6.1 Min imum gate leng th
5.6.1.1 Low vol tage and core 5.6.1.2 High uo l tage
5.6.2 Min imum spacing 5.6.3 Min imum POLY2 extension on to f i e l d 5.6.4 Min imum spacing f r o m POLY2 on f ie ld
t o unre la ted d i f fus ion 5.6.5 Min imum spacing f r o m end cap t o
unre la ted d i f fus ion 5.6.6 Min imum over lap o f d i f fus ion 5.6.7 Min imum POLY2 w i d t h
5.9.4 Minimum spacing from diffusion contact to gate
5.9.5 Minimum ouerlap to : 5.9.5.1 POLY I I 5.9.5.2 POLY I without POLY l l cross 5.9.5.3 POLY I with POLY I I cross
5.9.6 A l l POLY contact location field oxide only
5.1 0 METAL L A Y E R
5.1 0.1 Minimum width
5.1 0.2 Minimum spacing
5.10 3 Minimum ouerlap o f contact
METAL &
POL
5.1 1 PAD L A Y E R
5.1 1.1 Minimum size 100~100 5.1 1.2 Minimum overlap to metal 5.0 5.1 1.3 Minimum spacing 110 5.1 1.4 Minimum spacing from pad metal to
scribe lane 30 5.1 1.5 Minimum spacing from pad metal to
unrelated metal 20 5.1 1.6 Minimum spacing from pad metal to
diffusion and poly 15
S C R I B E LANE
I
METAL I
DIFFUSION
A - 4 The Extract and DRC program
(512K EPROM 11/88) { E x t r a c t command f i l e f o r 1.8 m i c r o n CMOS p r o c e s s ) {
11 /14 /88 YR change p2nga te n o t i n c l u d i n g p o l y l add badpga te check
1
< < f i l e s > > use epa l .w rk
< < l a y e r s > > p a c t i v e a c t i v e n a c t f ve d e p l e t i o n ~ 0 1 ~ 1 p o l YZ meta 1 PP 1 us nwel 1 c o n t a c t P f pad p f i e l d
{ i n t e r m e d t a t e LAYERS > P 4 nenh penh ndep n a t v n g a t e p 1 n g a t e p2nga te p 9 a t e psubcon t nwe 1 1 c o n t P sd nsd badpga te s u b s t r a t e c r e a t e g t n
< < h i e r a r c h y >> {
r e a d - c o v e r - f i l e 1
d r f t n e g t n c r e a t e g i n = b o u n d a r y andno t (boundary expand - 4 0 . 0 ) pfn-areampin-area o r c r e a t e g l n
analysis-name " e x t r a c t " keep-updated don t - r eana l yze f l a t - ce l l - name " * "
{ I gno re - subce l l " d r a m c e l l " f l a t - c e l l - s t z e 6 .0
donu t -s i ze 12.0 c o n s o l t d a t e edge-1 i m i t 300000
p r e f i x " M : " meta 1 p r e f i x "PZ:" ~ 0 1 ~ 2 p r e f t x "NA:" nsd p r e f i x "PA:" psd p r e f i x " P l : " ~ 0 1 ~ 1
p l n g a t e = ( p o l y l and a c t i v e ) andno t n w e l l p2ngate= ( ( p o l y Z andno t p o l y l and a c t i v e ) andno t n w e l l n a c t i v e = a c t i v e andnot p p l u s nga te=p loyZ and n a c t i v e ndep=ngate and d e p l e t i o n nenh=ngate andno t d e p l e t i o n n s d = n a c t i v e andnot n g a t e p a c t i v e = a c t i v e and p p l u s p g a t e = p o l y 2 and p a c t i v e p e n h r n w e l l and p g a t e p s d = p a c t i v e andno t p g a t e ( ndep= p2nga te and d e p l e t i o n nenh= p2nga te andnot ndep n a t v = p l n g a t e andnot d e p l e t i o n n s d l a c t i v e andno t ( p l n g a t e o r pZnga te )
p g a t e = ( a c t i v e and p o l y 2 ) and n w e l l penh= (pga te and n w e l l ) andno t p f p4 = ( p g a t e and n w e l l ) and p f p s d = a c t i v e andno t p g a t e > ~ s u b c o n t = ~ ( a c t f v e andno t n w e l l ) and c o n t a c t n w e l l c o n t = ~ n w e l l and a c t i v e ) and c o n t a c t
( t o u c h s u b s t r a t e ) t o u c h s u b s t r a t e psubcon t t o u c h n w e l l n w e l l c o n t t o u c h c o n t a c t me ta l p o l y l p o l y 2 psd nsd
t o u c h m e t a l psubcon t n w e l l c o n t
transistor NMOS NENH nenh nsd p o l y 2 s u b s t r a t e t r a n s i s t o r NMOS NDEP ndep nsd p o l y 2 s u b s t r a t e t r a n s i s t o r NMOS NATV n a t v nsd p o l y l s u b s t r a t e t r a n s i s t o r PMOS PENH penh psd p o l y 2 n w e l l t r a n s i s t o r PMOS P 4 p4 psd p o l y 2 n w e l l
< < checks > > < < end > >
< < f i l e s > > use eprom512.wrk
< < l a y e r s > > p a c t i v e n a c t i v e d e p l e t i o n ~ 0 1 ~ 1 p o l Y Z meta 1 nwel 1 c o n t a c t pad hv im mhv i m
i n t e r m e d i a t e LAYERS 1 pimp11 pimp12
P O ~ Y ~ 0 1 ~ s e r r o r - l a y e r spa ana a c t i v e h v a c t n o t h v a c t mhvact notmhvact 1 v a c t mhvnac dumact nwpp 1 us nwnp 1 us PWPP 1 us pwnp 1 us s b a c t 1 ve nwnsd nwpsd pwnsd pwpsd
ga te1 ga teb ga te2 hvga te g a t e depgate nwgate pwgate nga te p g a t e badngate badpga te l badpgate2
ncon t p c o n t p 1 c o n t p 2 c o n t meta 1 c o n t n o t p o l y c o n t n o t m e t a l c o n t n o t a c t c o n t p o l y c o n n e c t
< < hierarchy > > def i n e g i n ignore-multiple "VCC. ignore~rnultiple " V S S " ignore-multiple "VPP"
{nsd and psd in nwell and pwell a r e seperately deflned 1 poly=polyl or poly2 ana-nactive andnot (pactfve expand 1.4) apa-active and (pactive expand 1.4) nwnplus=ana and nwell nwpplus-apa and nwell nwgate=polyZ a n d (nwnplus or nwpplus) nwnsd=nwnplus andnot nwgate nwpsd=((nwell and active) and (pactive expand 1.4)) andnot nwgate
pwnplus=ana andnot nwnplus pwpplus=apa andnot nwpplus pwgate=poly2 and (pwnplus or pwpplus) pwnsd=pwnplus andnot pwgate pwpsd=pwpplus andnot pwgate
poly=polyl or poly2 notpolycont=contact andnot poly
polys=polyl and (poly2 expand 1.0)
touch contact metal nwnsd nwpsd touch contact metal pwnsd pwpsd
(
touch contact metal mhvact notmhvact touch contact metal hvact nothvact touch contact metal notactcont active
t o u c h contact meta 1 notpol ycont pol y touch polys polyl
edge-spacfng nwnsd nwpsd 2.8 error-layer different-node report-edge error-layer 'nwnplus t o nwpplus a t diff n o d e SPACING < 2.8. e d g p s p a c i n g pwnsd pwpsd 2.8 error-layer different-node report-edge error-layer 'pwnplus t o pwpplus a t diff node spacing <2.8' edge-spacing polys polys 5000.8 error-layer same-node report-edge error-layer '2 dlff poly2 touch t h e s a m e polyl - poly
( edge-spacing hvact nothvact 3.8 error-layer different-node report-edge error-layer 'hvacttve t o a11 actlve spacing a t dlff n o d e
edge-spacing mhvact notmhvact 3.8 error-layer different-node report-edge error-layer "mhvactive t o all active spacing a t diff n o d e
edge-spacing notactcont active 2.0 error-layer dffferent-node report-edge error-layer "contact t o active SPACING <2.0 different nodeg
edge-spacing notpolycont poly 2.0 error-layer different-node " report-edge error-layer "contact t o poly SPACING different node < 2.0"
flat-cell-size 6.0 flat-cell-name " y l g r g " flat-cell-name "xtprg flat-cell-name "rsprg"
ignore-subcell "epromarray"
(Operation for isolation^ active = pactive or nactive anarnactive andnot (pactive expand-octagon 1.4) sbactive = active fnclude poly hvact=hvim and active nothvact=active andnot hvim mhvact=mhvim and active notmhvact=active andnot mhvact lvact=active andnot hvact mhvnac=mhvim and nactive dumact=active andnot mhvnac gatel-polyl and pwnplus gateb=poly2 and active gatezrgateb andnot gate1 hvgate=gate2 and hvact gate=gatel or gate2 depgate=(poly2 and depletion) and ana badngate=ngate and nwell badpgatelxpgate andnot nwell badpgate2zpgate and depletlon ngate=poly and ana pgate=poly and apa
existence badngate "BADngate in nwelln existence badpgatel 'BADpgate outslde nwell" existence badpgate2 "BADpgate in depletionn
{contactact check? error-box-style width ncont 1.8 "nactive contact WIDTH < 1.8' {13.a) error-box-style width pcont 1.8 "pactive contact WIDTH < 1.8' {13.a) error-box-style width contact 1.8 "contact WIDTH < 1.8' <13.a) error-edge-style spacing contact contact 1.8 "contact to contact SPACING < 1.8' (13.b) error-box-style enclosure plcont polyl 1.0 'contact over polyl < 1.0' {13.e> error-box-style enclosure p2cont poly2 1.0 'contact over poly2 < 1.0' {13.e) error-box-style enclosure pcont apa 1.0 "contact overlaps with actual pactfve<lu ' error-box-style enclosure ncont ana 1.0 ignore-touchfng 'contact overlaps with actual error-edge-style spactng contact gate 2 . 0 *contact to gate SPACING < 2.9' {13.g> error-edge-style spacing notmetalcont metal 2.0 'contact to metal' SPACING < 2.0' C13.s)
{metal check) error-edge-style wldth metal 2.5 "metal WIDTH < 2.5" (l4.a) error-edge-style spacing metal metal 2.8 check-for-notch 'metal to metal SPACING < 2.8' C14.b) error-box-style enclosure metalcont metal 0.8 "contact over metal SPACING < 0.8' Zl4.c) < < end > >
A - 5 Spice parameters for simulation
Sk A h 1 P-{'HANkEL. . LIB FMODEL. EPH .MODEL P PMOS Fl=U. 14 kDEL.=U. 2 TOX-223 ES4T= 15. E4 MBL=O. 36 + LAMRL)A=3.7E-5 h b = I .U3 LDEL=-0.2 RD=470 RS=470 + VY=-U.65 C;..lMM4=U. 2 7 ' LIh-230 LATI)=O, 1 I.'DS=0.17 WIC=l MOE)=l + Ci,M=3 METO=U . 0 5 L D I F = , Z CF1-0.24 CF2=0.62 CF3=1 TR1)=2 .UE-3 + TRS=Z.OE-3 T C ' L = - 2 . i E - 3 REX=-1.3 + CJ.4=O.JE-I5 CJP=0.31E-15 EXAz0.5 EXPZ0.33 + ACM=Z PHl=0.6
STYPICAL DEP N-CHANNEL CELL .MODEL ND NMOS F1=0.02 WDEL=-0.14 TOX=250 ESAT=2.3E4 NBLo0.26 VT=-2 G A M W A = O . ~ ~ i LGAMMA=0.3 VBO=1.53 UB=560 LATDzO.1 FDSz1.37 LAMRDAz3.7E-6 + KU=l.l LDEL=O RD=360 RS=360 WIC=I MOB=l CLM=l HETO=O.l t LDIF=2 CF1=0.24 CF2=0.4 CF3s1.12 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCVs2.2E-3 t CJA=O.lE-15 CJP=0.33E-15 EXAr0.45 EXP=0.24 t ACM=2 PHI=0.36 . ENDL TNODEL. EPR
SSl,Ok P-CH4NNE1, . L i H SMOUt L. EPH .MODLI. P PMOS Fl =O. 18 !dI,EL=-0.2 7OX=275 E,dr\7'=12. E4 MBLzO. 44 t LAMBUA=J. IE-5 k U = 1 .01 LDEL=0.2 HD=570 RS=570 t VT=-1.05 GAMMA=0.33 UB=lYU LA'I'D=O.I FDS=U.13 WIC=1 MOB=1 t CLM=3 MFTO=0.15 LDIF=Z CFl=O.IH CF2~0.38 CF3~0.76 TRD=Z.OE-3 t TRSz2.OE-3 TCV=-2.7E-3 BEX=-1.3 t CJA=0.36E-15 cJP=0.49~-15 ExA~0.47 EXPz0.27 t ACH=2 PHI=0.8
SSLOW ENHANCEMENT N-CHANNEL .MODEL N NMOS F1=0.146 WDEL=-.2 TOX=275 ESAT=4.8E4 MBL=0.39 VT=0.9 GAMMA=0.55 t LGAMM4=0.13 VBO=l.l UH=590 LATDzO.1 FDSz0.76 LAMBDAz2.7E-5 t KU=1.01 LDEL=O.2 RD=400 RS=400 UIC=l MOB=l CLM=3 HETO=0.15 + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJAz0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=0.21 t ACM=2 PHI =O. 6
SS1,OU ENHANCEHENT N-CHANNEL FOR OFF CELL .MODEL ND NMOS F1~0.146 WDEL=-.2 TOXz275 ESAT=4.8E4 MB1,=0.39 VT=-2.0 t GAMMA=O. 55 t LGAl(nA=0.13 VBO=1.1 UB=590 LATD=O.~ FDS=0.76 LAMBDA=2.7E-5 + KU=1.01 LDEL=0.2 RD=400 RS=400 WIC=1 MOB=l CLM=3 METO=0.15 t LDIF=2 CFl=O.Q6 CF2~0.23 CF3~0.88 t TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJA=0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=O.21 + ACM=2 PHI=O.6
SSLOW PRO CELL .MODEL PRO NMOS P H I ' = o . ~ ~ VT=6.0 GAMMAsl.2 FDS=0.41 Flr0.037 ESAT=6.1E+4 + LAMBDA=l.EE-6 KLtO.1 F3r0.44 KA=1.33 MBLtO.46 WLx0.45 + KU11.5 LATDz0.18 CLH=3 UOB=l WIC=l LDEL=-0.21 WDELs0.58 + BETA=28.8E-6 RS=4OO RD=4OO LDIFr3 + TCV12.2E-3 BEXI-1.3 TRDt2.OE-3 TRSs2.OE-3
. ENDL SMODEL. EPR
APPENDIX B
B-1 The circuit simulation results and LVS results of a
input buffer circuit
****** h s p t c e 8807a 2:11:14 27-Jan89 u n 1 x ****** c o p y r i g h t 1988 m e t a - s o f t w a r e , l n c . * * * * * s l t e : e l i t e ***** r a b u f * * * * * * i n p u t l i s t i n g * * * * * * . o p t i o n p o s t aspec . w i d t h ou tm80
.model c j n d cja.0.1 cjp.0.33 e x r = 8 . 4 5 exp=#.24 p h t - d . 6 v c c 9 0 5 % ceb 7 $ a n t 1 0 S anb 8 % a n 6 v7 7 11 p u ( 5 0 Sns 2ns 2ns 80ns 90ns ) v l 0 10 11 p u ( 0 . 8 2.4 l 0 n s 2ns 2ns 20ns 4 0 n s ) vsub 5 0 0 v s s 11 0 0 . t r a n I n s 80ns . t e m p 25 . p l o t t r a n v ( 7 ) ~ ( 1 0 ) v ( 8 ) v ( 6 ) m l 1 0 11 11 5 nenh wr58.8 1-4 m2 3 2 11 5 nenh ~ ~ 3 . 0 l e 1 . 8 m3 4 3 11 5 nenh wa15 1 ~ 1 . 8 m4 6 4 11 5 nenh w.75 1=1.8 m5 9 2 3 9 penh w = l 0 1-1.8 m 6 8 3 11 5 nenh w.75 1.1.8 m 7 9 3 4 9 penh w=20 1-1.8 m8 9 4 6 9 penh w a l l 0 1-1.8 m9 9 3 8 9 penh w=140 1 ~ 1 . 8 m l 0 2 10 11 5 nenh w=100 113 m l l 2 7 11 5 nenh w-10 1-1.8 m12 12 1 0 2 9 penh w.25 113 m13 9 7 12 9 p e n h w=30 113 .end
SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:08:49 PST 1988).
8 - 3 The spice simulation and LVS result of a XTDEC
circuit
, - * * x i * * C o p ~ r . i C l t r 1 i r , . n i r l 4 - S o t t i ; a r ~ . I I I C . ' = * * * s 8 t * : r ~ ~ Le +i+++
x t j e C * * * * * * lnatlt I 1 s t lng q i c ~ a t l o n e x p i r e s Y U U H **a***
.opt l o n noqt R S D ~ C
.bJdT h 0\ l t=8( ) v c c Y (i 5 X L I J 1 1U $ x t n 11 S l t n b 1 6 S c l k i 14 S c l k 7 b 17 s a?)\ (1
S a l 2 x l Z S a i x 7 S Q d i s t b 1H S g h v b 1 5 v 1 0 1 0 0 1 2 v 8 8 0 5 v12 1 2 0 5 v 7 7 0 5 v l 8 1 8 0 5 - 1 5 1 5 0 0 v l 4 1 4 0 v u ( 0 7 . 5 l O n s 4011s l o o n s 2 0 n s 17011s) \ 1 7 1 7 O P U ( 7 . 5 0 l O n s l 0 O n s 4Ons 2017s 1 7 0 n s ) v s u b 3 0 0 v s s 1 3 0 0 . t r a n 5 n s 5OOns . temp 25 . p l o t t r a n v t l l ) v i 1 7 ) ~ ( 2 6 1 ~ 1 x 7 ) ~ 1 1 1 1 ~ 1 1 7 ) . p r i n t tran v 1 2 6 l v ( 2 7 1 v 1 2 ) ~ ( 1 1 ) m1 26 20 1 3 3 n e n h w=12 1 = 3 . 5 mZ 1 0 26 20 10 p e n h w = 5 . 8 1 = 3 . 5 md 1 0 20 2 6 l u p e n h w=6 1 = 3 . 5 m4 21 1 6 1 3 3 n e n h w=15 L=2.5 m5 1 1 1 1 21 3 n e n h w=15 1 ~ 2 . 5 16 22 9 11 3 n d e p w = 1 0 4 . 1 0 3 1 = 3 . 0 6 2 m i .i 15 22 3 n d e p w=120 1 - 3 . 5 mH 1 0 26 27 3 n e n h w=6 1=20 8 9 6 Y 20 3 n a t v w=30 1 = 3 mi0 27 27 2 3 n a t v w = 5 4 . 1 9 1 1 = 4 . 7 2 1 a l l 2 2 1 1 3 n a t v w=54 .194 1 = 4 . 7 2 1 m12 1 7 2 1 7 3 n a t v w=23 .2 1 = 4 3 . 3 0 6 0 1 3 14 27 1 4 3 n a t v w=23.2 1 = 4 3 . 3 0 6 m14 5 6 1 3 3 n e n h w=102 .311 1 = 1 . 8 0 5 ml5 1 6 4 1.3 3 n e n h w=100 .5 1 = 1 . 8 m16 9 6 5 9 p e n h w=259 .8 1 = 1 . 8 a 1 7 9 4 1 6 9 p e n h w=130 .2 1 = 1 . 8 a 1 8 6 4 1 3 3 n e n h w=40 1 = 1 . 8 m19 9 4 6 Y p e n h w=30 1 = 1 . 8 m20 2 3 1 8 1 3 3 n e n h w=40 1 = 1 . 8 m21 24 7 1 3 3 n e n h w = 2 5 . 1 l = l . 8 m22 4 1 9 2 3 3 n e n h v = 4 0 1 = 1 .8 m Z Y 2 5 1 2 24 3 npnh 1.=25.1 1 - 1 . x m24 1 9 8 2 5 3 n e n h v = Z 5 . l 1-1 . H
a 2 5 9 1 8 4 Y p e n h w-40 l = l . 8 m26 9 1 9 4 Y p e n h w=40 1-1 . H mZ7 9 7 1 9 9 p e n h w=10 1 = 1 . 8 m2H 9 1 2 1 9 9 p e n h w=10 1 ~ 1 . 8 m29 9 8 1 3 9 p e n h w=10 1 - 1 . 8 . e n d
O P E N I N G P L O T F I L E O N U N I T = 7
****** h s p i c e 8 8 U i a 9 : J t i : 6 3 1 - a u g 8 9 u n 1 x ****** coppriqht 1 9 8 8 meta-software,inc. *****slte:elite ***** xtdec ****** transient analysis tnom= 2 5 . 0 0 0 temp= 2 5 . 0 0 0 ******
9 . 8 2 2 -e------t------+------2------a-d---c+-------+------+------ t - 9 . 8 2 2 e t t 2 a d c + + t + 9 . 8 2 2 e t t 2 a d c + + t + 9.777 t e + t 2 t at d c+ + + t 9.894 t e t t 2 t a d c + t t t
1 0 . 0 8 7 t t e + 2 t a dc+ + + t
1 0 . 2 9 6 t t e t 2 t t t +a 2t + 1 0 . 5 1 7 t t et 2 t + a cd t + t
1 0 . 7 6 6 t t t2e t t a ctd + t t
1 1 . 0 2 t i t t 2 e t t a ctd t + t 1 1 . 2 8 8 -+------+-----Z+------e------+--- a - c + - d - - - - + - - - - - - + - - - - - - t - 11 , 2 6 0 t t 2 t e + a ctd t t t 1 1 . 1 5 4 t t 2 + e t a ctd t + t
1 1 . 0 3 2 t + Z t e t a cd t + t 1 0 . 9 1 2 + + Z t e t a c d + + t
10.7ti6 t 2 t e t + a dct t t t
1 0 . 6 4 1 t 2 + t e t t a t i c + t t t 10.528 + 2 t t e t +a d C + t + t
1 0 . 4 1 5 t 2 t t e + tad ct t t + 1O.:i04 t Z t t e t + Z c + t t + 1 0 . 1 9 3 - + - 2 - - - - + - - - - - - + p - - - - - + - - - - - - - - - - c + - - - - c + - - - - - - + - - - - - - t - - - - - - + - 1 0 . U 8 4 +'L + e t d a c l t t t
9 7 2 t e + t d a c t t t t
9 . 9 7 1 2 t e t + d a c + t t + 9.368 2 t e t + ti a c t t t t 9.967 2 + e t * d a c + t t t
9.966 2 te t + d a c + t t i
1C1.247 t 2 e t + d +a c + t t t 10.540 + 2et + d a ct t t t
1 0 . 9 3 2 + e + 2 t l d + a c + t t t I \ .SH9 -+---p--+--~---+------t~-----+---a-c+------+------t------+- 1 2 . 3 2 2 t e t 2 + td t c R t + t
1 3 . I Y . i t e + t 2 t -1 t c + a t t t I . ) . f l T Z + e t + 2 + d t C+ R t t t
I I J l l 4 o t + 3 + + ,- +
t e + + 2+ d t r t t a + + P + + Y + +d c + + a + + +e + 2 + + d c+ + a + + 2 + + 2 + + a + + + e+ 2 + + c +d t a + .I
****** h s P i c e 8807a 9:46: 6 3 1 - a u q 8 9 u n i x ****** copvrieht 1988 meta-software,inc. *****site:elite *+*** xtdec ****** transient analysis tnom= 25 .000 temp= 2 5 . 0 0 0 ******
11 .3267 I Z ' . 22UJ 13 .1132 14 . O O O f i 14 .8877 15.7735 15 .7726 15 .7729 15.4296 I5.0Uh.l 14 .7390 14.3914 14 .0444 1 .i . tr913 1.4. 4560 , : I ( i I
t t t t + 12.000 -c - - - - - -+-e- - - -2 - - - - - -+- - - - - - - - - -a+- - - - -a t - - - - - - t - - - - - - t - - - - - - t - 12 .000 c + e 2 t t at t t t
1 2 . 0 0 0 d + e 2 t t at t t t
12.000 c t e 2 t t at t t + 12.000 d + e 2 t t a t t t t
12.000 c t 3 t t a t t t t
12 .000 c + $ t + a l + t t
12.0UO d t 2e t t at t t t
1 2 . 0 0 0 c + 2e t + at t t t
1 2 . 0 0 0 d t 2 e t t at t t t 12.000 -c------+------2-e----t------
12.000 c + 2 e t t at + t t
12.000 d t 2 e + t at t t t
12 .000 c t 2 e t t at t + t
1 2 . 0 0 0 d + 2 e t t a t t t t
12 .000 c t 2 e t t at t t t
12.000 c t 2 e t + at t t t
12.000 d t 2 t e t at t t t
12 .000 c t 2 e t at t t t
12 .000 d + 2 + e t at t + t 1 2 , 0 0 0 -c------+------2------te-----+-----at------t------+------t- 12 .000 c t 2 t e t at t t t
12.000 d t 2 t e t at t t t
12.000 c t 2 + e t at t t + 12.000 d t 2 t e t a t t t t
12 .000 c t 2 t e t at t t + 12.000 c t 2 t e t a t t t t
12 .000 d t 2 t e t at t t t
12.000 c t 2 t e t at t t + 12.OOU d t 2 t e t a t t t t 12.000 -c- - - - - -+- - - - - -2- - - - - -+- - - - . - -e- t - - - - -at - - - - - - t - - - - - - t - - - - - - t - 12.000 c t 2 + e t a + t t + 12.000 d t 2 t e t at t t t
12 .000 c + 2 t e t at t t + 12.000 d t 2 t e at t t t
12 .000 c + 2 t e t a + t t t
12 .000 c t 2 t e t at t t t
12.0U0 d t 2 t e a + + t t
12.0iJ0 c t 2 t e a t t t t
12.000 d t 2 t t e a+ t t t 12.000 -c- - - - - -+- - - - - -2- - - - - -+- - - - - - - - - -a+-- - - -at - - - - - - t - - - - - - t - - - - - - t -
12.000 c t 2 t e at t t t
12 .000 d t 2 t t e a + t + t 12.Uo0 c t 2 t t e R t t t t
12.UU0 d t 2 t t e at t t t
1 2 . O O U c t 2 t t e at t t + 12 .000 c t Z t te at + + t
12.000 rl t 2 t t e at t t t 1 Z . 000 r t 2 + te 8 t t t t I ' . . " I < 1 + + + C A + +
P a t P a+ e a t
e a t e a+ e a+
ea+ ea+ ea+
***** lob concluded vp1 sws ****** l o b statistics strmmarv ******
S C A L D s y s t e m C O M P A R E Ver 9.2 SUNS-P1 (Tue Mar 15 01:08:49 PST 1988).
oebt -matching---> oebt VP f -matching---> v p f wafer substrate -matchfng---> wafersubstrate v s s -matching---> v s s nmos+45.50/4.00#natv -matching---> nmos#45.00/4.88+natv nmos#lB05.H0/3.00+nenh -matching---> nmos#l00H.B0/3.H8#nenh nmos#300.0B/3.B8#nenh -i3atchlng---> nmos#300.H8/3.0H~nenh
Tho C l r c u l t s Match.
B-5 The spice simulation and LVS result of a CLOCK
circuit
l ' t111 A I I ~ : ( I 2 2 : : j X : 18 P[)T 1 9 x 9 tar*** c < ~ ~ ~ v l . i g l ~ t 1 9 8 8 m r t i l - s o t t c i i r . ~ , ~ r l r . . * * * * * + I ! , . : , , I ~ t < -
<- I I< **a***
. ovt I on a s p r c ~~ost, d c o n : l r l \ = l O ( l 0 \ . r c 2 2 O 5 v 2 . i 2:1 0 I " v
21, 2 ( i ( 1 Ov
v.3 I .i 1 (1 l>Ll1 s e i u 5 l O u c l l l s 211s 211s I ~ ~ 0 1 1 ~ ~ I I ~ I l l l l ~ I v 3 u :3u 0 5\, $ \ P I 2.4 $ ~ l h v Z t i
$ a l h v p q m b 3 1 s s t h :ro $ c l k 7 2 7 fi c l k 7 t > 2 Y % c l k 5 2 5 $ c l k 5 h 2 8 vsub 5 U O v s s 2 4 U 0 . t r a n 5ns 1 O O O n s u l c . i c v 1 3 t i l = 5 v v l 1 3 ) = U v ( 9 ) = 5 v v l l t i ) = O \ I I $ l = 5 v v l l X . ) = O r - v l 1 l ) = 5 v 1 4 1 = 0 + v l X I = 5 v v ( 7 ) = O v l 2 5 ) = 1 v ( 2 ) = 5 \ . v ( 3 ) = 0 v ( 1 2 ) = 5 v ( l O l = 5 v v l 1 9 I=O v ( 2 0 ) = 5 + v l 2 1 l = O v ( 1 5 l = O v1 1 4 l = 5 v l 3 7 ) = 5 v ( . iH ) = 5 . p l o t 1 r . a 1 1 \ I 2 7 1 \ * I 2 9 1 ~ ( 2 5 1 v l Z X ) v l . i i I \ . I . < H I \ . ( : { I . t t,nll' 2 5 n ~ l .I7 1 9 1 0 ;17 p e n 1 1 w = 5 1=3. .5 in2 Z J 3 8 :it; :I r r a t v w = t i 1 = 4 m J 3 7 2 2 2 2 5 n a t v w = 1 5 1 - 3 . 5 nl l 1 2 2 2 111 5 r l n t \ w = . l O l =:1 1115 1 1 I x 2 I :> r l t ? l l l l w = 5 1 = 5 1111, 2 6 Z 2.4 5 I~e l \ l h w r 4 O 1 - 1 . H m i 1'2 .i 2 1 5 l l rnlt w = l O l = I . H lllX ') 4 2.) .-> ~ I ~ I I I I * = I 0 I = 1 . X m 9 l i 2 4 .i r 1 r t 1 1 1 w = 6 l = l . P 1 n 1 0 2 2 1 8 1 1 2 2 u e r r l r w - l l r I=:, m i l 25 T 2.4 5 r r e r l l ~ v = . S U I = l . 8 11112 2 2 2 :H 2 2 ) ) t>r111 h = j I l I = I .P. r n l .{ 7 X 2 I 5 ~ ~ r r ~ l i w = 1 5 1 = 1 .8 n 1 l 4 2 2 :i I 2 2 2 rent1 u=25 1 z I . H m 1 5 2 2 4 '4 2 2 ~ w r ~ t ) w = 1 0 1 = 1 .8 1 1 1 l l i H 1 2 1 .i 1 1 # . 1 i l 1 W - 2 0 ( = I . X m l i 2 2 li 1 3 2 2 p e t l l ~ w = t i l = l . t ( m l 8 I b 9 2 4 5 n ~ r ~ h w = 3 1 = 5 m l 9 2 2 7 2 5 2 2 pent1 w = 5 0 I = I . H n l2O 4 9 2 - 1 5 nptlh id='lU I = I . X m 2 I 1 i l t j 2 4 5 11e11t l w = 5 1 = 5 m 2 2 2 2 X 7 2 2 prnh w = 1 5 1 - 1 .8 m2:{ 1 H 1 7 2.1 5 1rf.11t1 w=!> 115 1n2sI 2 2 '1 H 2 2 1wr111 w = X O I = 1 .H m 2 3 2 2 Y lti 2 2 p e n h w = 1 0 1 = 5 m Z 0 2 2 9 .I 2 2 r ~ e r r h w = Z O 111 . H m 2 i 2 2 I f i 1 7 2 2 penh w = l U 1 - 5 i n 2 8 2 2 1 7 I H 2 2 r w n h w = l O 11% rnZY 19 I I J 2 I .-b ~ l ~ r l l , v = I l l I = . j . . I
TI,'{II 'Jl l I ' 1 I 4 r a ~ ~ ~ l ~ \. = J 6 I = ' I . :,
128.443. + + 3 + 3 f + + + + 127.64Ym + + 3 + 3 f + + + + 1 2 7 . 9 0 0 ~ + + .3 + 3 f + + + + 1 1 1 . 3 3 0 ~ + + 3 + Z c f + + + +
3 . 0 7 5 + + 2 + a e b c f + + + + 5 .272 + + 2 b + c a e + f + + + 6 . 7 7 8 + + 3 + c a e + f + + + 7 . 6 7 0 + + 3 + c a e f + + + 8 .112 -+------+------3------+------c------- -+-2----f--- - - -+------+ 8 . 3 1 6 + + 3 + c + 2 f + + 8 . 4 1 6 + + 3 + c + 2 1 + + 8 . 4 7 1 + + 3 + c + 2 f + + 8 . 1 9 8 + t 3 + d + 2 f + + 7 . 7 2 0 + + 2 + d b e a f + + + I . 3 0 9 + + 2 a + d 2 + f + + +
106.557m + + 2 a + 3 f + + + + l d l Y' /c;m + A 1 -, .-
8.046 t t 3 t c t 2 ft + + 8.287 t t .i + c t 2 t' +. t 8.404 t t 3 t c + ' L f t ' t 8.462 -+------+------J------+------c------+--2---f------t------t- 8.273 + t 3 t d t 2 f t + 7.377 + t 2 t db e a f + t t
2.811 t t 2 + a d b e t f t t t
207.382~ t t 'La t 3 f t t + t
142.311m t t 3 t 3 f t t t t
129.969. l t 3 t 3 f t t t t
128.785~ t t 3 t 3 f t t t t
128.862~ t t J t 3 f + t t t
119.217. t t 3 t 2c f + t t t 791.538D-+------t------22R----t---222CCf----+------+------+------+-
5.279 t t 2 t bcae tf + t t
6.327 + t 3 t c a e t f + t t
7.448 t t 3 + c 2 f t + t
8.004 + t 3 - + c tae f + t t 8.265 t t 3 + c t 2 f t t
8.394 t t 3 t c t 2 f t t
8.455 t t 3 + c t 2 f t t
8.415 + t 3 t d t ea f t t 7.401 t t 2 b t d ea f + + t 4.834 -+------t------2------+---------bs+----bet----f-t------t------t-
247.059. t t 2a t 3 f t t t + 151.018~ t t 3 t J f + t t t
13U. 072m t t 3 t 3 f + t t t
128.853~ t t 3 t 3 f + t t t
129.517r t t 3 t 3 f l t t t
128.333r t + 3 t 3 f t t t t
241.120m + t 2 a t 2 c f + t t t
5.057 t t 2 t 3 e f + t t
6.065 t t 3 t c a e t f + t t 7.330 - + - - - - - - + - - - - - - 3 - - - - - - + - - - - - - - - c - - - - - - ~ - - - - f - + - - - - - - + - - - - - - + - 7.943 t t 3 t C t2 ft t t
8.236 t t 3 + c t 2 f t t
8.379 t t 3 t c t ae f t t
8.447 t t 3 t c t 2 f + t
8.486 + t 2 d t c t 2 f t t
7.590 t t 3 t d 2 ft t t
6.346 t t 2 t d a 2 ft t t
298.321. t + 2 a + d2 F t t t t
155.706m t + 3 t 3 f t t + t )30.790m-+------+------3------+------3-f----+------+------+------+- 129.351~ l t 3 t 3 f l t t t
129.786. t t 3 t 3 f t t t t
129.948m t t 3 t d2 f + t t + llY.6RBm t t 3 t 2 c f l t t t
4 . r i 1 3 t t 2 t a2e f t t t
5.708 + + 2 b t c a e t f + t t
7.141 + t 3 t c a r f t t + 7.854 .t t 3 + r t 2 Yt t t
U.lk4 t t 3 t r t 2 t 4 + 8.35f, - + - - - - - - t - - - - - - ~ - - - - - - + - - - - - - , . - - - - - - + - a e - - f - - - - - - + - - - - - - + -
SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:88:49 PST 1988).