ChristophWolf-PracticalAspectsTesting

IHPIm Technologiepark 2515236 Frankfurt (Oder)

Germany

IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com 2007 - All rights reserved

Practical Aspects of TestingBased on Experiences with Verigy 93000 SOC

Wolf, Christoph


Outline

Introduction

Tester architecture concepts

Test pattern generation/conversion

Event-based test system

Memory test

Limitations of standard test systems


Usage Scenarios

StandaloneManual test of packaged devices

Docked to a handlerAutomatic test of packaged devices


Usage Scenarios

Docked to a wafer proberAutomatic test of unpackaged devices directly on a wafer


Typical Tester Architecture

Basic infrastructureManipulatorTest system power supplyClock- and control boardsCooling

Air or liquid

(Test) Application specific equipmentDevice power supply

General purpose, high voltage, high current, low noise, multi-channel

Digital channels

Analog & RF-resourcesWaveform generators, digitizers, TIAs

Utility lines (external circuitry, relay control, etc.)


Tester Architecture

Central control Central resources (control, memory etc) distributed to channelsAdvantage:

Simpler system architecture, lower complexity

Tester-per-pin-architecture

Mostly used in modern high performance testers

(Nearly) all resources available separately for each channel

Advantage:

Higher throughput possible (e.g. no memory bottleneck)

Increased flexibility (multi-port and/or multi-site capabilities)


Test Program Implementation Styles

Different implementation schemes varying among vendors and tester familiesStandard programming languages (C,)Specialized script-like high level languagesGUI-based approaches (graphical programming by joining basic building blocks)

Example Agilent/Verigy 93000 SOCTestvsystem based on extensive set of firmware commandsSeveral editors (both pure text editors and custom windows)Majority of data stored as text files, partly embedded firmware commandsVectors stored in binary formatBuilt-in test functionsAPI for customer specific tasks in C++


Test Program Entities

Typical set of common basic entities

Pin configuration: map logical pin/signal names to physical tester resources

Level configuration: voltages to apply to the chip and compare against

Timing configuration: define when signal events should occur

Vector configuration: actual data to be applied to the chip

Tests: continuity test, functional test, memory test, static/dynamic current,

Testflow: sequence of tests

External interfaces: prober/handler control, data logging


Pin Electronics General Principle

Driver(Input)

Receiver(Output)

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

0

GND

0

ZL=50O

DUT

Vt

Vih

Vil

Voh

Vol

Iol

Ioh

Clamps

PPMU

Active Load

50O

50O


Pin Electronics Driver ModeDriver(Input)

Receiver(Output)

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

0

GND

0

ZL=50O

DUT

Vt

Vih

Vil

Voh

Vol

Iol

Ioh

Clamps

PPMU

Active Load

50O

50O

Tristate-Ctrl

FormattedData


Pin Electronics Receiver ModeDriver(Input)

Receiver(Output)

a11

a22

3a3

4a4

b1

b2

b3

b4

5

6

7

8

Vcc1

0

GND

0

ZL=50O

DUT

Vt

Vih

Vil

Voh

Vol

Iol

Ioh

Clamps

PPMU

Active Load

50O

50O

Tristate-Ctrl

FormattedData

Vt

> Voh< Vol


Waveform Generation

ATE systems typically strictly cycle-basedNo instantaneous change of cycle period during pattern execution

Fixed format based approachFixed set of available waveforms

(D)NRZ (delayed non-return to zero)RZ, RO (return to zero/one)SBC (surrounded by complement)STB (edge strobe)WSTB (window strobe)

Timing setup defines edge positionsVector setup defines data (logical 0/1)Waveform type can be per pin or per cycle

0 1


Waveform Generation

Flexible waveform setup (93k style)Wavetable defines (up to 256) different waveform shapes

Combination of max 8 drive and 8 receive edgesPure shape definition, only edge actions (drive 0/1/Z, strobe L/H/X), no timing

Equations define edge positions in time, no shape/action information

Specset joins one wavetable and one equation set, optional spec vars

Vectors do not contain logical values but indices into wavetable

Test references a spec set (defines timing+wavetable) + vector setFlexible combinations of vector, timing and waveform shape sets possibleExample:

Basic functional test with NRZ waveformsCharacterization tests (setup/hold time) with SBC waveforms


Setup Example

Wavetable Equations Vector0 d1:0 period=45 01 d1:1 d1=0 22 d4:1 d6:0 d2=5 33 d2:1 d3:0 d4:1 d5:0 d3=10 14 d2:Z r1:H r2:L d4=20 45 d2:Z r1:L r2:L d5=25

d6=40r1=30r2=40

0 45 90 135 180 225

0 2 3 1 4

H L


X-Modes

Complex wavetables enable vector compression (or higher data rate)Several (device) cycles encoded into one tester cycleLimited by number of distinct edges and wavetable count

Examples (Verigy 93000, 8 driving + 8 receiving edges, 256 waveforms)Data input NRZ (1 edge, 0/1) 8 edges, 2^8 = 256 states x8Clock signal RZ (2 edges, 0/1) 2x4 edges, 2^4 states max x4Bidir pin NRZ/STB (0,1,L,H) 4 edges, 4^4=256 states max x4Bidir pin NRZ/STB (0,1,L,H,X) 4 edges, 5^4 > 256 states max x3


High(er) Speed Testing Issues

Signal reflections in unmatched environments

Driver can be used to supply 50 termination in receiver modeThird level termination or active load for bidirectional pins

Device must be able to drive into 50

For CMOS devices usually not fulfilled impedance matching resistors required on the load board

Termination acts as voltage divider only reduced levels seen by tester


High(er) Speed Testing Issues

Fixture delay calibrationConsiderable signal propagation times from tester electronics to DUTTester calibrated up to fixed interface, additional delays on DUT boardTDR measurement to determine additional propagation timeInput signals are applied earlier, output signals are evaluated later

Works fine for unidirectional pins, problems with bi-directional pinsSolution: separate tester channels for input and output path

t-td 0 +td -td 0 +td

Input

Output

Tester-Side DUT-Side


Test Pattern Generation/Conversion

Several test program elements can be generated by hand Test vectors usually require automatic handling

Example Verigy 93000Direct creation of binary vector files by appropriate toolsImport of already cyclized text format data via ascii interface

Device cycle file: list of state characters and corresponding waveformsPins clockDVC df0 0:0ns1 1:0nsP 1:10ns 0:20ns

ASCII vector file: one vector per row, one state character per pinEach line holds data of one tester cycle



Two major sources of test patterns

Structural test patterns generated by ATPG toolsDesign data required, tests for specific faultsMostly used in combination with scan chains to reduce complexityUsually used for production test to verify defect-free fabricationHigher effort to catch timing-related issuesUsually generated already in cycle based format (WGL, STIL)

Functional test patternsBlackbox testing Knowledge about internal structure not necessarily requiredOften used for design verificationMostly generated by simulation



Functional tests at IHP No product development and no mass productionHigh rate of new designs in prototype stateTransition to structural tests but functional test still dominant

Functional test patterns obtained by logging simulation runsProblem: simulation is event-based, usually (e)vcd file format for exportEvents can occur at arbitrary positions (E)VCD: (extended) value change dump format

(E)VCD state charactersVCD: 0/1/X/Z

Additional direction control signals for bi-directional pins required

EVCD: D/U/N/Z/d/u; L/H/X/T/l/h; extra state characters for collisionsSignal direction encoded into state characters, no need for separate direction control signals

Strength encoding: 0-6, separately for low and high value



(E)VCD file format

header (version info, timescale)signal declaration list (including hierarchy)initialization dumptime stampevent listtime stampevent list

...


Test Pattern Generation/Conversion EVCD example$var port 1



Required processing: cyclizationEvent file partitioned into cycles of equal lengthOptional signal conditioning (scaling, shifting events, ...)Potentially long periods of inactivity event based format does not contain data; cycle based format requires data for each cycle

Two methods for waveform mapping:Signal sampling at specified positions, acquired value is taken as argument for the parameterized tester waveform

Advantage: relatively simple process

Disadvantages: Only one value acquiredMultiple signal changes in a single cycle ignored/not detectedCareful selection of sample point required if signal changes

occur at different positions with respect to the cycle



Matching with predefined match waveforms, selection of corresponding target waveform

Disadvantage: computing intensive

Advantages:

More complex waveforms can be reproduced

Implicit cross check of simulation against a set of predefined waveforms

General problem:Arbitrary event based waveform must be reduced to cycle based representation with strictly limited number of signal changes (i.e. timing edges)


Event-Based Test System

Advantest CertiMAX

Inherently event based: test data stored as events(Action, time offset from previous event)

System can directly read evcd files, no cyclization

Each channel can run completely independently from each other

Single events can be repositioned

Minimum time 8ns between events

Limited speed but very suitable for functional debugging


Memory test

Several different algorithmsSolid, Checkerboard, March, ...

Differentiation between device address, physical address and topological addressDevice address: externally applied addressPhysical address: internal address (x,y,d)Topological address: internal addres (x,y)

ScramblingRelation between device & physical addressMemory test algorithms deal with cell neighborship calculate device address such that physical addresses match algorithm

Bitmap centric view rather than cycle based viewMapping between physical and topological addresses


Memory Test Scrambling Example

Scrambling: equations to calculate external addresses based on internal physical addresses such that x increases to the right and y increases to the bottomxor used as conditional inversion (mirror base address depending on block address)

ya[7:0] = y[7..0] XOR y[8] xa[6:0] = x[6..0] XOR NOTx[7]ya[8] = y[8] xa[7] = x[7]

A[16:15]=00 01

10 11

0

255

0

255

00127 127

A[7..0]

A[7..0]

A[14..8] A[14..8]0,0

Address range split into row (y) and column (x) addressesya[8..0] = A[16] A[7..0]xa[7..0] = A[15] A[14..8](A[16:15] block address, prependedto x and y base addresses)

ya/xa: externally applied device addr.

y/x: internal physical addr.


Memory Test Algorithmic Pattern Generation (APG)

Memory tests can have high complexity (>6N)

Huge amount of vectors for large memories

AGPs compute vectors on the fly rather than storing them

Make use of high regularity of memory tests Loop and repeat constructs, memory test algorithms implemented as sequencer programs

Example: solid test (write complete memory, read complete memory, n words)

LSB: 01010101... rep (2 * rep (n/2) * 01) 00110011... rep (2 * rep (n/4) * 0011)

MSB: 0000...1111 rep (2 * (rep (n/2)*0, rep (n/2)*1))


Limitations of Standard Test Systems

Speed, vector memory

Number of distinct timing edges

Number of independent clock domainsDespite tester-per-pin architecture usually common master clock, no truly asynchronous signals possible

Very limited degree of flexibility on pattern levelMatch loop: loop around until chip output matches the loop vector (i.e. for flash testing or PLL locking)

No further (conditional) processing on vector level

Severe problems with respect to asynchronous circuits

Practical Aspects of TestingBased on Experiences with Verigy 93000 SOCOutlineUsage ScenariosUsage ScenariosTypical Tester ArchitectureTester ArchitectureTest Program Implementation StylesTest Program EntitiesPin Electronics General PrinciplePin Electronics Driver ModePin Electronics Receiver ModeWaveform GenerationWaveform GenerationSetup ExampleX-ModesHigh(er) Speed Testing IssuesHigh(er) Speed Testing IssuesTest Pattern Generation/ConversionTest Pattern Generation/ConversionTest Pattern Generation/ConversionTest Pattern Generation/ConversionTest Pattern Generation/Conversion EVCD exampleTest Pattern Generation/ConversionTest Pattern Generation/ConversionEvent-Based Test SystemMemory testMemory Test Scrambling ExampleMemory Test Algorithmic Pattern Generation (APG)Limitations of Standard Test Systems

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