1 An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations Chris H. Kim, Kaushik Roy, Steven K. Hsu*, Ram K. Krishnamurthy*, Shekhar Borkar* Purdue University, West Lafayette, IN *Circuit Research, Intel Labs, Intel Corporation, Hillsboro, OR Intel Labs
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1
An On-Die CMOS Leakage Current Sensor for Measuring
Process Variation in Sub-90nm Generations
Chris H. Kim, Kaushik Roy, Steven K. Hsu*, Ram K. Krishnamurthy*, Shekhar Borkar*
Purdue University, West Lafayette, IN*Circuit Research, Intel Labs,
Intel Corporation, Hillsboro, ORIntel Labs
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Outline
Motivation and prior art
Proposed leakage sensing technique
Leakage sensor test chip implementation
in 90nm
Leakage binning results
Conclusions
3
Process Variation
0.4
0.6
0.8
1.0
1.2
1.4
0.01 0.1 1 10 100Normalized IOFF
Nor
mal
ized
I ON
NMOSPMOS
100X
2X
150nm CMOS, 110°C
IOFF spread > 100X, ION spread > 2XDevice parameters are NOT deterministic any more
4
Off-current meas.Off-current meas.
Process Variation Detection
Sub-threshold CMOS device:
T. Kuroda, JSSC, Nov. 1996
Test row devicesProcess monitor
Decay sensors
Strong inversion CMOS device:
M. Griffin, JSSC, Nov. 1998Y. Kim, IEICE, Nov. 1999
Delay line:M. Miyazaki, ISLPED, Aug. 1998
On-current meas.On-current meas.
Process detection method optimized for each applicationResolution, area, complexity, testing cost, etc.
5
Leakage Variations Impact
Dynamic circuit NMOS pull-down leakage variation:Keeper size determined for target robustness at worst-case leakage cornerExcess leakage dies: fail to meet target robustnessLower leakage dies: over-designed for robustness
Dynamic 8-way Bitline
0.7
1
1.3
1.6
0.25 1 1.75
Nor
mal
ized
Del
ay
Keeper upsizin
g 20%
5%
10%
DC noise robustness
8%
Target robustness
clk
...RS0
D0
RS1
D1
RS7
D7
Dyn_out
WKPR
R. Krishnamurthy et al, VLSI Circuits Symp. 2001
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Target Application: Process Compensating Dynamic Circuit
3-bit programmable conditional keeper
clk
. . .RS0 RS7
D0 D7
RS1
D1
LBL0
LBL1
N0
b[2:0]
W 2W 4Ws s s
On-die leakage current sensor required to generate b[2:0] based on NMOS pull-down leakage
Conventional
C. Kim, S. Hsu et al, VLSI Circuits Symp. 2003
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Usage Model and Design Goal for On-Die Leakage Sensor
83μm
73μ
m
current reference
comparators
current m
irrors
VBIASgen.
NMOS device
test interface
High leakage sensing gain (> 3b resolution)No complicated timing controlCompact analog design
On-Die Leakage Sensors
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Previous Leakage Current Sensing Circuits
Susceptible to P/N skew and supply fluctuationLarge area due to multiple analog bias circuitsLimited leakage sensing gain
+- d0
IREFd0VBIAS
+-
VSEN
VDD/2
VSEN
T. Kuroda et al., JSSC, Nov. 1996 M. Griffin et al., JSSC, Nov. 1998
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Proposed Single Channel Leakage Sensing Circuit
Basic principle: Drain induced barrier loweringLow sensitivity to P/N skew and supply fluctuation
IREF
M1 (saturation)
M2 (subthreshold)
+-
VBIAS+- d0
VREF
VSEN
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PV Insensitive Current Reference (IREF)
• Sub-1V process, voltage compensated MOS current generation concept
ConclusionsPost silicon tuning is becoming promising for process compensationOn-die leakage current sensors assist inter/intra-die process compensationMulti-channel leakage current sensor– No complicated timing control– 1.9-10.2X higher sensitivity to leakage– Shared analog components for compact