Chip Chip - - Package Package CoDesign CoDesign - - Challenges and Directions Challenges and Directions Paul Franzon Toby Schaffer, Alan Glaser, Andy Stanaski, Yusuf Tekmen, Mouna Nakkar North Carolina State University [email protected]www.ece.ncsu.edu/erl Funding:
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Chip-Package CoDesign · PDF fileGlobal Clock Distribution ... IBIS Models. Franzon 32 Packaging CAD Status ... High Density Packaging Trends Chip-Package Codesign Trends
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ChipChip--Package Package CoDesignCoDesign-- Challenges and DirectionsChallenges and Directions
Paul FranzonToby Schaffer, Alan Glaser, Andy Stanaski, Yusuf
Tekmen, Mouna NakkarNorth Carolina State University
environmentCore noise contribution significantGreater on-chip exposure to SSNIntend to produce suitable macromodels
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Alpine SystemsAlpine Systems> Achieving greatly decreased footprint with
careful codesign across multiple levels of interconnect
2,000 I/O pins in a 256-pin BGA
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Embedded PassivesEmbedded Passives> Frye, Lucent, Bell Labs
Passives
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OutlineOutline
High Density Packaging Trends
Chip-Package Codesign Trends
CAD Tools for Codesign
Codesign CAD at NCSU
•Current Status•Future Needs
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Packaging CAD StatusPackaging CAD Status> IC and package tools very separated:IC Physical Design Package Physical Design
Package Modeling/SimulationOn IC Modeling/Simulation
I/O LocationsIBIS Models
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Packaging CAD StatusPackaging CAD Status> Current points of integration concentrate on
single net SI and routability, mainly at the board level
e.g. Xinetix EDA Navigator or Cadence SpectraQuest
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> On-chip noise issues becoming criticalRequires co-modeling of chip and package
> Routing Resources becoming very tightFlip-chip breakout can be difficultOn-chip interconnect dominating on-chip delaysMiniaturization in RF systems leads to very constrained board designs
> Must seek codesign opportunitiesDigital - optimal interconnect allocationAnalog - embedded passivesMust include process variations of chip and package
Future Design IssuesFuture Design Issues
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Breakout IssuesBreakout Issues> To breakout a large number of pads with a river
route requires intensive routing resources:
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Possible Future FlowPossible Future FlowIC Physical Design•Floorplanner•Net planner
Place on-IC blocks and I/O to ◊ minimize longest delay◊ ensure routability
> ApproachSimulated annealing placementWeighted Trunk Tree length estimatorDelay mean and standard deviation used in objective function Routing Resource Metric used in objective function
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Yusuf Tekmen, Real Pommerleau, Paul Franzon, Grif Bilbro
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Weighted Trunk Tree LengthWeighted Trunk Tree LengthResults lengths within 1% of Cadence silicon ensemble actual lengths. (Other methods typically 5% accurate.)
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Yusuf Tekmen, Real Pommerleau, Paul Franzon, Grif Bilbro
Yusuf Tekmen, Real Pommerleau, Paul Franzon, Grif Bilbro
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ResultsResults> Placed and routed ten experiments (routing
using Cadence Silicon Ensemble)Designs 1.3x faster on average than with conventional methodsFaster convergence on correct design - One iteration in each case
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Proposed Method
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ConclusionsConclusions> The relationship between electronic packaging
design and IC design is becoming strong:Package adding value to ICPackage noise affecting IC designHigh pin count systems
> New design approaches and tools are neededCodesign across disciplinesIntegrated tool flows to solve important problems
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PerformancePerformance--drive IC placementdrive IC placement
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Impact:
Sample Designs are 1.3x faster
No timing violations after first iteration between placement and detailed routing
New Ideas:Estimators
Weighted Trunk Tree (WTT)
Pre-characterized Delay Models
Routing Resource Metric (RRM)
Dynamic Path-Delay Minimization
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High Density Packaging TrendsHigh Density Packaging Trends> Short Term
Increased penetration of Direct Chip Attach (DCA) (solder balls) and Chip-On-Board (COB)
◊ Increased scope for package-induced SSN noise impacting on-chip design and functionality
◊ Layout difficulties in high pin count systems
High speed interfaces require careful codesign of chip and package
◊ 400 MHz buses becoming common
> Long TermPackage technology adding value to the system
◊ High density, low-cost packaging◊ Embedded passives
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Clock DistributionClock Distribution> On-MCM H-tree removes level of clock tree, eliminating up to
150ps of process-induced skew
MCM-D substrate
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High Density Packaging TrendsHigh Density Packaging Trends> Reduced Chip Test Cost for High I/O Chips
2,000 I/OMembrane tester
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Examples of Emerging Design Examples of Emerging Design StylesStyles> Integrated IC-package functionality
NCSU workAlpine SystemsLucent RF Module (above)
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Future Design OpportunitiesFuture Design Opportunities> Mixed Signal
First-pass design success very difficult, and even more difficult with embedded passivesIssues:
◊ System Modeling◊ Co-simulation◊ Independent Process Variations
> Mixed TechnologyMEMS Sensors in general
◊ System Modeling Problem
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Solution PathsSolution Paths> Take Lead from IC World: