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Modern Semiconductor Devices for Integrated Circuits (C. Hu)Slide 3-1
Chapter 3 Device Fabrication Technology
About 10 20 transistors (or 10 billion for every person in theworld) are manufactured every year.
VLS (Very Lar!e Scale nte!ration)"LS ("ltra Lar!e Scale nte!ration)#S (#i!a$Scale nte!ration)
Variations of this versatile technolo!y are used for flat$paneldisplays% micro$electro$mechanical systems ( MEMS )% andchips for &'A screenin!...
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Slide 3-2
3.1 Introduction to Device Fabrication
idation
Litho!raphy *
+tchin!
on mplantation
Annealin! *&iffusion
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Slide 3-3
Si ,afers
2
'2
- 2 or ./+(trichloroethylene)
0uart1 tube
esistance$heated furnace
3lowcontroller
3.2 O idation o! Silicon
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Slide 3-4
3.2 O idation o! SiliconSi 4 2 Si 2
Si 42- 2 Si 2 4 2- 2
&ry idation 5 ,et idation 5
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Slide 3-
E"#M$%E & T'o()tep O idation (a) How long does it take to grow 0.1 m of dry oxide at 1000 oC ?
(b) After step (a), how long will it take to grow an additional0. m of oxide at !00 oC in a wet ambient ?
Solution 5
(a) "rom the #1000 oC dry$ %&r'e in lide * , it takes .+ hr to grow 0.1 m of oxide.
(b) se the #!00 oC wet$ %&r'e only. -t wo&ld ha'e taken 0. hr to grow the 0.1 m oxide and ./hr to grow 0. m oxide frombare sili%on. he answer is ./hr 0. hr 2 1. hr.
3.2 O idation o! Silicon
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Slide 3-!
3.3 %ithography
esist /oatin!(a) &evelopment(c)
+tchin! and esist Strip(d)
6hotoresist
ide Si
+ posure(b)
Si
Si
6ositive resist 'e!ative resist
Si
Si
pticalLens system
&eep "ltraviolet Li!ht
6hotomas7 with
opa8ue andclear patterns
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Slide 3-"
3.3 %ithographyPhotolithography Resolution Limit, *
9 3 k due to optical diffraction9 ,avelen!th needs to be minimi ed. (2:; nm% 1? nm@)9 k (
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Slide 3-#
3.3 %ithography
,afers are bein! loaded into a stepper in a clean room.
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Slide 3-$
%&oto Mas'
%&otoresistafer
ater
(a) ( )
%&oto Mas'%&oto Mas'
%&otoresistafer
%&otoresistafer
ater
(a) ( )
conventional dry litho!raphy wet or immersion litho!raphy
3.3.1 +et %ithography
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Slide 3-1*
eflective photomas7B
Laser produced plasma emittin!+"V
E tre,e - %ithography /13n, 'avelength0
'o suitable lens material at thiswavelen!th. ptics is based on mirrorswith nm flatness.
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Slide 3-11
9 Electron ea, +riting 5 +lectron beam(s) scans and e posed
electron resist on wafer. eady technolo!y with relatively lowthrou!hput.
9 Electron $ro ection %ithography 5 + poses a comple
pattern usin! mas7 and electron lens similar to optical litho!raphy.
9 ano(i,print 5 6atterns are etched into a durable material toma7e a stamp.B his stamp is pressed into a li8uid film overthe wafer surface. Li8uid is hardened with "V to create animprint of the fine patterns.
eyond Optical %ithography
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Slide 3-12
3.4 $attern Tran)!er5Etching Isotropic etching Anisotropic etching
Si 2
Si 2
Si 2
(1)
(2)
photoresist
p h o t o r e s i s t
Si 2
( 1 )
( 2 )
photoresist
p h o t o r e s i s t
Si 2
Si 2
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Slide 3-13
3.4 $attern Tran)!er5Etching
/ross$section View op View
*eactive(Ion Etching Sy)te,)
#as nlet
3 Vacuum
,afers#as Caffle
3
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Slide 3-14
3.4 $attern Tran)!er5Etching
Dry Etching /al)o 6no'n a) $la),a Etching7 or *eactive(Ion Etching0 is anisotropic.
9 Silicon and its compounds can be etched by plasmas
containin! 3.9 Aluminum can be etched by /l.9 Some concerns 5$ Selectivity and +nd$6oint &etection$ 6lasma 6rocess$ nduced &ama!e or ,afer /har!in!
&ama!e and Antenna +ffect
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Slide 3-1
Scanning electron ,icro)cope vie' o! a pla),a(etched8.19 , pattern in polycry)talline )ilicon !il,.
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Slide 3-1!
3.: Doping 3.5.1 Ion Implantation
9 he dominant dopin! method9 + cellent control of dose (cm $2)
9 #ood control of implant depth with ener!y (DeV to EeV)9 epairin! crystal dama!e and dopant activation re8uires
annealin!% which can cause dopant diffusion and loss ofdepth control.
&opant ions
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Slide 3-1"
3.5.1 Ion Implantation Sche,atic o! an Ion I,planter
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Slide 3-1#
3.5.1 Ion implantation
6hosphorous density profile afterimplantation
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Slide 3-1$
3.5.1 Ion Implantation Model o! I,plantation Doping $ro!ile /;au))ian0
22 2F)(
)(2)( 3 3 xi e
3 4 x 4
=
4 i 5 dose (cm $2)
3 5 ran!e or depth 3 5 spread or si!ma
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Slide 3-2*
Other Doping Method)
9 ;a)(Source Doping 5 3or e ample% dope Si with 6usin! 6 /l =.
9 Solid(Source Doping 5 &opant diffuses from a dopedsolid film (Si#e or o ide) into Si.
9 In(Situ Doping 5 &opant is introduced while a Sifilm is bein! deposited.
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Slide 3-21
3.9 Dopant Di!!u)ion
5t xo e 5t
4 t x 4 :F2
)%(
=
4 5 4 d or 4 a (cm $=)
4 o 5 dopant atoms per cm 2t 5 diffusion time
5 5 diffusivity% is the appro imate distance ofdopant diffusion
5t
p$type Si
Si 2
n$typediffusion layer
Gunction depth
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Slide 3-22
3.9 Dopant Di!!u)ion
9 Some applications needvery deep Hunctions (hi!h
% lon!t ). thers needvery shallow Hunctions(low % shortt ).
9 5 increases withincreasin! temperature.
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Slide 3-23
3.9 Dopant Di!!u)ion
Shallo'
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Slide 3-24
3.= Thin(Fil, Depo)itionThree >ind) o! Solid
/rystalline 6olycrystalline
+ ample5Silicon wafer
hin film of Si or metal. hin film ofSi 2 or Si = ' : .
Amorphous
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Slide 3-2
3.= Thin(Fil, Depo)ition
9 Advanced E S3+ !ate dielectric
9 6oly$Si film for transistor !ates
9 Eetal layers for interconnects
9 &ielectric between metal layers
9 +ncapsulation of /
+ amples of thin films in inte!rated circuits
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Slide 3-2!
3.7.1 Sputtering
ar!et materialdeposited on wafer
S i , a f e r
on (Ar 4)
Sputterin! tar!et
Atoms sputtered out of the tar!et
Sche,atic Illu)tration o! Sputtering $roce))
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Slide 3-2"
3.7.2 hemical !apor "eposition # !"$
hin film is formed from !as phase components.Modern Semiconductor Devices for Integrated Circuits (C. Hu)
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Slide 3-2#
So,e Che,ical *eaction) o! C D
6oly$Si 5 Si- : (!) Si (s) 4 2- 2 (!)
Si=': 5 =Si- 2/l 2 (!)4:'- = (!) Si = ' : (s)4J-/l(!)4J- 2 (!)
Si 2 5 Si- : (!) 4 2 (!) Si 2 (s) 4 2- 2 (!) or Si- 2/l 2 (!)42' 2 (!) Si 2 (s)42-/l (!)42' 2 (!)
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Slide 3-2$
wo types of /V& e8uipment5
9 LP !" #Lo% Pressure !"$ 5 #ood uniformity. "sed for poly$Si% o ide% nitride.
9 P& !" #Plasma &nhanced !"$ 5 Low temperature process and hi!h deposition rate. "sed for o ide%
nitride% etc.
3.7.2 hemical !apor "eposition # !"$
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Slide 3-3*
Si ,afers
uart tube
esistance$heated furnace6ressure sensor
#as control Source !ases
6ump
rap e hausto
system
L6/V& Systems
3.7.2 hemical !apor "eposition # !"$
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Slide 3-31
3.7.2 hemical !apor "eposition # !"$
6+/V& Systems
/old ,all 6arallel 6late
-ot ,all 6arallel 6late6ump
6lasma +lectrodes
6ower leads
,afers
#as
nlet
,afers#as nHectionin! 6ump
-eater /oil
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Si 2 Si 2
Substrate
Si 2 Si 2
Substrate
& p i ' i l m
(b)
Substrate
Substrate
&pi 'ilm
(a)
Si Si
Si Si
Slide 3-32
3.7.3 &pita(y /Depo)ition o! Single(Cry)talline Fil,0
+pita y Selective +pita y
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Slide 3-33
3.? Interconnect 5 The ac6(end $roce))
&opant diffusion re!ionSi
Si) 2
Al$/u
(a)
Sidiffusion re!ion
/oSi 2
* etal 1
*etal 2
* etal 3
&ielectric
&ielectric
+ncapsulation
(b)
&ielectric
via or plu!
silicide
Al or /u
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Slide 3-34
SEM& Multi(%evel Interconnect /a!ter re,oving the dielectric0
3.? Interconnect 5 The ac6(end $roce))
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Slide 3-3
Copper Interconnect 9 Al interconnect is prone to voids formation by
electromi!ration.
9 /u has e cellent electromi!ration reliabilityand :0K lower resistance than Al.
9 Cecause dry etchin! of copper is difficult (copperetchin! products tend to be non$volatile)% copper
patterns are defined by a da,a)cene process.
3.? Interconnect 5 The ac6(end $roce))
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Slide 3-3!
dielectric
dielectric dielectric
dielectric
/u
/u
liner liner
(a) (b)
(c) (d)
Copper Da,a)cene $roce))
9/hemical$Eechanical6olishin! (/E6) removes unwantedmaterials.
9Carrier liner prevents/u diffusion.
3.? Interconnect 5 The ac6(end $roce))
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Slide 3-3"
3.? Interconnect 5 The ac6(end $roce))
$lanari@ation
9 A flat surface is hi!hly desirable for subse8uentlitho!raphy and etchin!.
9 /E6 (/hemical$Eechanical 6olishin!) is used to planari e each layer of dielectric in the
interconnect system. Also used in the front$end process.
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Slide 3-3#
3.A Te)ting7 #))e,bly7 and Buali!ication
9 ,afer acceptance test9 &ie sortin!9 ,afer sawin! or laser cuttin!9 6ac7a!in!
9 3lip$chip solder bump technolo!y9 Eulti$chip modules9 Curn$in9 3inal test
9 ualification
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Slide 3-3$
3.18 Chapter Su,,ary5# Device Fabrication E a,ple
,afer
idation
Litho!raphy
+tchin!
Annealin! *&iffusion
AlSputterin!
(0)
6ositive resist Si 2
6$Si
6$Si
Si 26$Si
Eas7
"V
Si 2 Si 2
6$Si
( 1 )
(2)
(=)
Si 2
"V
Litho!raphy
Si 2 Si 2
Si 2 Si 2
6 ' 4
Si 2 Si 2
6 ' 4
6$Si
Si 2 Si 2
6 ' 4
Eas7
Al esist
(:)
Arsenic implantation
A l
"V
(?)
(>)
(J)
A l
"V
on
mplantation
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Eetaletchin!
/V&nitridedeposition
Litho!raphyand etchin!
Cac7 Sidemillin!
Cac7 sidemetalli ation
&icin!% wire bondin!%and pac7a!in!
3.18 Chapter Su,,ary5# Device Fabrication E a,ple
Si 2 Si 2
6 '4
(;)
(