Cheng-Wen Wu (吳誠文Semiconductor Memory Diagnostics Cheng-Wen Wu (吳誠文) IC Design Technology Center (DTC) National Tsing Hua University. Hsinchu, Taiwan

Semiconductor Memory Diagnostics

Semiconductor Memory Semiconductor Memory DiagnosticsDiagnostics

Cheng-Wen Wu (吳誠文)

IC Design Technology Center (DTC)National Tsing Hua University

Hsinchu, Taiwan

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OutlineOutlineIntroductionFault models and March testsMemory error catch and analysis (MECA) systemDiagnostic algorithm generationDiagnostic data compressionConclusions

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IntroductionIntroductionMemory testing is more and more important• Memories are key components

Represent about 30% of the semiconductor marketDominate the chip area/yield

Memory testing is more and more difficult• Growing density, capacity, and speed• Emerging new architectures & technologies• Growing need for embedded memories

Why diagnostics?• Yield improvement

Repair and/or design/process debugging

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Memory Functional Model ExampleMemory Functional Model Example

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RAM Fault ModelsRAM Fault ModelsAddress-Decoder Fault (AF)Stuck-At Fault (SAF)Transition Fault (TF)Stuck-Open Fault (SOF)Coupling Fault (CF)• State Coupling Fault (CFst) • Inversion Coupling Fault (CFin)• Idempotent Coupling Fault (CFid)

Disturb Fault (DF)Data Retention Fault (DRF)

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March TestsMarch Tests

March C [Marinescu 1982]• For AF, SAF, TF, & all CFs---redundant

March C- [Goor 1991]

• Also for AF, SAF, TF, & all CFs---irredundant

)}0();0,1();1,0();0();0,1();1,0();0({

rwrwrrwrwrw

cc

c

⇓⇓

⇑⇑

)}0();0,1();1,0();0,1();1,0();0({

rwrwrwrwrw

c

c

⇓⇓

⇑⇑

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RAMSES Simulation ResultsRAMSES Simulation Results

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Fault Model SubtypesFault Model Subtypes

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NTHUNTHU--FTC BIST ArchitectureFTC BIST Architecture

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Test ModeTest ModeIn Test Mode it runs a fixed algorithm for production test and repair• Only a few pins need to be controlled, and

BGO reports the result (Go/No-Go)

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Fault Analysis ModeFault Analysis ModeIn Fault Analysis Mode, we can apply a longer March algorithm for diagnosis• FSI captures the error information of the faulty cells

EOP format:

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Error Catch and AnalysisError Catch and AnalysisLocate the faulty cellsIdentify the fault types

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How to Identify Fault Type?How to Identify Fault Type?Tester/BIST OutputRAM Circuit/Layout

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March DictionaryMarch DictionaryMarch 11N

E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10

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March Signature and Error MapMarch Signature and Error MapMarch Signature (Syndrome)

Error Map

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MECA SystemMECA System

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Error AnalyzerError Analyzer

Data log parser

Tester/BIST data log

Fault analysis

Error maps

Fault maps

March Dictionary

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Fault AnalysisFault AnalysisDerive analysis equations from the fault dictionary

• Convert error maps to fault maps by the equations

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Test Algorithm GenerationTest Algorithm Generation• Start from a base test: generated by TAGS or

user-specified• Generation options reduced to read-insertions

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Diagnostic ResolutionDiagnostic ResolutionDiagnostic resolution

faults detectable of#faults habledistinguis of # resolution Diagnostic =

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Experimental ResultsExperimental ResultsProposed diagnosis framework has been applied to commercial embedded SRAMsResults for a 16Kx8 embedded SRAM (FS80A020) are shownTester log from Credence SC212 is examinedAddress remapping (logical to physical) is applied

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The Total Error BitmapThe Total Error Bitmap

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Fault BitmapsFault BitmapsIdempotent Coupling Fault Stuck-at 0

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Diagnostic Data CompressionDiagnostic Data CompressionDiagnostic data usually are exported serially to the tester• Excessive tester time• Increased tester storage requirementCompression can solve this problemWe propose• Compression by syndrome accumulation• Tree-based Hamming syndrome compression

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Syndrome AccumulationSyndrome AccumulationConventional approach for exporting diagnostic data:• Each time a fault is detected, the BIST circuit

exports the faulty-cell address and March syndrome

There is redundancy since a fault can be detected by many Read operations during the test process

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Syndrome Accumulation ExampleSyndrome Accumulation Example

000 001 010 011 100 101 110 111

000

001

010

011

100

101

110

111

Column address

Row

address

Fault Diagnosis data

SAF(1)

CFst(H,0,0)

SAF(0)

CFin(L, , )

D1=(100010, 100011100011)SAF(1)

CFin(L, , )

SAF(0)

CFst(H,0,0)

D1=(101110, )

D1=(100010, )

D1=(100010, )

100000001100

011100011100

011100000100

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Syndrome Accumulation Circuit (SAC)Syndrome Accumulation Circuit (SAC)

Faulty-cell Address March Syndrome

CAM

Data Register

Mask Register

AddressingM

echanism

01

01

Vdd

S

01

01

Vdd

S

01

01

Vdd

S

Up/dow

n shift register

Mk-1

Wk-1

M1

W1

M0

W0

HitClkRst SData Register

W0

M0W1

M1

Wk-1

Mk-1

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Compression RatioCompression RatioWe define the compression ratio as

R = compressed bits/original bits

Comparison:RAM sizeMarch CdModified March CMarch-26NMarch-12NMarch-17N

256K36.84%26.19%30.30%45.71%28.89%

512K36.52%25.79%29.95%45.45%28.55%

1M36.23%25.42%29.62%45.21%28.24%

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Hardware OverheadHardware OverheadWe use the register-bit equivalent (rbe) modelHardware overhead (HO) vs. largest number of faults (K)

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Compression for Word-Oriented RAMDiagnostic data for word-oriented RAM

Faulty-cell addressMarch syndromeHamming syndrome

Hamming syndromeThe modulo-2 sum of the expected fault-

free data output vector and the output vector from the memory under test

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MotivationEmbedded RAM usually has long words

Diagnostic data dominated by Hamming syndrome

8kx256-bit RAM & March Cd (72 Read operations, extended for word-oriented RAM with 9 data backgrounds):

13-bit faulty address7-bit March syndrome256-bit Hamming syndrome

About 0.93 of the diagnostic data

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Basic IdeaA source message is regarded as a sequence of symbols with fixed sizeFor example, (00101001001001000100) can be represented by {0010 1001 0010 0100 0100}

Only three unique symbols {0010 1001 0100} appear in this exampleWe thus can compress the message by removing the redundancy

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Hamming Syndrome CompressionTree-basedCodeword

10

0

0

0 1

1

11 0

0

124

83 5 6

7 9 A B CD E F

Symbol Hexadecimal

0123456789ABCDEF

101101000000011001000001010000011000000111000100001001000010100000101100001100000011010000111000001111

0000000100100011010001010110011110001001101010111100110111101111

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EvaluationA 128Kb RAM with 2kx64, 1kx128, and 512x256 configurations are consideredThree different symbol sizes (B=4, 8, and 16) are used to estimate R

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Experimental ResultsR for 64-bit HS R for 128-bit HS R for 256-bit HSRF

100150200250500100150200250500100150200250500

B=4 B=8 B=16 B=4 B=8 B=16 B=4 B=8 B=16

26.8% 15.1% 9.6%26.9% 15.2% 9.7%26.9% 15.2% 9.9%27.0% 15.3% 10.0%27.2% 15.7% 10.7%

25.9% 13.8% 8.0%26.0% 13.9% 8.1%26.1% 14.0% 8.2%26.1% 14.1% 8.2%26.4% 14.5% 9.0%

Without Other faults

With two Faulty rows

With 10% cluster faults

28.6% 17.5% 12.9%28.7% 17.6% 13.1%28.7% 17.7% 13.2%28.8% 17.7% 13.3%29.0% 18.2% 14.1%32.3% 20.4% 15.3%31.1% 19.5% 14.5%30.5% 19.4% 14.2%30.1% 18.9% 14.3%29.8% 18.8% 14.6%

31.7% 22.4% 20.5%31.9% 22.3% 20.7%31.9% 22.4% 21.0%31.9% 22.5% 21.2%32.4% 23.2% 22.3%

29.8% 17.1% 10.1%28.5% 16.1% 10.0%28.1% 15.7% 9.7%27.8% 15.5% 9.7%27.5% 15.4% 9.7%

30.6% 18.1% 12.3%29.3% 17.1% 11.6%28.8% 16.9% 11.3%28.6% 16.5% 11.2%28.1% 16.3% 11.2%

29.0% 18.0% 14.2%29.1% 18.1% 14.4%29.1% 18.2% 14.5%29.3% 18.4% 14.8%29.6% 19.0% 15.8%

27.5% 15.9% 10.9%27.7% 16.0% 11.1%27.7% 16.1% 11.3%27.8% 16.2% 11.5%28.3% 17.0% 12.7%

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ConclusionsConclusionsOur diagnosis framework provides error catch and analysis• For design/process verification and debugging• For yield improvement

Our syndrome accumulation method compresses faulty-cell address and March syndrome to about 28% of the original size• Hardware overhead is about 0.9% for a 1Mb SRAM

with 164 faultsOur tree-based method compresses the Hamming syndromes to about 10% for a 128Kb RAM with a 16-bit symbol size and 100-500 random faults