CHARGE COUPLING TRUE CDS PIXEL PROCESSING True CDS CMOS pixel noise data 2.8 e- CMOS photon transfer.

CHARGE COUPLINGTRUE CDS PIXEL PROCESSING

True CDS CMOS pixel noise data

2.8 e- CMOS photon transfer

FULL WELL / NONLINEARITY

3T PHOTO DIODE PIXEL

FULL WELL DEPENDENT ON PHOTO DIODE CAPACITANCE

NONLINEAR RESPONSE CAUSED BY PHOTO DIODE CAPACITANCE DEPENDENCE ON SIGNAL

NONLINEARITY MAY BE ADVANTAGEOUS FOR EXTENDED DYNAMIC RANGE

5T / 6T CHARGE COUPLE PIXEL

FULL WELL DEPENDENT ON SENSE NODE CAPACITANCE

LINEAR RESPONSE BECAUSE SENSE NODE IS DECOUPLED FROM PHOTO REGION

SOURCE FOLLOWER GATE CAPACITANCE CAN BE MADE TO BE DOMINATE SENSE NODE CAPACITANCE FOR GOOD LINEARITY

3T FULL WELL

LED

GND

VSS = -6 V

0.5 V 2 V

RESETFULL WELL

Source follower gain = 0.8 V/V

Source followeroutput voltage

RAW VIDEO

3T LINEARITY

PHOTO GATE FULL WELL

PHOTO GATE LINEARITY

CHARGE TRANSFER EFFICIENCY

CHARGE COUPLED SURFACE CHANNEL PIXEL

SURFACE STATE DENSITY FOR CMOS IS CONSIDERABLY GREATER THAN CCD

EXHIBITS POOR CTE PERFORMANCE BECAUSE OF INTERFACE TRAPS

CTE SENSITIVE TO HIGH ENERGY RADIATION SOURCES

CHARGE COUPLED BURIED CHANNEL PIXEL

EXHIBITS EXCELLENT CTE PERFORMANCE

RAD HARD CTE PERFORMANCE

NOISE VARIANCE

NOISE

3

4

5

6

7

8

9

10

11

12

13

14

15

0 5 10 15 20 25 30

CURRENT, (uA)

NO

ISE

, (e

-)

T7A-1

T7A-2

T7A-3

T7A-4

T7A-5

T7A-6

T7A-7

CHARGE COUPLED PG PIXEL

SURFACE vs BURIED CHANNEL CTE

SURFACE CHANNEL

BURIED CHANNEL

SURFACE CHANNEL PHOTOGATE

PRE RAD

250 krad

CMOS DARK CURRENT

DARK CURRENT IS THE MOST LIMITING PERFORMANCE PARAMETER FOR CMOS IMAGERS

DARK CURRENT IS THE MOST DIFFICULT PARAMETER TO UNDERSTAND AND LOWER

SURFACE STATE DENSITY IS SIGNIFICANTLY GREATER THAN CCD. HENCE, HIGHER DARK CURRENT

MPP CCD < 10 pA/cm^2 3T CMOS pixel > 0.5 nA/cm^2CUSTOM CHARGE COUPLED PINNED PHOTO DIODE CMOS PIXELS < 30 pA/cm^2

DARK CURRENT PROBLEMSLIMITED H2 ANNEALING DURING CMOS FABRICATIONHIGH FIELD ASSISTED DARK CURRENT GENERATIONSHALLOW TRENCH ISOLATION (STI) DARK CURRENTLUMINESCENCEGATE LEAKAGEOXIDE TUNNELINGSILICON WAFER ISSUES (QUALITY, PROPER GETTERING, etc.)

3T PHOTODIODE DARK CURRENT

FRONTSIDE

BACKSIDE

INVERTED BURIED CHANNEL PHOTO GATE OPERATION

CMOS RAD HARDNESS

IONIZATION DAMAGE

3T READ MOSFETS (RESET, ROW SELECT AND SOURCE FOLLOWER) EXHIBIT VERY LITTLE LEAKAGE AND FLAT BAND SHIFT IN REACTION TO 1 Mrd Co-60 RADIATION

SOURCE FOLLOWER FLICKER NOISE INCREASE

THERMAL DARK CURRENT INCREASE

BULK DAMAGE

DARK SPIKES (HOT PIXELS)

QE LOSS WITHIN NON DEPLETED MATERIAL

FLAT BAND SHIFT(ROW SELECT MOSFET)

PHOTON TRANSFER CHARACTERISTICS

3T DEEP N WELL

DARK CURRENT AND DARK SPIKES

DARK SPIKES 10 krd

DARK CURRENT 1 Mrd

CMOS ARRAY PROBLEMS FOR SCIENTIFIC PERFORMANCE

ON-CHIP CMOS FEATURES OFTEN DEGRADE FUNDAMENTAL PIXEL PERFORMANCEe.g. ANALOG TO DIGITAL CONVERTER (ADC) LIMITS PERFORMANCE TO 12 BIT DYNAMIC RANGE

INFLEXIBILITY TO CHANGE CRITICAL PIXEL TIMING AND READOUT MODESe.g., 3T, 5T, 6T PIXEL CLOCKING ROLLING SHUTTER, PROGRESSIVE SCAN AND SNAP READOUT

INABILITY TO CHANGE CDS TIMING, SYSTEM BANDWIDTH, GAIN AND OFFSET

INABILITY TO CLOCK PIXELS WITH DRIVE VOLTAGES GREATER THAN VDD

INABILITY TO CONTROL,GROUND AND FILTER REGULATED VOLTAGES EXTERNALLY

SCIENTIFIC CMOS ARRAYS ARE BEING DESIGNED WITH THESE LIMITATIONS IN MIND (e.g. ALLOW OFF CHIP ADC)

HYBRID ARRAYS: CMOS TO CMOS

512 x 512 sparse bumped“monolithic mosaic.”

Frame rate vs array size

HYBRID ARRAYS: CMOS TO CMOS

↑ CMOS pixel array CMOS ROIC array voltage compatible.

↑ CMOS pixel array is fabricated independently from ROIC array (allowing pixel optimization and isolation).

↑ Sparse bumping can take place within the array.

↑ Tolerant to high-energy radiation sources.

↑ Very high resolution – ultra high speed operation.

↑ Read noise independent of array size or frame rate.

↑ Low power / compact sensor designs.

↓ High cost for custom pixel CMOS processing.