Chapter 3 Composer Schematic Capture C OMPOSERis the schematic capture tool that is bundled with the the dfII ( Design Framewo rk II ) tool set. It is a full-fea tued schemat ic captur e tool that we’ ll use for des igning tra nsistor le vel schemat- Although the schematictool is calledComposerin thedocumentation, it’s calledVirtuosoSchematic Editingin the window title. Virtuosois also thespecific name given tothe layout editor in dfII. They’re both part of thedfIIVirtuosotool suiteI guess. ics for small cells, gate level schematics for larger circuits, and schematics contain ing a mix of gates and V erilog code for more complex circ uits. In that case some of the components in the schematic will contain transistors at the lowest level, and some will contain Verilog code. Because the simula- tors that are used in conjunction with Composer are all Verilog simulators, these mixed schematics can be simulated using the same simulators used by schema tics with only gates or transistors. I find schemati cs extre mel y use ful for all le vel s of design. Eve n for designs that are done completely in Verilog code I find that connecting the Verilog components in a schematic often makes things easier to understand than large pieces of code where connections are made with large argument lists and named wires. Your mileage may vary, of course. Composer has conne ctio ns to all sort s of other tools in the dfII tool Composer is a part ofthe IC v5.1.41 tools suite, and to other tool suites. We’ll look at all of them in future chapters. • Composer is integrated with the Verilog-XLand NC Verilog sim- A file that captures thecomponent andconnection information for a circuit is called a“netlist,” and the process of generating that file is called “netlisting.”ulators so that you can automatically export a schematic to a simula- tor. The Composer /V erilog integration will take your schematic and genera te a Verilog netlist for simulation, and also build a simple test- bench wrapper as a Verilog file that you can modify with your own testing commands. We’ll see how that works in the chapter on Verilog simulation. • There is also an interface that can take a schematic and convert that schematic to the Verilog structural file for input to a tool that uses that type of inp ut. Synopsy s dc shell for synthesis and Cadence SOC
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COMPOSER is the schematic capture tool that is bundled with the the
dfII ( Design Framework II) tool set. It is a full-featued schematiccapture tool that we’ll use for designing transistor level schemat- Although the schematic
tool is called
Composer in the
documentation, it’s
called Virtuoso
Schematic Editing in
the window title.
Virtuoso is also the
specific name given to
the layout editor in dfII.
They’re both part of the
dfII Virtuoso tool suite
I guess.
ics for small cells, gate level schematics for larger circuits, and schematics
containing a mix of gates and Verilog code for more complex circuits. In
that case some of the components in the schematic will contain transistors
at the lowest level, and some will contain Verilog code. Because the simula-
tors that are used in conjunction with Composer are all Verilog simulators,
these mixed schematics can be simulated using the same simulators used by
schematics with only gates or transistors.
I find schematics extremely useful for all levels of design. Even for
designs that are done completely in Verilog code I find that connecting the
Verilog components in a schematic often makes things easier to understandthan large pieces of code where connections are made with large argument
lists and named wires. Your mileage may vary, of course.
Composer has connections to all sorts of other tools in the dfII tool Composer is a part of
the IC v5.1.41 toolssuite, and to other tool suites. We’ll look at all of them in future chapters.
• Composer is integrated with the Verilog-XL and NC Verilog sim- A file that captures the
component and
connection information
for a circuit is called a
“netlist,” and the process
of generating that file iscalled “netlisting.”
ulators so that you can automatically export a schematic to a simula-
tor. The Composer /Verilog integration will take your schematic and
generate a Verilog netlist for simulation, and also build a simple test-
bench wrapper as a Verilog file that you can modify with your owntesting commands. We’ll see how that works in the chapter on Verilog
simulation.
• There is also an interface that can take a schematic and convert that
schematic to the Verilog structural file for input to a tool that uses that
type of input. Synopsys dc shell for synthesis and Cadence SOC
1. Start up Cadence dfII by running the command cad-ncsu . as de-
scribed in Chapter 2. You may have used (and may still be using) a
different setup for a different class, but please use cad-ncsu for
this class. You should get a window (called the Command Informa-
tion Window or CIW) similar to the one shown in Figure 2.1.
2. You should also get another window for the Library Manager as
shown in Figure 2.2. The libraries that you’ll see in the default Li-
brary Manager window are described in Chapter 2.
3. In order to build your own schematics, you’ll need to define your Librarys are defined in a
cds.lib file that is
created in your cadence
directory.
own library for your own circuits. To create a new working library in
the library manager, select File → New → Library. In the Create
Library window that appears fill in the Name field as tutorial, or
whatever you’d like to call your library. Leave the Path field blank so
that it creates the new library under the directory in which you started
Cadence. If you want to create a library somewhere other than in your˜ /IC CAD/cadence directory you can put the whole path in the path Don’t make your library
name start with a
number, and don’t use
“-“ or “.” in the name!
An underscore is all
right.
field. In the Technology Library box select Attach to an existing
tech library and choose the UofU AMI 0.60u C5N technology li-
brary. The dialog box is shown in Figure 3.1 Now press OK and the
new library will show up in your Library Manager window.
Now the working library has been created. All the project cells (compo-
nents) that you generate should end up in this library. When you start up the
Library Manager to begin working on your circuits, make sure you select
your own library to work in.
3.2 Creating a New Cell
When you create a new cell (component in the library), you actually create
a view of the cell. For now we’ll be creating “schematic” views, but We’ll eventually use
“cmos sch” views for
individual leaf cells and
“schematic” views for
cells with hierarchy. For
now we’ll just make
“schematic” views to
keep things simple.
eventually you’ll have lots of different views of the same cell. For example,
a “layout” view of the same cell will have the composite layout information
in it. It’s a different file, but it should represent the same circuit. More about
that later. For now, we’re creating a schematic view. To create a cell view,
carry out the following steps
Creating the Schematic View of a Full Adder
1. Select the tutorial library you just created in the Library Manager.
CHAPTER 3: Composer Schematic Capture Draft August 24, 2006
is shown in Figure 3.13.
Change the properties of the nmos transistor by changing the Width
to 3u M (3 microns). Leave the length as 600n M (0.6 microns).
Similarly follow the steps for the pmos transistor with W/L = 3/0.6
(i.e. W = 3u M amd L = 600n M ).
4. Create a symbol for the NAND gate by selecting Design → Create
CellView → From CellView. The Cadence-generated symbol will
be a simple rectangle. You can easily modify it to make it look like
Figure 3.14 using arcs and circles.
Note that in order to get the circle for the nand2 bubble to be the right
size in proportion to the rest of the gate you may have to use a finer
grid while you’re drawing that circle. You can change the grid size in
the Options → Display Options dialog box, as the Snap Spacing
value. But, when you’re done make sure that you set the snap grid
back to 0.0625 so that the pins you make will match up properly withthe wires in the schematic!
3.4 Printing Schematics
To print schematics you need to have printers set up by your tools adminis-
trator. The printers available to you are defined in a .cdsplotinit file. This
file lives in the Cadence installation tree, but may also exist in a site-specific
location for local printer information. It contains printer descriptions thatDetails of the
.cdsplotinit file can be
found in Chapter Adescribe which plot drivers should be used (usually postscript), and how to
spool the output to the printer. There is usually at least one postscript or eps(encapsulated postscript) option defined so that if you plot to a file you can
get a postscript version of your schematic.
To print (plot) a schematic, select the Design → Plot → Submit...
menu choice. This will bring up the Submit Plot dialog box (seen in Fig-
ure 3.15). If all the choices are correct, you can select OK to plot the file.
If you’ve selected a printer the schematic will print to that printer. If you’ve
selected the Plot To File option you will get a file in the directory from
which you started Cadence. Those are options that you have to select from
the Plot Options... choice though.
When you click on the Plot Options... button you get another dialog
box for the plot options as seen in Figure 3.16. This dialog box lets youset up all sorts of details about how you want your schematic plotted. The
important options are:
Top Section: In this section you cand choose which plotter (printer) you
wish to send your hard copy to with the Plotter Name selection.