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Chapter_11 DC - AC Converter

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    Chapter 11

    DC AC Converters (Invertors)

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    10

    Three-Phase, Step-Wave InverterCircuits

    10.1 SKELETON INVERTER CIRCUIT

    The form of voltage-source inverter (VSI) most commonly used consists of athree-phase, naturally commutated, controlled rectifier providing adjustable direct

    voltage Vdc as input to a three-phase, force-commutated inverter (Fig. 10.1). The

    rectifier outputinverter input section is known as the dc link. In addition to a

    shunt capacitor to aid direct voltage stiffness the link usually contains series

    inductance to limit any transient current that may arise.

    Figure 10.2a shows the skeleton inverter in which the semiconductor recti-

    fier devices are shown as generalized switches S. The notation of the switching

    devices in Fig. 10.2 is exactly the same as for the controlled rectifier in Fig. 7.1

    and the naturally commutated inverter ofFig. 9.1. In high-power applications theswitches are most likely to be SCRs, in which case they must be switched off

    by forced quenching of the anode voltages. This adds greatly to the complexity

    and cost of the inverter design and reduces the reliability of its operation.

    If the inverter devices are GTOs (Fig. 10.2b), they can be extinguished

    using negative gate current. Various forms of transistor switches such as BJTs

    (Fig. 10.2c), and IGBTs (Fig. 10.2d) can be extinguished by control of their base

    currents, as briefly discussed in Chapter 1. In Fig. 10.2 the commutating circuitry

    is not shown. It is assumed in the following analysis that each switch can be

    opened or closed freely.

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 1 Basic form of voltage-source inverter (VSI) [20].

    From the power circuit point of view all versions of the skeleton inverterofFig. 10.2 are identical. In each case the frequency of the generated voltages

    depends on the frequency of gating of the switches and the waveforms of the

    generated voltages depend on the inverter switching mode.The waveforms of the

    associated circuit currents depend on the load impedances.

    Manydifferent voltage waveforms canbe generated bythe use ofappropriate

    switching patterns in the circuit of Fig. 10.2. An invariable requirement in three-

    phase systems is that the three-phase output voltages be identical in form but phase

    displaced by 120 electrical from each other. This does not necessarily create a bal-

    anced set of load voltages, in the sinusoidal sense of summing to zero at every in-

    stant of the cycle, but it reduces the possibility of gross voltage unbalance.

    A voltage source inverter is best suited to loads that have a high impedance

    to harmonic currents, such as a series tuned circuit or an induction motor. The

    series inductance of such loads often results in operation at low power factors.

    10.2 STEP-WAVE INVERTER VOLTAGEWAVEFORMS

    For the purpose of voltage waveform fabrication it is convenient to switch thedevices of Fig. 10.2 sequentially at intervals of 60 electrical or one-sixth of a

    period. The use of a dc supply having equal positive and negative voltage values

    Vdc is common. The zero point of the dc supply is known as the supply zero

    pole but is not grounded.

    10.2.1 Two Simultaneously Conducting Switches

    If two switches conduct at any instant, a suitable switching pattern is defined in

    Fig. 10.3 for no-load operation. The devices are switched in numerical order, and

    each remains in conduction for 120 electrical. Phase voltages vAN, vBC, and vCN

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 2 Skeleton switching circuit of voltage source inverter: (a) general switches, (b)

    GTO switches, (c) BJT switches, and (d) IGBT switches [20].

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 3 Load voltage waveforms with two simultaneously conducting switches. No load

    and resistive load [20].

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    consist of rectangular pulses of heightVdc. If equal resistors R are now con-

    nected in star to the load terminals A, B, and C of Fig. 10.2, the conduction

    pattern ofFig. 10.4 ensues for the first half period.

    In interval 0 t /3,

    22

    0

    2

    2

    = = =

    =

    = = = +

    v I R VR

    R V

    v

    v I RV

    RR V

    v

    AN Ldc

    dc

    BN

    CN Ldc

    dc

    AB == + = = v v v v V AN NB AN BN dc (10.1)

    In the interval /3 t 2/3,

    0== = +

    = = +

    = +

    v

    v I R V

    v I R V

    v V

    AN

    BN L dc

    CN L dc

    AB dc(10.2)

    In the interval 2/3 t ,

    0

    2

    = = +

    = = =

    =

    v I R V

    v I R V

    v

    v V

    AN L dc

    BN L dc

    CN

    AB dc(10.3)

    For each interval it is seen that the load current during conduction is

    IV

    R

    V

    RL

    dc dc=

    = 2

    2 (10.4)

    The results of Eqs. (10.1)(10.4) are seen to be represented by the waveforms

    ofFig. 10.3. For this particular mode of switching the load voltage and current

    waveforms with star-connected resistive load are therefore identical with the

    pattern of the open-circuit voltages. The potential of load neutral point Nis always

    midway between Vdc and Vdc and therefore coincides with the potential of

    the supply midpoint 0.

    Phase voltage waveform vAN in Fig. 10.3 is given by an expression

    v AN dc dct V V= = ( ),

    ,

    240

    120

    60 360

    0 300

    (10.5)

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 4 Current conduction pattern for the case of two simultaneously conducting

    switches: (a) 0 t 60, (b) 60 t 120, and (c) 120 t 180 [20].

    This has the rms value

    V t d t V V AN AN dc dc= = =1

    2

    2

    30 816

    2

    0

    2

    v

    ( ) .

    (10.6)

    The fundamental Fourier coefficients of waveform vAN (t) are found to be

    a t t d t V AN dc1 0

    21 2 3

    = = v

    ( ) cos

    (10.7)

    b t t d t AN1 0

    210= = v

    ( ) sin

    (10.8)

    c a b a V dc1 12

    12

    1

    2 3= + = =

    (10.9)

    11 1

    1

    1 90= = = tan tan ( )a

    b

    (10.10)

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    It is seen from Eqs. (10.9) and (10.10) that the fundamental (supply frequency)

    component of the phase voltages has a peak value (23/) Vdc, or 1.1Vdc withits origin delayed by 90. This (23/)Vdc fundamental component waveformis sketched in Fig. 10.3.

    The distortion factor of the phase voltage is given by

    = = =V

    V

    c

    V

    AN

    AN AN

    1 1 2 3/

    Distortion factor

    (10.11)

    Line voltage vAB (t) in Fig. 10.3 is defined by the relation

    v AB dc dc dct V V V ( ),

    ,

    ,

    ,= +

    120 240

    60 180

    60 300

    0 240

    1802

    120

    360

    3002Vdc (10.12)

    This is found to have fundamental frequency Fourier coefficients of value

    a V

    b V

    c V

    dc

    dc

    dc

    1

    1

    1 11

    3 3

    3

    63 60

    =

    = +

    = = =

    Therefore, tan

    (10.13)

    The fundamental component ofvAB (t) is therefore given by

    v

    AB dct V t16

    60( ) sin( )= (10.14)

    It is seen in Fig. 10.3 that vAB1 (t) leads vAN1 (t) by 30, as in a balanced three-

    phase system, and comparing Eqs. (10.9) and (10.13), the magnitude |VAB1| is3 times the magnitude |VAN1|.

    With a firing pattern of two simultaneously conducting switches the load

    voltages of Fig. 10.3 are not retained with inductive load. Instead, the load volt-ages become irregular with dwell periods that differ with load phase-angle. Be-

    cause of this, the pattern of two simultaneously conducting switches has only

    limited application.

    10.2.2 Three Simultaneously Conducting Switches

    A different load voltage waveform is generated if a mode of switching is used

    whereby three switches conduct at any instant. Once again the switching devices

    conduct in numerical sequence but now each with a conduction angle of 180

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    electrical. At any instant of the cycle three switches with consecutive numbering

    are in conduction simultaneously. The pattern of waveforms obtained on no load

    is shown in Fig. 10.5. With equal star-connected resistors the current conduction

    patterns ofFig. 10.6 are true for the first three 60 intervals of the cycle, if the

    load neutral N is isolated.

    For each interval,

    IV

    R R

    V

    R

    dc dc=+

    =2

    2

    4

    3/ (10.15)

    FIG. 5 Output voltage waveforms with three simultaneously conducting switches. No

    load [20].

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 6 Current conduction pattern for the case of three simultaneously conducting

    switches. Star-connected R load: (a) 0 t 60, (b) 60 t 120, and (c) 120

    t 180 [20].

    In the interval 0 t /3,

    2

    2

    3

    4

    3

    2

    = = =

    = =

    = =

    v vI

    R V

    v IR V

    v v v V

    AN CN dc

    BN dc

    AB AN BN dc (10.16)

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    In the interval /3 t ,

    1

    2

    2

    3

    4

    32

    = = =

    = =

    =

    v v R V

    v IR V

    v V

    AN BN dc

    CN dc

    AB dc(10.17)

    In the interval 2/3 t ,

    1

    2

    2

    3

    4

    3

    0

    = = =

    = =

    =

    v v R V

    v IR V

    v

    AN BN dc

    CN dc

    AB(10.18)

    The load voltage waveforms obtained with star-connected resistive load are plot-

    ted inFig. 10.7. The phase voltages are seen to be different from the corresponding

    no-load values (shown as dashed lines), but the line voltages remain unchanged.

    Although the no-load phase voltages do not sum to zero, the load currents, with

    three-wire star connection, must sum to zero at every instant of the cycle. In Fig.

    10.7 the phase voltage vAN is given by

    v AN dc dct V V( ),

    ,

    ,

    ,= +

    2

    3

    2

    3

    4

    3

    60 180

    0 120

    240 360

    180 300VV Vdc dc

    120

    60

    300

    240

    4

    3

    (10.19)It can be seen by inspection in Fig. 10.7 that the fundamental frequency compo-

    nent ofvAN (t) is in time phase with it, so that

    1

    11 1

    1

    0

    0

    =

    = =tanb (10.20)

    Fundamental frequency Fourier coefficient b1 for the load peak phase voltage is

    found to be

    b c Vdc1 14

    = = (10.21)

    The corresponding fundamental (supply) frequency Fourier coefficients for line

    voltage vAB (t) are given by

    a

    1

    1

    2 3

    6

    =

    =

    V

    b V

    dc

    dc

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    FIG. 7 Output voltage waveforms with three simultaneously conducting switches. Star-

    connected R load, isolated neutral. No-load waveforms [20].

    1

    11

    43 3

    1

    330

    = =

    = =

    c Vdc the phase value

    tan(10.22)

    The positive value30 for 1 implies that its origin lies to the left of the zero

    on the scale of Fig. 10.7. Line voltage component AB (t) is plotted in Fig. 10.7,

    consistent with Eq. (10.22).

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    The fundamental components of the load voltages, plotted in Fig. 10.7

    show that, as with a three-phase sinusoidal system, the line voltage leads its

    corresponding phase voltage by 30. The rms value of phase voltage vAN (t) is

    found to be

    V t d t V V AN AN dc dc= = =1 2 23 0 9432

    0v ( ) . (10.23)

    Combining Eqs. (10.21) and (10.23) gives the distortion factor of the phase

    voltage,

    = = =V

    V

    c

    V

    AN

    AN AN

    1

    1

    2 3

    Distortion factor

    (10.24)

    This is seen to be identical to the value obtained in Eq. (10.11) for the phasevoltage waveform of Fig. 10.3 obtained with two simultaneously conducting

    switches. Although the distortion factors are identical, waveform AN (t) of Fig.

    10.7 has a slightly greater fundamental value (4/)Vdc than the corresponding

    value (23/)Vdc for AN (t) of Fig. 10.3, given by Eq. (10.7). The switchingmode that utilizes three simultaneously conducting switches is therefore poten-

    tially more useful for motor speed control applications. The properties of relevant

    step waves and square waves are summarized in Table 10.1.

    It can be deduced from the waveforms of Fig. 10.7 that load neutral point

    N is not at the same potential as the supply neutral point 0. While these pointsremain isolated, a difference voltage VNO exists that is square wave in form, with

    amplitudeVdc/3 and of frequency three times the inverter switching frequency.

    If the two neutral points are joined, a neutral current will flow that is square wave

    in form, of amplitudeVdc/R, and of three times the inverter switching frequency.

    10.3 MEASUREMENT OF HARMONICDISTORTION

    The extent of waveform distortion for an alternating waveform can be definedin a number of different ways. The best known of the these, the distortion factor

    defined by Eq. (10.24), was used in connection with the rectifier circuits of

    Chapters 29.

    An alternative measure of the amount of distortion is by means of a property

    known as the total harmonic distortion (THD), which is defined as

    THDV V

    V

    V

    V

    AN AN

    AN

    AN

    AN

    h=

    =2 2

    2

    1

    1 1 (10.25)

    Copyright 2004 by Marcel Dekker, Inc. All Rights Reserved.

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    Chapter 6

    Digitally Controlled DC/ACInverters

    As described in Chapter 3, all DC/AC pulse-width-modulation (PWM) inverters aretreated as a first-orde -hold (FOH) element in digital control systems. We will discuss

    this model in various circuits in this Chapter.

    6.1 INTRODUCTION

    DC/AC inverters are a newly developed group of the power switching circuits applied

    in industrial applications in comparison with other power switching circuits. Althoughchoppers were popular in DC/AC power supply long time ago, power DC/AC invert-

    ers were used in industrial application since later 1980s. Semiconductor manufacture

    development brought power devices, such as gate turn-off thyristor,Triac, bipolar tran-

    sistor, insulated gate bipolar transistor and metal-oxide semiconductor fiel effected

    transistor (GTO, Triac, BT, IGBT, MOSFET, respectively) and so on, in higher switch-

    ing frequency (say from thousands Hz upon few MHz) into the DC/AC power supply

    since 1980s. Due to the devices such as thyristor (silicon controlled rectifie , SCR)

    with low switching frequency, the corresponding equipment is low power rate.Square-waveform DC/AC inverters were used in early ages before 1980s. In those

    equipment thyristors, GTOsandTriacscouldbeused in low-frequency switching opera-

    tion. High-frequency/high-power devices such as power BTs andIGBTs wereproduced

    in the 1980s. The corresponding equipment implementing the PWM technique has

    large range of the output voltage and frequency, and low total harmonic distortion

    (THD). Nowadays, most DC/AC inverters are DC/AC PWM inverters in different

    prototypes.

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    Digitally controlled DC/AC inverters 163

    DC/AC inverters areused for inverting DCpowersource intoAC power applications.

    They are generally used in following applications:

    1. Variable voltage/frequency AC supplies in adjustable speed drives (ASDs), suchas induction motor drives, synchronous machine drives and so on.

    2. Constant regulated voltage AC power supplies, such as uninterruptible power

    supplies (UPSs).

    3. Static var compensations.

    4. Active filters

    5. Flexible AC transmission systems (FACTSs).

    6. Voltage compensations.

    Adjustable speed induction motor drive systems are widely applied in industrial

    applications.These systemsrequestedtheDC/AC powersupply with variable frequency

    usually from 0 to 400 Hz in fractional horsepower (HP) to hundreds of HP. A large

    number of the DC/AC inverters were in the world market. The typical block circuit is

    shown in Figure 6.1.

    From this block diagram we can see that the power DC/AC inverter produces

    variable frequency and voltage to implement the ASD.

    The power devices used for ASD can be thyristors, Triacs and GTOs in the 1970s

    and early 1980s. Power IGBT was popular in the 1990s, and greatly changed the

    manufacturing of DC/AC inverters. The DC/AC power supply equipment is totally

    changed. The corresponding control circuit is gradually changed from analog control

    to digital control system since late 1980s. The mathematical modeling for all AC/DC

    rectifier is well discussed widely in worldwide. Finally, an FOH is generally accepted

    to be used for simulation of all DC/AC inverters.

    The generally used DC/AC inverters are introduced below:

    1. Single-phase half-bridge voltage source inverter (VSI)2. Single-phase full-bridge VSI

    3. Three-phase full-bridge VSI

    4. Three-phase full-bridge current source inverter (CSI)

    5. Multistage PWM inverters

    Vi

    C

    Rectifier Inverter

    DC link

    ASD

    IM

    Figure 6.1 A standard ASD scheme.

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    164 Digital power electronics and applications

    6. Multilevel PWM inverters

    7. Soft-switching inverters.

    As mentioned in Chapter 3, we list some parameters as follows:

    The modulation index ma (also known as the amplitude-modulation ratio in

    Chapter 3):

    ma =VC

    V(6.1)

    where VC is the amplitude of the control or the preliminary reference signal, and

    V is the amplitude of the triangle signal. Generally, linear-modulation operation

    is considered, so that ma is usually smaller than unity (e.g. ma = 0.8). The normalized carrier frequency index mf (also known as the frequency-

    modulation ratio in Chapter 3):

    mf =f

    fC(6.2)

    where f is the frequency of the triangle signal, and fC is the frequency of the

    control signal or the preliminary reference signal. Generally, in order to obtain

    low THD, the mf has usually taken large number (e.g. mf= 9).

    In order to wellunderstand each inverter, we have shown some typical circuits below.

    6.1.1 Single-Phase Half-Bridge VSI

    A single-phase half-bridge VSI is shown in Figure 6.2. The carrier-based PWM tech-

    nique is applied in this single-phase half-bridge VSI. Two large capacitors are required

    to provide a neutral point N, therefore, each capacitor keep the half of the input DCvoltage. Two switches S+ and S are switched by the PWM signal.

    Figure 6.3 shows the ideal waveforms associated with the half-bridge VSI. We can

    fin out the output of the phase delayed between the output current and voltage.

    Vi

    S

    S D

    Vi/2

    Vi/2

    N

    iiD

    aIO

    VO_

    C

    C

    Figure 6.2 Single-phase half-bridge VSI.

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    Digitally controlled DC/AC inverters 165

    VC

    90180 270 360

    V

    vt

    (a)

    vt

    90 180 270 3600

    on

    (b)

    S

    vt

    90 180 270 3600

    on

    (c)

    S

    vt

    1800 90 270 360

    VO1

    VO Vi/2

    (d)

    vt

    iO

    900 270 360

    iO1

    180

    (e)

    Figure 6.3 Ideal waveforms associated with the single-phase half-bridge VSI (ma = 0.8,

    mf= 9). (a) Carrier and modulating signals, (b) switch S+ state, (c) switch S state, (d) AC

    output voltage and (e) AC output current.

    6.1.2 Single-Phase Full-Bridge VSI

    A single-phase full-bridge VSI is shown in Figure 6.4.

    The carrier-based PWM technique is applied in this single-phase full-bridge VSI.

    Two large capacitors may be used to provide a neutral point N, therefore, each capacitor

    keep the half of the input DC voltage. Four switches S1+ and S1plus S2+ and S2

    are applied and switched by the PWM signal. Figure 6.5 shows the ideal waveforms

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    166 Digital power electronics and applications

    Vi

    S1

    S1 D1

    Vi/2

    Vi/2

    N

    iiD1

    S2 D2

    D2

    a

    b

    iO

    VO

    S2

    Figure 6.4 Single-phase full-bridge VSI.

    VC

    90 180 270 360

    V

    (a)

    vt

    90 180(b) 270 3600

    onS1

    vt

    (c) 90 180 270 3600

    onS2

    vt

    (d)

    1800 90 270

    VO1

    VOVi

    360

    vt

    (e)

    iO

    900

    270 360180

    vt

    Figure 6.5 Ideal waveforms associated with the full-bridge VSI (ma = 0.8, mf= 8). (a) Carrier

    and modulating signals, (b) switch S1+ and S1 state, (c) switch S2+ and S2 state, (d) AC

    output voltage and (e) AC output current.

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    Digitally controlled DC/AC inverters 167

    Vi

    S1

    S4 D4

    Vi/2

    Vi/2

    N

    iiD1 S3

    S6 D6

    D3 S5

    S2 D2

    D5

    a

    b

    c

    ioa

    Vab

    Figure 6.6 Three-phase full-bridge VSI.

    associated with the full-bridge VSI. We can fin out the output of the phase delayed

    between the output current and voltage.

    6.1.3 Three-Phase Full-Bridge VSI

    A three-phase full-bridge VSI is shown in Figure 6.6.The carrier-based PWM technique is applied in this single-phase full-bridge VSI.

    Two large capacitors may be used to provide a neutral point N, therefore, each capacitor

    keep the half of the input DC voltage. Six switches S1S6 are applied and switched by

    the PWM signal. Figure 6.7 shows the ideal waveforms associated with the full-bridge

    VSI. We can fin out the output of the phase delayed between the output current and

    voltage.

    6.1.4 Three-Phase Full-Bridge CSI

    A three-phase full-bridge CSI is shown in Figure 6.8.

    The carrier-based PWM technique is applied in this single-phase full-bridge CSI.

    The main objective of these static power converters is to produce AC output current

    waveforms from a DC current power supply. Six switches S1S6 are applied and

    switched by the PWM signal. Figure 6.9 shows the ideal waveforms associated with

    the full-bridge CSI.We can fin out the output of the phase ahead between the outputvoltage and current.

    6.1.5 Multistage PWM Inverter

    Multistage PWM inverter consists of many cells. Each cell can be a single- or three-

    phase input plus single-phase output VSI, which is shown in Figure 6.10. If the

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    168 Digital power electronics and applications

    90(b) 180 270 3600

    onS1

    vt

    Vca Vcb

    90 180 270 360

    V

    Vcc

    (a)

    vt

    (c)

    S3

    0 90 270 360180

    on

    vt

    (d)

    1800 90 270 360

    Vab1Vab Vi

    vt

    (e)

    ioa

    900 270 360180

    vt

    Figure 6.7 Ideal waveforms associatedwith the three-phase full-bridgeVSI (ma = 0.8, mf= 9).

    (a) Carrier and modulating signals, (b) switchS1+ state, (c) switch S3 state, (d)AC outputvoltage

    and (e) AC output current.

    Vi

    S4

    D4

    iI

    D1

    S3

    S6

    D6

    D3

    S5

    S2

    D2

    D5

    ab

    c

    ioa

    Vab

    S1

    C C C

    Figure 6.8 Three-phase full-bridge CSI.

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    Digitally controlled DC/AC inverters 169

    ica

    i

    icb icc

    (a)

    90 180 270 3600

    onS1

    (b)

    0 90 270 360180

    onS3

    (c)

    1800 90 270 360

    ioa1ioa ii

    (d)

    vab

    900 270 360180

    vab1

    (e)

    t

    t

    t

    t

    t

    90 180 270 360

    Figure 6.9 Ideal waveformsassociatedwith the three-phase full-bridge CSI (ma= 0.8, m

    f= 9).

    (a)Carrier and modulating signals, (b) switchS1+ state, (c) switch S3 state, (d)AC output current

    and (e) AC output voltage.

    D4 D6 D2

    D5 S1

    S1D1

    D1S2

    S2 D2

    D2

    a

    b

    iO

    VO

    N

    ii

    Vi/2

    Vi/2

    C

    C

    L

    D1 D3

    isa

    Figure 6.10 Three-phase input plus single-phase output VSI.

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    170 Digital power electronics and applications

    C13

    C12

    C11

    C23

    C22

    C21

    C33

    C32

    C31

    IM

    VO11

    VO21

    VO31

    isa

    Multicellarrangement

    MultipulsetransformerAC

    mains

    isaVsa

    3

    n

    Figure 6.11 Multistage converter based on a multicell arrangement.

    three-phase AC supply is a secondary winding of a main transformer, it is floatin

    and isolated from other cells and common ground point. Therefore, all cells can be

    linked in series or parallel manner.

    A three-stage PWM inverter is shown in Figure 6.11. Each phase consist of three

    cells with difference phase-angle shift by 20 each other.

    The carrier-based PWM technique is applied in this three-phase multistage PWM

    inverter. Figure 6.12 shows the ideal waveforms associated with the full-bridge VSI.

    We can fin out the output of the phase delayed between the output current and voltage.

    6.1.6 Multilevel PWM Inverter

    A three-level PWM inverter is shown in Figure 6.13. The carrier-based PWM technique

    is applied in this multilevel PWM inverter. Figure 6.14 shows the ideal waveforms

    associated with the multilevel PWM inverter. We can fin out the output of the phase

    delayed between the output current and voltage.

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    Digitally controlled DC/AC inverters 171

    Vca Vca

    90 180 270 360

    (a)

    V1

    v

    t

    V2 V3

    0

    (b)

    vt

    90 180 270

    360

    ViVO211

    VO21

    0

    (c)

    vt

    VO111VO11

    90 180 270 3600

    (d)

    vt

    Vi

    Vi

    VO311

    VO31

    90 180 270 360

    0

    (e)

    vt

    90 360180 270

    3ViVaN

    0

    Figure 6.12 Ideal waveforms associated with the multicell PWM inverter (three stages,

    ma = 0.8, mf= 6). (a) Carrier and modulating signals, (b) cell c11 AC output voltage, (c) cell c21AC output voltage, (d) cell c31 AC output voltage and (e) phase a load voltage.

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    172 Digital power electronics and applications

    S5a D5a

    S1b

    S4aD

    4a

    D1b

    S3b

    S6a

    D6a

    D3b

    S5b

    S2a D2a

    D5b

    a

    b

    c

    ioa

    S2b D2bS6b

    D6b

    S3a D3aS1a D1a

    S4b D4b

    Dc

    DcDb

    Db

    Da

    Da

    Vi/2

    Vi/2

    C

    C

    VabN

    ii

    Figure 6.13 Three-phase three-level PWM VSI.

    = 1/f

    =L/

    iO-k

    = iO-(k

    1)

    (1 et/

    iO-(k

    =

    +