Chapter Four Combinational Logic 1
Chapter Four Combinational Logic 1. Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is.
Jan 21, 2016
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Chapter FourCombinational Logic
1
Discrete quantities of information are represented in digital systems by binary codes.
A binary code of n bits is capable of representing up to 2n distinct elements of coded information.
DECODERS A decoder is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique output lines.
If the n-bit coded information has unused combinations, the decoder may have fewer than 2n outputs.
2
DECODERS
Extract “Information” from the code n-to-m line decoder ( n inputs, m<= 2n output) Binary Decoder
Example: 2-bit Binary Number
BinaryDecoder
x1
x0
Only one lamp will turn on
0
0
1000
3
DECODERS
2-to-4 Line Decoder
I1 I0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
I1I0
Y3
Y2
Y1
Y0
013 IIY 012 IIY
011 IIY 010 IIY
Bin
ary
Dec
oder I1
I0
Y0
Y1
Y2
Y3
21
20
4
DECODERS 3-to-8 Line Decoder (Binary to Octal
conversion)B
inar
yD
ecod
er
xyz
D0
D1
D2
D3
D4
D5
D6
D7
22
21
20
5
6
DECODERS
“Enable” Control
Bin
ary
Dec
oder21
20
E
Y0
Y1
Y2
Y3
E I1 I0 Y0 Y1 Y2 Y3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
EI0
Y3
Y2
Y1
Y0
I1
I1
I0
7
DECODERS
Expansion
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
3 x8 decoder constructed with two 2 x 4 decoders8
94 x16 decoder constructed with two 3 x 8 decoders
DECODERS
Active-High / Active-Low
I1 I0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
I1 I0 Y0 Y1 Y2 Y3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
I1I0
Y3
Y2
Y1
Y0
Bin
ary
Dec
oder I1
I0
Y0
Y1
Y2
Y3
21
20
Bin
ary
Dec
oder I1
I0
Y0
Y1
Y2
Y3
21
20
10
IMPLEMENTATION USING DECODERS Each output is a minterm All minterms are produced Sum the required mintermsExample: Full AdderS(x, y, z) = ∑(1, 2, 4, 7)C(x, y, z) = ∑(3, 5, 6, 7)
x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
11
A function with a long list of minterms requires an OR gate with a large number of inputs.
If the number of minterms in the function is greater than 2n/2, then F’ can be expressed with fewer minterms.
So we use a NOR gate to sum the minterms of F’.
The output of NOR gate complements this sum and generates the normal output F. 12
IMPLEMENTATION USING DECODERS WITH NAND GATES
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryDecoder
xyz
S C
22
21
20
13
ENCODERS (EX. KEYBOARD ENCODER) Perform the inverse operation of a decoder Inputs <= 2n , n outputs Put “Information” into code (it generates the
binary code corresponding to the input value). Binary Encoder
x0 x1 x2 x3 y1 y0
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Only one switch should be activated at a time
BinaryEncoder
y1
y0
x0
x1
x2
x3Example: 4-to-2 Binary Encoder
14
ENCODERS Octal-to-Binary Encoder (8-to-3)
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1
Bin
ary
En
cod
er
Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I1
I0
I7I6I5I4I3I2I1I0
Y2
Y1
Y0
Limitation:1- Only one of the input is allowed to be 12- When all inputs are zeros, the output is
zero but this situation is the same as input Y0=1!!
13570
23671
45672
IIIIY
IIIIY
IIIIY
15
PRIORITY ENCODERS
4-Input Priority Encoder ( V is a valid bit indicator)
Pri
orit
yE
nco
der V
yx
D3
D2
D1
D0
V: is the valid bit indicator that is set to 1 when one or more inputs are equal to 1.
16
17
1
18
ENCODER / DECODER PAIRS
Y2
Y1
Y0
I7
I6
I5
I4
I3
I2
I1
I0
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
BinaryEncoder
BinaryDecoder
19
MULTIPLEXERS (DATA SELECTOR) It Selects binary information from one of many input lines and directs it to a single output line. (Ex. single data bus is required to carry two or more different digital signals)(2n input lines and n selection lines)
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MUX Y
I0
I1
I2
I3 S1 S0
01
23
20
21
2-to-1 MUX
MULTIPLEXERS
4-to-1 MUX
I1
I0
S1
YI2
I3
S0
MUX Y
I0
I1
I2
I3
S1 S0
01
23
22
MULTIPLEXERS
Quad 2-to-1 MUX
A0
A1
A2
A3
B0
B1
B2
B3
MUX Y001 S
MUX Y101 S
MUX Y201 S
MUX Y301 S
S
MUX
A0
A1
A2
A3
S E
Y0
Y1
Y2
Y3
B0
B1
B2
B3
(two 4-bits input, one 4-bits output)23
24
IMPLEMENTATION USING MULTIPLEXERS
MUX Y
01
23 S1 S0
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Any Boolean function of n-variables can be implemented using a MUX with n-1 selection lines
ExampleF(x, y, z) = ∑(1, 2, 6, 7)
x y
FF = zz
F = z
z
F = 0
0
F = 1
1
25
MUX Y
01
23 45
67
S2 S1 S0
IMPLEMENTATION USING MULTIPLEXERS
A B C D F0 0 0 0 00 0 0 1 10 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1
ExampleF(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C
F
F = DD
F = DD
F = D
D
F = 0
0
F = 0
F = D
F = 1
F = 1
0
D
1
1
26
Y
I0
I1
I2
I3
I4
I5
I6
I7
S2 S1 S0
MULTIPLEXER EXPANSION
8-to-1 MUX using Dual 4-to-1 MUX & one 2x1 Mux
MUX Y
01
23 S1 S0
MUX Y
01
23 S1 S0
MUX Y01
S
0 0127
28
/ 65
DEMULTIPLEXERS A circuit that receives information from a single line and directs it to one of 2n possible output lines
DeMUXI
Y3
Y2
Y1
Y0
S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
I
Y3
Y2
Y1
Y0
S0S1
DEMULTIPLEXERS / DECODERS
Bin
ary
Dec
oder I1
I0
E
Y0
Y1
Y2
Y3
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
DeMUXI
Y0
Y1
Y2
Y3
S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 029
30
THE PROBLEMS:
4.1, 4.2, 4.4, 4.13, 4.21, 4.23, 4.25, 4.27, 4.31, 4.33, 4.34, 4.35(a)
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