Chapter Five

Chapter Five

The Field-Effect Transistor

Figure 6—2A three-terminal nonlinear device that can be controlled by the voltage at the third terminal vG: (a) biasing circuit; (b) I–V characteristic and load line. If vG = 0.5 V, the d-c values of ID and VD are as shown by the dashed lines.

Figure 6—3Simplified cross-sectional view of a junction FET: (a) transistor geometry; (b) detail of the channel and voltage variation along the channel with VG = 0 and small ID.

Figure 6—4Depletion regions in the channel of a JFET with zero gate bias for several values of VD : (a) linear range; (b) near pinch-off; (c) beyond pinch-off.

Figure 6—5Effects of a negative gate bias: (a) increase of depletion region widths with VG negative; (b) family of current–voltage curves for the channels as VG is varied.

Figure 6—11n-channel MOSFET cross-sections under different operating conditions: (a) linear region for VG > VT and VD < (VG 2 VT); (b) onset of saturation at pinch-off, VG > VT and VD = (VG 2 VT); (c) strong saturation, VG > VT and VD > (VG 2 VT ).

Figure 6—27Drain current–voltage characteristics for enhancement transistors: (a) for n-channel VD, VG, VT, and ID are positive; (b) for p-channel all these quantities are negative.

Figure 6—28Linear region transfer characteristics: (a) plot of drain current versus gate voltage for MOSFETs in the linear region; (b) transconductance as a function of gate bias.

Figure 6—29Saturation region transfer characteristics: plot of square root of the drain current versus gate voltage for MOSFETs.

Figure 6—39Equivalent circuit of a MOSFET, showing the passive capacitive and resistive components. The gate capacitance Ci is the sum of the distributed capacitances from the gate to the source-end of the channel (CGS) and the drain-end (CGD). In addition, we have an overlap capacitance (where the gate electrode overlaps the source/drain junctions) from the gate-to-source (COS) and gate-to-drain (COD). COD is also known as the Miller overlap capacitance. We also have p-n junction depletion capacitances associated with the source (CJS) and drain (CJD). The parasitic resistances include the source/drain series resistances (RS and RD), and the resistances in the substrate between the bulk contact and the source and drain (RBS and RBD). The drain current can be modeled as a (gate) voltage-controlled constant-current source.

Figure 5.24(a) An NMOS common-source circuit and (b) the NMOS circuit for Example 5.3

Figure 5.25(a) A PMOS common-source circuit, (b) results when saturation-region bias assumption is incorrect, and (c) results when nonsaturation-region bias assumption is correct

Figure 5.28Transistor characteristics, vDS (sat) curve, load line, and Q-point for the NMOS common-course circuit in Figure 5.24 (b)

Figure 5.29NMOS common-source circuit with source resistor

Figure 5.35Circuit with enhancement load devices and NMOS driver

Figure 5.36Voltage transfer characteristics of NMOS inverter with enhancement load device

Figure 5.37(a) Depletion-mode NMOS device with the gate connected to the source and (b) current-voltage characteristics

Figure 5.39Circuit with depletion load device and NMOS driver

Figure 5.40Voltage transfer characteristics of NMOS inverter with depletion load device

Figure 5.47(a) An NMOS common-source circuit with a time-varying signal coupled to the gate and (b) transistor characteristics, load line, and superimposed sinusoidal signals

Chapter Six

Basic FET Amplifiers

Figure 6.13Common-source circuit with voltage divider biasing and coupling capacitor

Figure 6.14Small-signal equivalent circuit, assuming coupling capacitor acts as a short circuit

Figure 6.17

DC load line and transition point for NMOS circuit shown in Figure 6.16

Figure 6.19Small-signal equivalent circuit of NMOS common-source amplifier with source resistor

Figure 6.28NMOS source-follower or common-drain amplifier

Figure 6.29(a) Small-signal equivalent circuit of NMOS source-follower and (b) small-signal equivalent circuit of NMOS source-follower with all signal grounds at a common point

Figure 6.34

Common-gate circuit

Figure 6.35

Small-signal equivalent circuit of common-gate amplifier

Figure 6.39(a) NMOS amplifier with enhancement load device; (b) driver transistor characteristics and enhancement load curve with transition point

Figure 6.39cVoltage transfer characteristics of NMOS amplifier with enhancement load device

Figure 6.43(a) NMOS amplifier with depletion load device; (b) driver transistor characteristics and depletion load curve, with transition points

Figure 6.43c(c) voltage transfer characteristics

Figure 6.45(a) CMOS common-source amplifier; (b) PMOS active load i-v characteristic, (c) driver transistor characteristics with load curve, (d) voltage transfer characteristics

Figure 6.50 NMOS cascode circuit

Figure 6.52Small-signal equivalent circuit of NMOS cascode circuit