7. Storage Components 7-1 Chapter 7. Storage Components Introduction St ora ge components store data and perform simpledata transforma tio ns, suc h as counting and shifting. Registers, counters, register files, memories, etc. Register: a group of binary cells (FFs) suitable for holding binary informa- tion. In addition to the FFs, a regi ster may have combi nationa l gates that con- trol when and how new informa tion is transfe rred into the register . Counter: a re gis ter t hat goes through a predetermined sequence of sta tes upon the application of input pulses. The gates in a counter are connected in such a way as to produce a pre- scribed sequence of binary states in the register. Memory unit : a collection of storage cells togethe r with associated circuits needed to transfer information in and out of storage. For example, SRAM & DRAM. Registers A register can be vie wed as a bitwise extensio n of a FF . The simplest of the storage components: inputs, outputs , and aclocksignal. c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
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All the FFs are driven by the common clock signal.
Registers are readily available as MSI circuits, it becomes convenient at timesto employ a register as part of the sequential circuit. The combinational-
circuit part of the sequential circuit can be implemented by any of the meth-ods discussed in Chapters 4 & 5.
D-FFs are normally used for registers.
The register may be enhanced by asynchronous Preset and Clear (Reset) sig-nals, which are not controlled by the clock signal.
Q Q Q Q 0
Register 0 I I I I
123
3 2 1
(a) Graphic symbol
(b) Register schematic
I 3
Q3
Q3
3 D
I
Q
Q
I
Q
Q
I
Q
Q
D
Clk
2 1 0
00
01
D1 12 D2
2
Figure 1: A 4-bit register [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
To be able to control when the data will be entered into a register, and forhow long it will be stored there before being sent to the output, we add theLoad (Enable) input to form a parallel-load register .
Q3
3
3 D Q Q D Q D
Clk
I
Selector
1 0
I
Selector
1 0
I
Selector
1 0
I
Selector
1 0
Load
3 2 1 0
D 2 2 1 1 0 0
Y Y Y 01Y 2
(a) Graphic symbol
Q Q Q Q 0
Register 0 I I I I 123
3 2 1
Load
(b) Operation table
Present state Load
Next state
Q3 Q Q Q2 1 0
3 2 1 0 I I I I
No change0
1
(c) Register schematic
Figure 3: Register with parallel load [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
input datalines, and output data lines (see Fig. 12).
The input data lines can be the same with the output data lines, i.e., thedata lines can be bidirectional.
For a commodity RAM, , and = 1, 4, 8, 16, 0r 32.
A memory cell (MC) can be considered as a clocked D latch with an ANDgate and an output driver (see Fig. 13(a)).
For a static RAM (SRAM) , MC is constructed by 6 transistors, usingcross-coupled inverters to serve as a latch, and implementing the inputAND gate and the output driver with one transistor each.
For a dynamic RAM (DRAM) , MC is constructed by only 1 transistor.
The latch is implemented by a capacitor. It needs to be refreshed periodically. It has high density (therefore low cost).
The RAM also has a Chip-Select (
) input and a Read/Write Select (
)input (see Fig. 13(b)).
The input sometimes is denoted as
.
Both SRAM and DRAM are volatile memories , i.e., their content is lost if the power is shut down.
ROM, PROM, EPROM, EEPROM, and ash memories are nonvolatile .
The delay time from address input to data output (
in Fig. 14) is thememory access time .
The address/data setup time and hold time are shown in Fig. 14.
We can connect several memory chips to get one of longer words (Fig. 15),or connect several memory chips to get one with more words (Fig. 16).
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
A push-down stack (or simply stack ) is a memory component with limitedaccess—data can be accessed through only one location (i.e., the top of thestack).
When data is to be stored, it is pushed on the stack and stays on top of others.
When data is to be fetched, it has to be in the top position before it canbe popped out of the stack.
A stack can be implemented by shift registers, with an up-down counter todetect full/empty stack as shown in Fig. 18.
It can also be implemented by a RAM—less expensive for a large stack, butneed two pointers (implemented by counters) as shown in Fig. 19.
TopTop − 1
Top − 2
Top − 3
34 23
empty
empty
34 23
empty
empty
45 34
23
empty
(a) Stack content
before 45 ispushed down
45 45
(b) Stack content
after 45 ispushed down
(c) Stack content
after 45 ispopped up
Figure 17: Push-down stack operations [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
A rst-in-rst-out (FIFO) queue (or simply queue or FIFO ) is a memory com-ponent with limited access—data can be written through only the head (front)of the queue and read (and removed) through only the tail (back) of the queue.
A queue can be implemented by shift registers, with an up-down counter todetect full/empty queue as shown in Fig. 21.
It can also be implemented by a RAM—less expensive for a large queue, butneed two pointers (implemented by counters) as shown in Fig. 22.
Top
Top − 1
Top − 2
Top − 3
empty
empty
34
23
empty
45
34
23
empty
empty
45
34
23
45
(a) Queue content before 45 is stored
(b) Queue content after 45 is stored
(c) Queue content after 23 is read
Figure 20: FIFO queue operations [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
Datapaths are used in all standard CPU and ASIC implementations to per-form complex numerical computation or data manipulations; a datapath con-sists of temporary storage in addition to arithmetic, logic, and shift units.
Example 1Assume we want to perform the summation of 100 numbers:
Wecan use the datapath as shown in Fig. 23 to implement the following algorithm:
sum=0;for(i=1; i<=100; i++)
sum=sum+x[i];
(b) Control word
(a) Datapath schematic
Selector 1 0
S
ALU
A B M S
S 01
01S
S
Clk Accumulator
Input O
I R I L
8 7 6 5 4 3 2 1 0 Input select
Accumulator controls
ALU controls
Shift values
Out enable
8
76
5
43
21
0
Figure 23: Simple datapath with one accumulator [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005