Chapter 5

© Digital Integrated Circuits2nd Inverter

Digital Integrated

CircuitsA Design Perspective

The Inverter


The CMOS Inverter: Switch models

Vin Vout

CL

VDD VDD VDD

0

VoutVout

Rn

Rp

VOL = 0

VOH = VDD

VM = f(Rn, Rp)


Important Properties of CMOS

Invertor is ratioless, because output voltage

level is not dependent on the device size.

Low output impedance: there always a path

between output and VDD or GND.

Input gate resistance is extremely high. A

single invertor can (theoretically) drive infinite

invertors.

In steady state, no direct path exists between

VDD and GND.


Voltage Transfer

Characteristic


PMOS Load Lines

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDn

Vin=0

Vin=1.5

Vout

IDn

Vin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDn

Vin = VDD+VGSp

IDn = - IDp

Vout = VDD+VDSp


CMOS Inverter Load Line Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS


CMOS Inverter VTC

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.5

22.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

VTC exhibits very narrow

transition zone. This results

from high gain when both

NMOS and PMOS are in

Saturation mode.

High gain means a small

change in the input results

in large output variation.


Switching Threshold as a function of

Transistor Ratio

The switching threshold (VM ) is defined

as the point where Vin = Vout

Both PMOS and NMOS are in

Saturation (and velocity saturated)


Switching Threshold as a function

of Transistor Ratio For identical oxide thickness for NMOS and MOS

VM r VDD / (1+r)

This means VM is set by r, which compares the driving

strength of PMOS and NMOS

It is desirable ( for noise margin) to have VM in the

middle of VDD, where r=1

The ratio PMOS to NMOS sizes for desired VM:

)2/('

)2/('

)/(

)/(

DSATpTpMDDDSATpp

DSATnTnMDSATnn

n

p

VVVVVk

VVVVk

LW

LW


Switching Threshold as a function of Transistor Ratio

If devices are long-channel or VDD is

low, then velocity saturation does not

occur. Under these conditions VM can

be expressed as:

n

p

TpDDTn

M

k

kr

r

VVrVV

1

)(


Switching Threshold as a function of

Transistor Ratio

100

101

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV

(V)

Wp/Wn

Calculated VM is at sizes

of NMOS and PMOS:

(W/L)p/(W/L)n = 3.5

Simulated VM is at ration

of 3.4

Note:

-VM is relatively insensitive

to device variations.

-Effect of changing the

device sizes is to shift the

VTC.


Determining VIH and VIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simpler approach for calculating

noise margins is to use piece-wise

linear approximation approach.

g: gain at the switching threshold

VM . g is negative.

High gain increases

noise margins, and

therefore desirable.


Inverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin

(V)

gain


Robustness: Impact of Process Variations

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vo

ut(V

)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal

Manufacturing causes

devices to deviate from

ideal behavior.

The variation causes shift

in the switching threshold.

But it does not affect the

device operation.


Robustness: Gain as a function of VDD

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin

(V)

Vout (

V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vout(V

)

Reducing power supply improves gain, but it deteriorates

for very low supply voltage. The minimum voltage is:

VDDmin = 2..4 kT/q = 50-100mV

However, reducing power supply increases gate delay.


Propagation Delay

16


CMOS Inverter: Transient Response

tpHL = f(Ron.CL)

= 0.69 RonCL

VoutVout

Rn

Rp

VDDVDD

Vin VDDVin 0

(a) Low-to-high (b) High-to-low

CLCL


CMOS Inverter: Transient Response (2)

CL consists of:

Overlap gate-drain capacitance of driving gate

(~0.31 fF/m)

– Causes glitch in the output before switching

Diffusion capacitance of driving gate

– Bottom junction capacitance: (2 fF/m2)

– Sidewall junction capacitance: (~0.25 fF/m)

Gate capacitance of fanout gates (6 fF/m2)

Wire capacitance


Inverter Propagation Delay Propagation delay is proportional to the time-constant of the network

formed by the pull-down resistor and the load capacitance

tpHL = ln(2) Reqn CL = 0.69 Reqn CL

tpLH = ln(2) Reqp CL = 0.69 Reqp CL

tp = (tpHL + tpLH)/2 = 0.69 CL(Reqn + Reqp)/2

To equalize rise and fall times make the on-resistance of the NMOS

and PMOS approximately equal.

VDD

Rn

Vout = 0

Vin = V DD

CL

tpHL = f(Rn, CL)

19

Inverter Transient Response

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

t (sec) x 10-10

VDD=2.5V

0.25m

W/Ln = 1.5

W/Lp = 4.5

Reqn= 13 k ( 1.5)

Reqp= 31 k ( 4.5)

tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

tf trtpHL tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec 20

What are those overshoots (next page)


The overshoots

The overshoots are

caused by gate-drain

capacitance of the

inverter transistors.

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5


Propagation Delay vs. Power Supply

Combining earlier equations:

For VDD>> VTn + VDSATn

Increasing VDD results in

reducing delay. Simulation

results (as shown) confirms

analytical results.


Reducing Propagation Delay Delay CL / (W/Ln k’n VDSATn )

Reduce CL

internal diffusion capacitance of the gate itself

– keep the drain diffusion as small as possible

interconnect capacitance

fanout

Increase W/L ratio of the transistor

the most powerful and effective performance optimization

tool in the hands of the designer

watch out for self-loading! – when the intrinsic capacitance

dominates the extrinsic load

Increase VDD

can trade-off energy for performance

increasing VDD above a certain level yields only very minimal

improvements

reliability concerns enforce a firm upper bound on VDD23


Inverter Propagation Delay, Revisited To see how a designer can optimize the delay of a gate

have to expand the Req in the delay equation

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4VDD (V)

tpHL = 0.69 Reqn CL

= 0.69 (3/4 (CL VDD)/IDSATn )

0.52 CL / (W/Ln k’n VDSATn )

24


Inverter Sizing

25


Propagation Delay Issues

Design consideration and trade-offs

1. NMOS-to-PMOS Ratio

2. Sizing Inverters for Performance

3. Sizing a Chain of Inverters

4. Choosing the Right Number of Stages in

an Inverter Chain

5. The Rise-Fall of Input Signal

6. Delay with long interconnects


1. NMOS/PMOS Ratio

Widening the PMOS degrades the tpHL due to larger

parasitic capacitance

If speed is the only concern, reduce the width of the

PMOS device! See next slide

For equal rise and fall time: the PMOS and NMOS are sized so that the Req’s match (ratio of 3 to 3.5)

symmetrical VTC

equal high-to-low and low-to-high propagation delays

Does not lead to minimum overall delay

27


1. NMOS/PMOS Ratio: Optimum Ration

Reqp and Reqn : Ration of identically-sized PMOS and NMOS.

For our process, r=31K/13K = 2.4

For C w << C dn1 + C gn2

This is in contrast with ration of r.

PMOS/NMOS Ratio Effects

3

3.5

4

4.5

5

1 2 3 4 5

= (W/Lp)/(W/Ln)

x 10-11

of 2.4 (= 31 k/13 k)

gives symmetrical

response

Previous equation

predicts opt to be 1.6

From simulation, opt is

around 1.9! (close to our

analytical results.)

tpLH

tp

tpHL

29


2. Device Sizing for Performance Divide capacitive load, CL, into

Cint : intrinsic - diffusion and Miller effect (drain-gate overlap cap)

Cext : extrinsic - wiring and fanout

where tp0 = 0.69 Req Cint is the unloaded (intrinsic) delay of the gate

Widening both PMOS and NMOS by a factor S reduces Req by an identical factor (Req = Rref/S), but raises the intrinsic capacitance by the same factor (Cint = SCiref)

tp0 is independent of the sizing of the gate

any S sufficiently larger than (Cext/Cint) yields the best performance gains with least area impact. Yet, any sizing factor S that is sufficiently larger than (Cext/Cint) produces similar results at a substantial gain in silicon area

30

Sizing Impacts on Delay: Example

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1 3 5 7 9 11 13 15

S

x 10-11 From example 5.5,

Cext/Cint = 3.15ff/3.0ff

1.05

The majority of the

improvement is already

obtained for S = 5. Sizing

factors larger than 10

barely yield any extra gain

(and cost significantly

more area).

for a fixed load

self-loading effect

(intrinsic capacitance

dominates)31


3. Sizing a Chain of Inverters

Sizing up transistor reduces its delay, but it increases

the Cext of the preceding gate.

Therefore, it is important to determine the optimum size

for inverters embedded in (for example) a chain of

inverters.

First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing:

• Cint = Cg So is independent of gate sizing (almost equal to 1)

• Define Effective Fanout (f ) = Cext/Cg

• tp = tp0 (1 + Cext/Cint)

= tp0 (1 + Cext/ Cg)

= tp0 (1 + f/)

• The delay of an inverter is a function of f. 32


Inverter Chain

If CL is given

How should the inverters be sized?

How many stages are needed to minimize the delay?

– May need some additional constraints.

Real goal is to minimize the delay through an inverter chain

the delay of the j-th inverter stage and the total delay are:

33


Sizing the Inverters in the Chain The optimum size of each inverter is the geometric mean

of its neighbors – meaning that if each inverter is sized up

by the same factor f wrt the preceding gate, it will have

the same effective fan-out and the same delay

where F represents the overall effective fan-out of the circuit

(F = CL/Cg,1)

and the minimum delay through the inverter chain is:

The relationship between tp and F is linear for one

inverter, square root for two, etc.

34


Example of Inverter Chain Sizing

CL/Cg,1 has to be evenly distributed over N = 3 inverters

CL/Cg,1 = 8/1

f =

In Out

CL = 8 Cg,1Cg,1

Cg= Cg,1 Cg= 2 Cg,1 Cg= 4 Cg,1

38 = 2

36


4. Optimum Number of Stages

Examining the above delay equation reveals the the trade-off’s

in choosing the number of stages (N) for a given F (=fN).

• When the number of stages is too large, the first

component of the equation, representing the intrinsic delay

of the stages, becomes dominant.

• If the number of stages is too small, the effective fanout of

each stage becomes large, and the second component is

dominant.

37


4. Optimum Number of Stages

The optimum value can be found by differentiating

the minimum delay expression by the number of

stages, and setting the result to 0.

ff 1exp

38

0ln/1

/1 N

FFF

NN

This equation only has a closed-form solution for = 0

• = 0 No self-loading (i.e. Cint=0)

•This is when the self-loading is ignored and the load capacitance

only consists of the fanout.

• Under these simplified conditions, it is found that the optimal

number of stages equals N = ln(F), and the effective fanout of

each stage is set to f = 2.71828 = e


Optimum Effective Fanout f: ≈1When self-loading is included,

•The equation can only be

solved numerically.

•The results are plotted below.

• For ≈ 1, fopt = 3.6

39


Optimum Effective Fanout f: ≈1

40

The plots the (normalized)

propagation delay of the inverter

chain as a function of the effective

fanout ≈1 .

• Choosing values of the fanout that are

higher than the optimum does not impact the

delay that much, and reduces the required

number of buffer stages and the

implementation area. A common practice is

to select an optimum fanout of 4.

• The use of too many stages (f < fopt), on the

other hand, has a substantial negative

impact on the delay, and should be avoided.


Example of Inverter Staging ( =1 )

CL = 64 Cg,1Cg,1 = 1

1

CL = 64 Cg,1Cg,1 = 1

1 8

CL = 64 Cg,1Cg,1 = 1

1 4 16

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6

N f

1 64 65

2 8 18

3 4 15

4 2.8 15.3

41

/10N

pp FNtt

topt/tp0 versus x for various driver configurations

Impressive speed-ups with optimized

cascaded inverter chain for very large

capacitive loads.

F ( = 1)

Unbuffered Two Stage Chain

Opt. Inverter Chain

10 11 8.3 8.3

100 101 22 16.5

1,000 1001 65 24.8

10,000 10,001 202 33.1

/10N

pp FNtt

42

Sizing An Inverter Network N=3

CL_total = CL * 16 = 64*16 = 1024

f = (CL_total)1/N = 10.08

The effect gate size of stage2

10.08

The effective gate size of stage2

101.6

However, a stage1 inverter drives 4

stage2 inverters

Cg2 = 10.08/4 = 2.52

Similarly, the size of stage3 inverter

is

Cg3 = 101.6/16 = 6.35

CL = 64 * Cg1


5. Input Signal Rise/Fall Time In reality, the input signal

changes gradually (and both

PMOS and NMOS conduct for a

brief time). This affects the

current available for

charging/discharging CL and

impacts propagation delay.

3.6

3.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

0 2 4 6 8

ts(sec)

x 10-11

x 10-11

for a minimum-size inverter

with a fan-out of a single gate

tp increases linearly with increasing input slope, ts, once ts > tp

ts is due to the limited driving capability of the preceding gate

44


Design Challenge A gate is never designed in isolation: its performance is

affected by both the fan-out and the driving strength of

the gate(s) feeding its inputs.

tip = tistep + ti-1step ( 0.25)

Keep signal rise times smaller than or equal to the gate propagation delays.

good for performance

good for power consumption

Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering.

45


6. Delay with Long Interconnects When gates are farther apart, wire capacitance and

resistance can no longer be ignored.

tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan

where Rdr = (Reqn + Reqp)/2

= 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2

cint

Vin

cfan

(rw, cw, L)Vout

Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires.

46


Power Dissipation


Why Power Matters

Packaging costs

Power supply rail design

Chip and system cooling costs

Noise immunity and system reliability

Battery life (in portable systems)

Environmental concerns

Office equipment accounted for 5% of total US commercial

energy usage in 1993

Drain leakage will increase as VT decreases to maintain noise

margins and meet frequency demands, leading to excessive battery

draining standby power consumption.

48


Why worry about power? -- Power Dissipation

P6Pentium ®

486

386

2868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000

Year

Po

we

r (W

att

s)

Lead microprocessors power continues to increase

Power delivery and dissipation will be prohibitive

Source: Borkar, De Intel49

Chip Power Density Distribution

Power density is not uniformly distributed across the chip

Silicon is not a good heat conductor

Max junction temperature is determined by hot-spots Impact on packaging, w.r.t. cooling

0

50

100

150

200

250

Heat

Flu

x (

W/c

m2)

Willamette Power Distribution

200-250

150-200

100-150

50-100

0-50

Power Map

40

60

80

100

120

Tem

pera

ture

(C

)

Al-SiC+ Epoxy Die Attach

100-120 80-100

60-80 40-60

On-Die Temperature

50


Power and Energy Figures of Merit Power is the rate of consuming energy

It is measured in Watts

power is a rate (e.g. speed)

Peak power

– determines power ground wiring designs

– sets packaging limits

– impacts signal noise margin and reliability analysis

Average Power determines battery life

Energy is a quantity and measured in Joules

Energy = power * time

Joules = Watts * seconds

lower energy number means less power to perform a

computation at the same frequency

51


Power versus Energy

Watts

time

Power is height of curve

Watts

time

Approach 1

Approach 2

Approach 2

Approach 1

Energy is area under curve

Lower power design could simply be slower

Two approaches require the same energy

52


PDP and EDP Power-delay product (PDP) = Pav * tp = (CLVDD

2)/2

PDP is the average energy consumed per switching event

(Watts * sec = Joule)

lower power design could simply be a slower design

allows one to understand tradeoffs better

0

5

10

15

0.5 1 1.5 2 2.5

Vdd (V)

En

erg

y-D

elay (n

orm

alized

)

energy-delay

energy

delay

Energy-delay product (EDP) = PDP * tp = Pav * tp2

EDP is the average energy consumed multiplied by the computation time required

takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)

53


Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

54


Dynamic Power

Energy = Q * VDD = CL * VDD2

Energy/transition =CL * VDD2 * P01

Pdyn = Energy/transition * f = CL * VDD2 * P01 * f

Pdyn = CEFF * VDD2 * f where CEFF = P01 CL

Vin Vout

CL

Vdd

f01

55


Transistor Sizing for Minimum

Energy

Goal: Minimize Energy of whole circuit

Design parameters: f and VDD

tp tpref of ref circuit, i.e. f=1 and VDD =Vref

1Cg1

In

fCext

Out

TEDD

DDp

pp

VV

Vt

f

Fftt

0

0 11

56


Transistor Sizing (2)

Performance Constraint (=1)

Energy for single Transition

1

3

2

3

2

0

0

F

f

Ff

VV

VV

V

V

F

f

Ff

t

t

t

t

TEDD

TEref

ref

DD

refp

p

pref

p

F

Ff

V

V

E

E

FfCVE

ref

DD

ref

gDD

4

22

11

2

1

2

57


1 2 3 4 5 6 70

0.5

1

1.5

2

2.5

3

3.5

4

f

vd

d (

V)

1 2 3 4 5 6 70

0.5

1

1.5

f

no

rma

lize

d e

ne

rgy

Transistor Sizing (3)

F=1

2

5

10

20

VDD=f(f) E/Eref=f(f)

58


Short-Circuit Consumption

(Dissipation due to Direct-Path

Current)

Finite slope of the input signal causes a direct

current path between VDD and GND for a short

period of time during switching when both the

NMOS and PMOS transistors are conducting.

Vin Vout

CL

Isc


Short Circuit Currents Determinates

Duration and slope of the input signal, tsc

tsc (Vdd- 2 Vt)/Vdd x tr/0.8

Ipeak determined by

the saturation current of the P and N transistors which

depend on their sizes, process technology, temperature, etc.

strong function of the ratio between input and output slopes

– a function of CL

Esc = tsc VDD Ipeak P01

Psc = tsc VDD Ipeak f01

60


Impact of CL on Psc

Vin Vout

CL

Isc 0

Vin Vout

CL

Isc Imax

Large capacitive load

Output fall time significantly larger than

input rise time.

Input moves through the transient region

before the output starts to change. As a

result, the PMOS shuts-off before

delivering much current.

Small capacitive load

Output fall time substantially smaller than

the input rise time.

The drain-source voltage of PMOS is equal

to Vdd most of the transient period,

guaranteeing maximum current. 61

Ipeak as a Function of CL

-0.5

0

0.5

1

1.5

2

2.5

0 2 4 6

time (sec)

x 10-10

x 10-4

CL = 20 fF

CL = 100 fF

CL = 500 fF

500 psec input slope

Short circuit dissipation

is minimized by

matching the rise/fall

times of the input and

output signals - slope

engineering.

When load capacitance

is small, Ipeak is large.

62

Psc as a Function of Rise/Fall Times

0

1

2

3

4

5

6

7

8

0 2 4

P(normalized wrt zero input rise-time dissipation)

tsin/tsou

t

VDD= 3.3 V

VDD = 2.5 V

VDD = 1.5V

* tsin/tsou > 2

- Small cap loade

- High Psc

* tsin/tsou < 2

-Large cap loade

-Low Psc

If VDD < VTn + |VTp| then

Psc is eliminated since

both devices are never

on at the same time.

W/Lp = 1.125 m/0.25 m

W/Ln = 0.375 m/0.25 m

CL = 30 fF 63

Leakage (Static) Power Consumption

It is static power dissipation caused by

Pstat = Istat Vdd

Sources of the static current:

1. Reverse-biased diode junction between source/drain and substrate

• Devices with high Vt leaks less.

2. Sub-threshold current: Drain-to-source current when -0<Vgs <Vt.

• Devices with higher threshold has less sub-threshold leakage current.

Choosing the right Vt is trade-off between performance and leakage power


Leakage (Static) Power Consumption

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

VDD Ileakage

Vout

Drain junction

leakage

Sub-threshold currentGate leakage

65

Leakage as a Function of VT

0 0.2 0.4 0.6 0.8 1

VGS (V)

ID (

A)

VT=0.4V

VT=0.1V

10-2

10-12

10-7

Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation.

An 90mV/decade VT

roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)

66

Exponential Increase in Leakage Currents

1

10

100

1000

10000

30 40 50 60 70 80 90 100 110

0.25

0.18

0.13

0.1

Temp(C)

I lea

kag

e(n

A/

m)

From De,1999

67


CMOS Energy & Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage

P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage

Dynamic

power

Short-circuit

power

Leakage

power

f01 = P01 * fclock

68


Power measures and metrics Power-Delay Product:

PDP = Pav tp== CL * VDD2 /2

Measures the average energy per switching event

This metric can be made to “ look good” by lowering Vdd on

the expense of performance.

Energy-Delay Product

EDP = PDP tp * = tp CL * VDD2 /2

In EDP, higher voltage improves performance but hurt energy,

and the opposite is true for low voltage.

The optimum voltage can be obtained by taking the derivative

of EDP with respect to Vdd,

VDDopt = 1.5 * VTE

where VTE = VT + VDSAT/2


Analyzing Power Using Spice

Chapter 5

Documents

vin vvout v0

dsatn nnpv v v v v kv

threshold vm

middle of vdd

ratio pmos

nmos sizes

high b high

voutboth pmos