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EE415 VLSI Design 1
The Wire
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
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EE415 VLSI Design 2
The Wire
transmitters receivers
schematics physical
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EE415 VLSI Design 3
Interconnect Impact on Chip
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EE415 VLSI Design 4
Wire Models
All-inclusive modelCapacitance-only
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EE415 VLSI Design 5
Impact of Interconnect Parasitics
Interconnect parasitics
reduce reliability
affect performance and powerconsumption
Classes of parasitics
Capacitive
Resistive Inductive
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EE415 VLSI Design 6
10 100 1,000 10,000 100,000
Length (u)
No
ofnets
(Log
Scale)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnologySGlobal = SDie
Source:In
tel
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EE415 VLSI Design 7
INTERCONNECT
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EE415 VLSI Design 8
Wiring Capacitance
The wiring capacitance depends upon thelength and width of the connecting wires and isa function of the fan-out from the driving gateand the number of fan-out gates.
Wiring capacitance is growing in importancewith the scaling of technology.
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EE415 VLSI Design 9
Capacitance of Wire Interconnect
VDD VDD
Vin
Vout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
Vout
Vin
CL
Simplified
Model
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EE415 VLSI Design 10
Capacitance: The Parallel Plate Model
Dielectric
Substrate
L
W
H
tdi
Electrical-fie ld lines
Current flow
WLt
c
di
di
int
LL
Cwire
SSS
SS
1
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EE415 VLSI Design 11
Permittivity Values of Some Dielectrics
3.1 3.4Polyimides (organic)
2.1Teflon AF
11.7Silicon
9.5Alumina (package)
7.5Silicon nitride
5Glass epoxy (PCBs)
3.9 4.5Silicon dioxide
2.6 2.8Aromatic thermosets (SiLK)
1.5Acrogels
1Free space
diMaterial
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EE415 VLSI Design 12
Fringing Capacitance
W - H/2H
+
(a)
(b)
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EE415 VLSI Design 13
Fringing versus Parallel Plate
(from [Bakoglu89])
H/T
H/T
W/T
HT
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EE415 VLSI Design 14
Sources of Interwire Capacitance
Cwire = Cpp+ Cfringe+ Cinterwire= (di/tdi)WL
+ (2di)/log(tdi/H)+ (di/tdi)HL
interwire
fringe
pp
W W
W
H
H
H
tdi
tdi
tdi
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EE415 VLSI Design 15
Impact of Interwire Capacitance
(from [Bakoglu89])
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EE415 VLSI Design 16
Wiring CapacitancesField Active Poly Al1 Al2 Al3 Al4
Poly 88
54
Al1 30 41 57
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 3812 12 12 14 19 27 52
fringe in aF/mpar. plate in aF/m2
Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/m for minimally-spaced wires
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EE415 VLSI Design 17
Dealing with Capacitance Low capacitance (low-k) dielectrics
(insulators) such as polymide or even airinstead of SiO2 family of materials that are low-k dielectrics
must also be suitable thermally and mechanically
and compatible with (copper) interconnect
Copper interconnect allows wires to be thinnerwithout increasing their resistance, thereby
decreasing interwire capacitance SOI (silicon on insulator) to reduce junction
capacitance
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EE415 VLSI Design 18
INTERCONNECT
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EE415 VLSI Design 19
Wire Resistance
L
W
H
R = L
H W
Sheet Resistance R
R1 R2=
=
L
A=
Material (-m)Silver (Ag) 1.6 x 10-8
Copper (Cu) 1.7 x 10-8
Gold (Au) 2.2 x 10-8
Aluminum (Al) 2.7 x 10-8
Tungsten (W) 5.5 x 10-8
Material Sheet Res. (/)n, p well diffusion 1000 to 1500
n+, p+ diffusion 50 to 150
n+, p+ diffusionwith silicide
3 to 5
polysilicon 150 to 200
polysilicon with
silicide
4 to 5
Aluminum 0.05 to 0.1
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EE415 VLSI Design 20
Sources of Resistance
MOS structure resistance - Ron
Source and drain resistance
Contact (via) resistance
Wiring resistance
Top view
Drain n+ Source n+
W
L
Poly Gate
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EE415 VLSI Design 21
Contact Resistance
Vias add extra resistance to a wire keep signals wires on a single layer if possible
avoid excess contacts
using multiple vias to make the contact
Typical contact resistances, RC,
5 to 20 for metal or poly to n+, p+ diffusionand metal to poly
2 to 20 for metal to metal contacts
More pronounced with scaling since contact
openings are smaller
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EE415 VLSI Design 14: Wires22
Contacts Resistance
Use many contacts for lower R
Many small contacts for current crowding
around periphery
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EE415 VLSI Design 23
Skin Effect At high frequency, currents tend to flow on the surface of a
conductor with the current density falling off exponentially with
depth into the wire
H
W= (/(f))where f is frequency
= 4 x 10-7 H/m
so the overall cross section is ~ 2(W+H)
= 2.6 mfor Al at 1 GHz
The onset of skin effect is at fs - where the skin depth is equal to half
the largest dimension of the wire.fs = 4 / ( (max(W,H))2)
An issue for high frequency, wide (tall) wires (i.e., clocks!)
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EE415 VLSI Design 24
Skin Effect for Different Ws
A 30% increase in resistance is observe for 20 m Al wires at 1 GHz(versus only a 1% increase for 1 m wires)
0.1
1
10
100
1000
Frequency (Hz)
%I
ncreas
einResistanc
e
W = 1 um
W = 10 um
W = 20 um1E8 1E9 1E10
for H = .70 um
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EE415 VLSI Design 25
Dealing with Resistance
Selective Technology Scaling
Use Better Interconnect Materials
e.g. copper, silicidesMore Interconnect Layers
reduce average wire-length
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EE415 VLSI Design 26
Polycide Gate MOSFET
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi2, TiSi2, PtSi2and TaSi
Conductivity: 8-10 times better than Poly
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EE415 VLSI Design 27
Modern Interconnect
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EE415 VLSI Design 28
Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
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EE415 VLSI Design 29
InterconnectModeling
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EE415 VLSI Design 30
The Lumped Model
Vout
Driver
cwire
VinClumped
RdriverVout
Th L d RC M d l
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EE415 VLSI Design 31
The Lumped RC-Model
The Elmore Delay
To model propagation delay
time along a path from the
source s to destination iconsidering the loading effect
of the other nodes on the pathfrom s to k
The shared path resistance Rik
The Elmore delay
s
Th Ell D l
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EE415 VLSI Design 32
The Ellmore Delay
RC Chain
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EE415 VLSI Design 33
Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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EE415 VLSI Design 34
The Distributed RC-line
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EE415 VLSI Design 35
Step-response of RC wire as a
function of time and space
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time nsec
voltage
(V)
x= L/10
x = L/4
x = L/2
x= L
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EE415 VLSI Design 36
RC-Models
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EE415 VLSI Design 37
Driving an RC-line
Vin
Rs V
ou
(rw,cw,L)
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EE415 VLSI Design 38
Design Rules of Thumb
rc delays should only be considered whentpRC >> tpgate of the driving gate
Lcrit >> tpgate/0.38rc rc delays should only be considered when the
rise (fall) time at the line input is smaller thanRC, the rise (fall) time of the line
trise < RC otherwise, the change in the input signal is slower
than the propagation delay of the wire