Chapter 4: Processor Architecture How does the hardware execute the instructions? We’ll see by studying an example system Based on simple instruction set devised for this purpose Y86, inspired by x86 Fewer data types, instructions, addressing modes Simpler encodings Reasonably complete for integer programs We’ll design hardware to implement Y86 ISA Basic building blocks Sequential implementation Pipelined implementation
Instruction Set Architecture Defines interface between hardware and software Software spec is assembly language State: registers, memory Instructions, encodings Hardware must execute instructions correctly May use variety of transparent tricks to make execution fast. Results must match sequential execution. ISA is a layer of abstraction Above: how to program machine Below: what needs to be built ISA Compiler OS CPU Design Circuit Chip Layout Application Program
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Chapter 4: Processor Architecture How does the hardware execute the instructions? We’ll see by studying an example system
Based on simple instruction set devised for this purpose Y86, inspired by x86
Fewer data types, instructions, addressing modes Simpler encodings Reasonably complete for integer programs
We’ll design hardware to implement Y86 ISA Basic building blocks Sequential implementation Pipelined implementation
Instruction Set Architecture Defines interface between hardware
and software Software spec is assembly language
State: registers, memory Instructions, encodings
Hardware must execute instructions correctly
May use variety of transparent tricks to make execution fast.
Results must match sequential execution.
ISA is a layer of abstraction Above: how to program machine Below: what needs to be built
ISA
Compiler OS
CPUDesign
CircuitDesign
ChipLayout
ApplicationProgram
Where Are We Now?
Memory
Loader
Executable (mach lang pgm): a.out
Linker
Object (mach lang module): foo.o
Assembler
Assembly program: foo.s
Compiler
C program: foo.c
lib.o
CS142 & 124
IT344
Y86 Processor and System State
Program Registers Same 8 as with IA32. Each 32 bits
Condition Codes Single-bit flags as in x86: OF (Overflow), ZF (Zero), SF (Negative)
Program Counter Indicates address of instruction
Memory Byte-addressable storage, words in little-endian byte order
Stat Indicates exceptional outcomes (bad opcode, bad address, halt)
%eax%ecx%edx%ebx
%esi%edi%esp%ebp
RF: Program registers
ZF SF OF
CC: Condition
codes
PCDMEM: Memory
Stat: Program Status
Y86 Instructions Format
1 to 6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types, and simpler encoding than IA32
Each accesses and modifies some portion of the CPU and system state
Program registers Condition codes Program counter Memory contents
Encoding Registers Each register has 4-bit ID
Similar encoding used in IA32 But we never deciphered encoding to notice!
Register ID 0xF indicates “no register” Will use this in our hardware design in multiple places Could otherwise encode register # in 3 bits Simplifies decoding of instructions
%eax%ecx%edx%ebx
%esi%edi%esp%ebp
0123
6745
Instruction Example Addition instruction
Add value in register rA to that in register rB Store result in register rB Y86 allows addition to be applied to register data only
Set condition codes based on result Two-byte encoding
First byte indicates instruction type Second gives source and destination registers e.g., addl %eax,%esi has encoding 60 06
addl rA, rB 6 0 rA rB
Encoded RepresentationGeneric Form
Arithmetic and Logical Operations
Refer to generically as “OPl” Encodings differ only by
“function code” Low-order 4 bits in first
instruction word All set condition codes as side
effect
addl rA, rB 6 0 rA rB
subl rA, rB 6 1 rA rB
andl rA, rB 6 2 rA rB
xorl rA, rB 6 3 rA rB
Add
Subtract (rA from rB)
And
Exclusive-Or
Instruction Code Function Code
Move Operations
Similar to the IA32 movl instruction Simpler format for memory addresses Separated into different instructions to simplify hardware
implementation
rrmovl rA, rB 2 0 rA rB Register --> Register
Immediate --> Registerirmovl V, rB 3 0 F rB V
Register --> Memoryrmmovl rA, D(rB) 4 0 rA rB D
Memory --> Registermrmovl D(rB), rA 5 0 rA rB D
Move Instruction Examples
irmovl $0xabcd, %edx movl $0xabcd, %edx 30 82 cd ab 00 00
CISC arguments Easy for compiler (bridge semantic gap) Concise object code (memory was expensive)
RISC arguments Simple is better for optimizing compilers A simple CPU can be made to run very fast
Current status For desktop processors, choice of ISA not a technical issue
With enough hardware, anything can be made to run fast Code compatibility more important
For embedded processors, RISC makes sense Smaller, cheaper, less power
4.1 Summary Y86 instruction set architecture
Similar state and instructions as IA32 Simpler encodings Small instruction set Y86 somewhere between CISC and RISC
Changes from x86 consistent with RISC principles
4.2: Logic Design: A Brief Review Fundamental hardware requirements
Communication How to get values from one place to another
Computation Storage
All are simplified by restricting to 0s and 1s Communication
Low or high voltage on wire Computation
Compute Boolean functions Storage
Store bits of information
Communication: Digital Signals
Use voltage thresholds to extract discrete values from continuous signal
Simplest version: 1-bit signal Either high range (1) or low range (0) With guard range between them
Not strongly affected by noise or low quality circuit elements Can make circuits simple, small, and fast
Voltage
Time
0 1 0
Computation: Logic Gates
Outputs are Boolean functions of inputs Respond continuously to changes in inputs
After some small delay
Voltage
Time
a
ba && b
Rising Delay Falling Delay
Combinational Circuits
Acyclic network of logic gates Continuously responds to changes on primary inputs Primary outputs become (after some delay) Boolean functions of
primary inputs
Acyclic Network
PrimaryInputs
PrimaryOutputs
Bit Equality
Generate 1 if a and b are equal Hardware control language (HCL)
Very simple hardware description language Boolean operations have syntax similar to C logical operations
We’ll use it to describe control logic for processors Much more convenient than drawing gates Assumes compiler exists to turn HCL into gate equivalent
Bit equala
b
eq
bool eq = (a&&b)||(!a&&!b)
HCL Expression
Word Equality
32-bit word size HCL representation
Equality operation Generates Boolean value
b31Bit equal
a31
eq31
b30Bit equal
a30
eq30
b1Bit equal
a1
eq1
b0Bit equal
a0
eq0
Eq
=B
A
Eq
Word-Level Representation
bool Eq = (A == B)
HCL Representation
Bit-Level Multiplexer
Control signal s Data signals a and b Output a when s=1, b when s=0
Bit MUX
b
s
a
out
bool out = (s&&a)||(!s&&b)
HCL Expression
Word Multiplexer
Select input word A or B depending on control signal s
HCL representation Case expression Series of test : value pairs Result value determined by first
successful test
Word-Level Representation
HCL Representation
b31
s
a31
out31
b30
a30
out30
b0
a0
out0
int Out = [ s : A; 1 : B;];
s
B
AOutMUX
Arithmetic and Logical Operations
Refer to generically as “OPl” Encodings differ only by
“function code” Low-order 4 bits in first
instruction word All set condition codes as side
effect
addl rA, rB 6 0 rA rB
subl rA, rB 6 1 rA rB
andl rA, rB 6 2 rA rB
xorl rA, rB 6 3 rA rB
Add
Subtract (rA from rB)
And
Exclusive-Or
Instruction Code Function Code
OFZFCF
OFZFCF
OFZFCF
OFZFCF
Arithmetic Logic Unit
Combinational logic Continuously responding to inputs
Control signal selects function computed Corresponding to 4 arithmetic/logical operations in Y86
Also computes values for condition codes
ALU
Y
X
X + Y
0
ALU
Y
X
X - Y
1
ALU
Y
X
X & Y
2
ALU
Y
X
X ^ Y
3
A
B
A
B
A
B
A
B
Edge-Triggered Latch (Flip Flop)
Only in latching mode for brief period
On rising clock edge Value latched depends on
data as clock rises Output remains stable at all
other times
Q+
Q–
R
S
D
C
Data
Clock TTrigger
C
D
Q+
Time
T
Storage: Registers
Each stores word of data (one byte in above register) Different from program registers (e.g., %eax)
Collection of edge-triggered latches Loads input on rising edge of clock
I O
Clock
DC Q+
DC Q+
DC Q+
DC Q+
DC Q+
DC Q+
DC Q+
DC Q+
i7
i6
i5
i4
i3
i2
i1
i0
o7
o6
o5
o4
o3
o2
o1
o0
Clock
Structure
Register Operation
Stores data bits For most of time acts as barrier between input and output As clock rises, loads input
State = x
RisingclockOutput = xInput = y
x State = y
Output = y
y
State Machine Example
Accumulator circuit Load or accumulate
on each cycle
Comb. Logic
ALU
0
OutMUX
0
1
Clock
InLoad
x0 x1 x2 x3 x4 x5
x0 x0+x1 x0+x1+x2 x3 x3+x4 x3+x4+x5
Clock
Load
In
Out
Storage: Random-Access Memory
Stores multiple words of memory Address input specifies which word to read or write
Register file Holds values of program registers
– %eax, %esp, etc. Register identifier serves as address
– ID 0xF implies no read or write performed Multiple Ports
Can read and/or write multiple words simultaneously– Each has separate address and data input/output
Registerfile
A
B
WdstW
srcA
valA
srcB
valB
valW
Read ports Write port
Clock
Register File Timing
Reading Like combinational logic Output data generated based on input
address After some delay
Writing Like register (a few slides ago) Update only as clock rises
Registerfile
A
B
srcA
valA
srcB
valB
y2
Registerfile
W dstW
valW
Clock
x2Risingclock Register
fileW dstW
valW
Clock
y2
x2
2
x
Administrivia Lab 4 – Farmer Game in VHDL HW 5 – Farmer Game in C HW 5 – Buffer Overflow #1 Quiz 3 – due Feb 7 Quiz 4 – due Feb 14 Quiz 5 – due Feb 21 Midterm – available after class on Feb 28
No class Mar 1, work on the exam Due 5PM Monday Mar 5 Take home, open book, open notes, open lecture slides NO COLLABORATION
FPGA in IT Network switch Security gateway System on a chip Embedded system …
4.2 Summary Computation
Performed by combinational logic Computes Boolean functions Continuously reacts to input changes
Storage Registers
Hold single words Loaded as clock rises
Random-access memories Hold multiple words Multiple read and write ports possible Read word anytime address input changes Write word only on rising clock edge