Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR FIREWALL IMPLEMENTATION 1 Chapter 4 Instantiation of Customized Soft IP Core for Multiprocessor Firewall Implementation This chapter presents the complete system design based on the core principle of hardware -software co-design. The main contribution is reporting the technical know-how related to the codesign aspects that comprehend synergic mixture of soft IP cores of the content addressable memory (CAM) in hardware and software with the Xilinx Spartan 3e and Microblaze processor. Another striking attribute of this chapter is presentation of the customization / adaptation of the Xilinx Microblaze processor in terms of multiprocessor configuration and to facilitate the inter- processor communication for accessing the filter rule base and packet parsing. The toolset used to accomplish the hardware-software codesign is the Xilinx Embedded Design Kit (EDK). The design flow comprises of the IP core design in Handel-C, embedded in EDK driven by the central customized core of Microblaze. At the end of the chapter the device usage summary is covered with in-depth description of the overall design flow and the resulting System on Chip (SoC) on the Xilinx Spartan 3e FPGA. 4.1 Introduction The most appropriate means in the complex product design with heavy software overhead such as the present ones i.e. firewall is adopting the methodology of amalgamation of various IP cores and customizing them to work on a single prototyping platform such as FPGA. The literature also reveals a similar trend and expresses that the System-chip design which starts at the RTL-level today has hit a plateau of productivity and re-use which can be characterized as a “Silicon Ceiling” has become the upcoming methodology in the VLSI arena. However, breaking through this plateau and moving to higher and more effective re-use of IP blocks and system-chip architectures demands a move to a new methodology: one in which the best aspects of today’s RTL based methods are retained, but complemented by new levels of abstraction and the commensurate tools to
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Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
FIREWALL IMPLEMENTATION
1
Chapter 4 Instantiation of Customized Soft IP Core for Multiprocessor Firewall Implementation
This chapter presents the complete system design based on the core principle
of hardware-software co-design. The main contribution is reporting the technical
know-how related to the codesign aspects that comprehend synergic mixture of soft IP
cores of the content addressable memory (CAM) in hardware and software with the
Xilinx Spartan 3e and Microblaze processor. Another striking attribute of this
chapter is presentation of the customization / adaptation of the Xilinx Microblaze
processor in terms of multiprocessor configuration and to facilitate the inter-
processor communication for accessing the filter rule base and packet parsing. The
toolset used to accomplish the hardware-software codesign is the Xilinx Embedded
Design Kit (EDK). The design flow comprises of the IP core design in Handel-C,
embedded in EDK driven by the central customized core of Microblaze. At the end of
the chapter the device usage summary is covered with in-depth description of the
overall design flow and the resulting System on Chip (SoC) on the Xilinx Spartan 3e
FPGA.
4.1 Introduction
The most appropriate means in the complex product design with heavy software
overhead such as the present ones i.e. firewall is adopting the methodology of
amalgamation of various IP cores and customizing them to work on a single prototyping
platform such as FPGA. The literature also reveals a similar trend and expresses that the
System-chip design which starts at the RTL-level today has hit a plateau of productivity
and re-use which can be characterized as a “Silicon Ceiling” has become the upcoming
methodology in the VLSI arena. However, breaking through this plateau and moving to
higher and more effective re-use of IP blocks and system-chip architectures demands a
move to a new methodology: one in which the best aspects of today’s RTL based methods
are retained, but complemented by new levels of abstraction and the commensurate tools to
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
FIREWALL IMPLEMENTATION
2
allow designers to exploit the productivity inherent in these higher levels of abstraction [1].
The state of art System on Chip (SoC) design shows a clear trend toward integration of
multiple processor cores especially for the applications in networked paradigm. The SoC
system driver section of the International Technology Roadmap for Semiconductors
(http://public.itrs.net) predicts that the number of processor cores in a typical SoC will
increase fourfold per technology node to match the corresponding applications’ processing
demands. Typical multiprocessor SoC (MPSoC) applications, such as network processors,
multimedia hubs, and baseband telecommunications circuits, have fuelled the above
mentioned trend [3]. Thus Ready-to-use IP designs of complex functionalities greatly
reduce the time and effort of hardware development. However, IP designs in the form of
static library modules have the limitation that they cannot match the optimal
cost/performance tradeoff encountered in every application scenario [2]. Therefore the
design flow for such combination can be realized by using the Hardware-Software
Codesign methodology that makes the best use of each of the domain. It is worthwhile to
present this methodology in contextual reference with the research problem taken in our
work.
4.2 Hardware-Software Codesign: Synergizing the Performance
Hardware/software co-design means meeting system- level objectives by exp loiting
the synergism of hardware and software through their concurrent design. Formal definition
of the same is given as [12]:
“The meeting of system- level objectives by exploiting the trade-offs between
hardware and software in a system through their concurrent design”
The key concepts involved are:
? Concurrent: hardware and software developed at the same time on parallel
paths
? Integrated: interaction between hardware and software development to
produce design meeting performance criteria and functional specs
Since digital systems have different organizations and applications, there are several
co-design problems of interest [4]. Thus designing hardware and software in isolation no
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
FIREWALL IMPLEMENTATION
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longer provides good solutions for complex embedded systems. Hardware-software
codesign (HSC) promises an integrated approach in which hardware and software are
designed in parallel. CAD environments, employing the tenets of HSC, are now being
developed to provide a cost and time effective solution [5].
As far as the history of the HSC is concerned the pioneering work was carried out
by Prakash and Parker of the University of Southern California [6]. Early work also dealt
with co-simulation and soon recognized the same as an essential component of a codesign
methodology. The challenge was to perform co-simulation at mixed abstraction levels to
execute enough input vectors to validate the design. With mixed- level simulation, designers
can trade off simulation performance for accuracy by choosing the detail level at which to
simulate various system components. Such a co-simulator was developed for the first time
in 1992, by Becker, Singh, and Tell [7] that linked a hardware simulator to executions of
application software. In earlier days FSM model was predominantly used to address the
codesign issues [9]. Thus in nutshell HSC is widely expressed in the literature as a complex
discipline that builds upon advances in several areas such as software compilation,
computer architecture and very large scale integration (VLSI) circuit design. Co-design is
perceived as an important problem, but the field is fragmented because most efforts are
applied to specific design problems [10]. However, the things are changing rapidly and
unified design frameworks are emerging. One such framework is recently reported by us in
[11].
4.3 Motivation behind the Hardware Software Codesign
There are number of driving forces fuelling the HSC methodology. Some of them
are as follows:
? Availability of the hard and soft cores of the processors such as Microblaze, the one
used in this work
? Increasing software centric applications of the present VLSI chips
? Capability of the FPGAs to reprogram on a fly
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
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? Emerging C based design methodology that eases the EDIF coding of the complex
algorithms
? Possibility of rapid prototyping
? Unified testing environment of the Hardware and software instead of testing them
in isolation
? Better matching of the software with the underlying hardware thus improving the
overall efficiency
? Less possibility of failures with the hardware and software being on one chip
? Reduced development time due to possible parallelism in designing hardware and
software.
However there are many open problems in Hardware Software Codesign when it
comes to applications such as Network on Chip, the one that is dealt in the present
research. The problem is pertaining to evaluation of the effect of networks on chips on
codesign. On the one hand, NoCs provide a more structured system that should be easier to
analyze. On the other, NoCs are themselves complex systems that are not trivial to analyze
for performance or power, so adding them to architecture make it that much harder to
analyze [13]. Nevertheless an increasing number of embedded systems connect to the
Internet, which imposes new workloads and new mixtures of hard and soft deadlines.
Along with this new synthesis tools such as the Xilinx Embedded Design Kit used in our
work are turned out to be viable options to realize the designs. With the completion of more
than a decade since its inception the HSC has become a recognized research field that has
moved from an emerging discipline to a mainstream technology [14]. Therefore, it is
worthwhile to take a review of the existing and recently introduced Hardware Software Co-
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
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4.7.2 Ethernet MAC Core
The Ethernet MAC instantiated here is used for network communication interface.
The above mentioned Ethernet MAC is capable of transmitting and receiving data at 10 and
100 Mbps and supports MII interfacing. The interfacing details of this core are given in
table 4.3
Table 4.3 Ports List and Other Interfacing Details of the Ethernet MAC
PORT LIST These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL 0 PHY_tx_clk I 0:0 fpga_0_Ethernet_MAC_PHY_tx_clk_pin 1 PHY_rx_clk I 0:0 fpga_0_Ethernet_MAC_PHY_rx_clk_pin 2 PHY_crs I 0:0 fpga_0_Ethernet_MAC_PHY_crs_pin 3 PHY_dv I 0:0 fpga_0_Ethernet_MAC_PHY_dv_pin 4 PHY_rx_data I 0:3 fpga_0_Ethernet_MAC_PHY_rx_data_pin 5 PHY_col I 0:0 fpga_0_Ethernet_MAC_PHY_col_pin 6 PHY_rx_er I 0:0 fpga_0_Ethernet_MAC_PHY_rx_er_pin 7 PHY_tx_en O 0:0 fpga_0_Ethernet_MAC_PHY_tx_en_pin 8 PHY_tx_data O 0:3 fpga_0_Ethernet_MAC_PHY_tx_data_pin 9 PHY_MDC O 0:0 fpga_0_Ethernet_MAC_PHY_MDC_pin 10 IP2INTC_Irpt O 0:0 Ethernet_MAC_IP2INTC_Irpt 11 PHY_MDIO IO 0:0 fpga_0_Ethernet_MAC_PHY_MDIO_pin
Bus Interfaces NAME TYPE BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 11 Peripherals.
4.7.3 Embedding the CAM Filter Core
The CAM filter IP core which was designed in the previous chapter is instantiated
here and connected to the rest of the 11 peripherals by means of PLBV46 bus.
Integration of the CAM IP core to the other cores has been done by means of following
steps:
? The design was started in EDK environment by specifying the Spartan 3e starter kit
? Create and Import peripheral wizard was used to instantiate the CAM IP core
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR
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? In order to facilitate the read/write operations of the peripheral cores with the CAM,
a FIFO mechanism was selected. The FIFO was selected as against the register
mechanism due to the possibility of simultaneous read/write without contention.
? The CAM core originally designed by using Handel C was converted into the EDIF
and then integrated as a black box.
The implementation of the CAM soft IP core in the form of pseudo code is given below:
************************** Pseudo code for the CAM ***********************
interface port_in(unsigned 1 clk with {clockport=1}) clockport();
unsigned 32 result;
interface port_in (unsigned 8 a) Inport() with {busformat = "B<N:0>"};
interface port_out() outport(unsigned 32 p = result) with {busformat = "B<N:0>"};
set clock = internal clockport.clk;
//set clock =external "c9";
mpram filter
{ ram <unsigned 8> ReadWrite[256]; // Read/write port
rom <unsigned 8> Read[256]; // Read only port
}; mpram filter SrcIP1;
void main()
{
unsigned 8 in1;
unsigned 8 IP;
while(1)
{
in1 = Inport.a;
IP=in1;
par (i=0;i<255;i++)
{
SrcIP1.ReadWrite[i]=192;
}
Chapter 4: INSTANTIATION OF CUSTOMIZED SOFT IP CORE FOR MULTIPROCESSOR