1 George Mason University Dataflow Modeling in VHDL ECE 545 Lecture 6 2 Required reading • P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 3 Components and interconnects structural VHDL Descriptions dataflow Concurrent statements behavioral (sequential) • Registers • State machines • Instruction decoders Sequential statements Subset most suitable for synthesis • Testbenches Types of VHDL Description 4 Synthesizable VHDL Dataflow VHDL Description VHDL code synthesizable VHDL code synthesizable Dataflow VHDL Description 5 Register Transfer Level (RTL) Design Description Combinational Logic Combinational Logic Registers … Today’s Topic 6 Data-Flow VHDL • simple concurrent signal assignment (Ü) • conditional concurrent signal assignment (when-else) • selected concurrent signal assignment (with-select-when) Concurrent Statements
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1
George Mason University
Dataflow Modelingin VHDL
ECE 545Lecture 6
2
Required reading
• P. Chu, RTL Hardware Design using VHDL
Chapter 4, Concurrent Signal Assignment Statements of VHDL
3
Components andinterconnects
structural
VHDL Descriptions
dataflow
Concurrent statements
behavioral(sequential)
• Registers• State machines• Instruction decoders
Sequential statements
Subset most suitable for synthesis
• Testbenches
Types of VHDL Description
4
Synthesizable VHDL
Dataflow VHDL Description
VHDL codesynthesizable
VHDL codesynthesizable
Dataflow VHDL Description
5
Register Transfer Level (RTL) Design Description
Combinational Logic
Combinational Logic
Registers
…
Today’s Topic
6
Data-Flow VHDL
• simple concurrent signal assignment (Ü)
• conditional concurrent signal assignment(when-else)
• selected concurrent signal assignment(with-select-when)
Concurrent Statements
2
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Simple concurrent signal assignment
target_signal <= expression;
<=
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Conditional concurrent signal assignment
target_signal <= value1 when condition1 elsevalue2 when condition2 else. . .
valueN-1 when conditionN-1 elsevalueN;
When - Else
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Selected concurrent signal assignment
with choice_expression selecttarget_signal <= expression1 when choices_1,
expression2 when choices_2,. . .
expressionN when choices_N;
With –Select-When
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Data-Flow VHDL
• simple concurrent signal assignment (Ü)
• conditional concurrent signal assignment(when-else)
• selected concurrent signal assignment(with-select-when)