CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model

S. Barua – CPSC 240 [email protected] http://sbarua.ecs.fullerton.edu

CHAPTER 4COMPUTER SYSTEM – Von Neumann Model

Topics

Basic components of a computer

Instruction processing

Examples from the LC-3 simulator

Changing the sequence of execution


Basic Components of a Computer System

The basic components are:

• Central processing unit (CPU) • Memory • Input devices • Output devices

A clock controls all the operations performed in a computer system.

A computer system is a synchronous machine.


Von Neumann Model of a Computer System

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CON TR OL UN IT

M AR M DR

IR

P R OCE S S IN G UN IT

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Central Processing Unit (CPU)

The CPU consists of:• Arithmetic logic unit (ALU)• Control unit (CU)• Small set of storage areas, called registers

Arithmetic Logic Unit (ALU)

The ALU is the primary processing unit in a computer.

It performs all the arithmetic and logic operations.

Control Unit (CU)

The CU controls all the operations performed by a computer and determines what operations the program calls for and in what order they need to be carried out.


CPU (Continued)

The CPU is responsible for:• The complete processing of information • All the decision-making operations

Word Size of a processor:• Number of bits the processor reads from or writes

into the memory in one clock cycle• Number of bits normally processed by ALU in one

instruction• Also width of registers• LC-3 is a 16 bit processor


Memory

Memory provides the storage space for• the program that is currently being executed • the data that is needed during the execution of the

program

The memory unit consists of a number of memory locations of the same width.

The number of bits that can be stored in a memory location corresponds to the memory width.

Each memory location is identified by a unique address.

Memory capacity = Total number of memory locations * memory width


Interface to Memory

M E M OR Y

M AR M DR

MAR: Memory Address Register

MDR: Memory Data Register


Block Diagram of a Memory Unit

memory width

7 6 5 4 3 2 1 0 0 1 2 .

MAR 10 bits . 8 bits MDR .

10-bit memory address . 8-bit data

(A9 – A0) . (D7 – D0) . 1023

For this example, memory capacity = 210 x 8 bits = 1 Kbytes

(The above figure does not show the control signals needed to control the memory read and memory write

operations.)


Memory - Basic Operations

LOAD - Read data from a memory location1. Write the address of the location into the MAR.

2. Send a “read” signal to the memory.

3. Read the data from MDR.

STORE - Write data to a memory location1. Write the data to the MDR.

2. Write the address of the location into the MAR.

3. Send a “write” signal to the memory.


Input/Output (I/O) Devices

Input devices transfer information from the outside world into the memory of a computer system.

Examples: Keyboard, disk drives, scanner, mouse

Output devices transfer information from the memory of a computer system into the outside world.

Examples: Printers, display units, plotters, disk drives

Some devices provide both input and outputExamples: disk, network

Driver - Program that controls access to a device


Buses in a Computer System

Buses are the physical link between the various

components within the computer.

The computer employs mainly three types of buses:

• Address bus

• Data bus • Control bus


Buses in a Computer System (Continued)

Three types of buses in a computer system:

• Address bus: Carries the address generated by the CPU to the memory and I/O.

• Data bus: Allows the transfer of data between the CPU, memory and I/O.

• Control bus: Carries the control signals, generated by the control unit, to the various components in

the system in order to ensure proper sequencing of data and instruction movement.


Block Diagram of a Basic Computer Architecture

CPU

Clock CU ALU Clock Generator

Address Bus p

Data Bus q

Control Bus r

Main Memory I/O Unit

I/O Bus (represents address, data, & control)

Keyboard Printer Secondary Memory


Instruction

The instruction specifies two items:• Opcode: operation to be performed• Operands: data/locations to be used for operation

An instruction is encoded as a sequence of bits. Often,but not always, instructions have a fixed length, such as16 or 32 bits.

Instruction Format – The binary representation of an instruction


Instruction (Continued)

Control unit• interprets the instruction • generates sequence of control signals to carry

out operation.

A computer’s instructions and their formats is known as

its Instruction Set Architecture (ISA).


Instruction Processing

Decode instructionDecode instruction

Evaluate addressEvaluate address

Fetch operands from memoryFetch operands from memory

Execute operationExecute operation

Store resultStore result

Fetch instruction from memoryFetch instruction from memory


Instruction Processing: FETCH

Load the instruction from memory into Instruction Register

• Copy contents of PC into MARMAR ← PC

• Increment PC so that PC points to the next instruction in sequence

PC ← PC + 1• Send “read” control signal to memory

MDR ← Memory [MAR] • Copy contents of MDR into IR

IR ← MDR

EAEA

OPOP

EXEX

SS

FF

DD


Example Instruction: LDR Instruction

LDR R2, R3, #6 – Loads (reads) data from memory

into the destination register R2

Memory address: Base register + SEXT (offset)Memory address = R3 + 6 Load the contents of the memory location [R3 + 6] to R2


Instruction Processing: DECODE

• First identify the opcode• Identify the operands

Example: LDR R2, R3, #6

Opcode: IR[15:12] = 0110

Operands:

Offset: IR[5:0] = #6 (6 decimal; 000110 binary)

Base register: IR[8:6] = 011 = R3

EAEA

OPOP

EXEX

SS

FF

DD


Instruction Processing: EVALUATE ADDRESS

For instructions that require memory access,

compute address used for memory access.


Address = SEXT (offset) + Base Register

MAR ← 6 + R3

EAEA

OPOP

EXEX

SS

FF

DD


Instruction Processing: FETCH OPERANDS

Obtain source operands needed to

perform operation.


Load data from memory (LDR)

MDR ← Memory [MAR]

EAEA

OPOP

EXEX

SS

FF

DD


Instruction Processing: EXECUTE

Perform the operation, using the source

operands.


No operation done in this step

EAEA

OPOP

EXEX

SS

FF

DD


Instruction Processing: STORE RESULT

Write results to destination.

Destination can be a register or

Memory.


Data read from the memory is placed in

destination register.

R2 ← MDR

EAEA

OPOP

EXEX

SS

FF

DD


Changing the Sequence of Instructions

In the FETCH phase, we increment PC by 1.

Need special instructions called control instructions to

change the contents of the PC during the Execute

phase.• jumps (unconditional)

Always change the PC• branches (conditional)

PC is changed only if the specified condition is

true


Examples: LC-3 Control Instructions

JMP R2 ; PC ← R2

RET ; PC ← R7

BRzp NEXT ; if the last result was zero or positive then

PC ← address corresponding to NEXT


Instruction Processing Summary

Three basic kinds of instructions:• Arithmetic/logic instructions (ADD, AND, …)• Data transfer instructions (LD, ST, …)• Control instructions (JMP, BRnz, …)

Six basic phases of instruction processing:

F D EA OP EX S

Not all phases are needed by every instruction

Phases may take variable number of machine cycles


Example Instruction: LDR Instruction

LDR R2, R3, #6 ; R2 ← mem [R3 + 6]Opcode: IR[15:12] = 0110

Operands:

Base register: R3 given by IR[8:6]Offset: 6 given by IR[5:0]

Destination: R2 given by IR[11:9]


Instruction Processing: LDR R2, R3, #6

FetchMAR ← PCPC ← PC + 1MDR ← Memory [MAR] IR ← MDR

DecodeIdentify the opcodeIdentify the operands

Execute MAR ← 6 + R3 MDR ← Memory [MAR] R2 ← MDR


Example Instruction: ADD Instruction

ADD R6, R2, R6 ; R6 ← R2 + R6

Opcode: IR[15:12] = 0001

Operands:

Source1: R2 given by IR[8:6]Source2: R6 given by IR[2:0]

Destination: R6 given by IR[11:9]


Instruction Processing: ADD R6, R2, R6

Fetch

MAR ← PC

PC ← PC + 1


IR ← MDR

Decode

Identify the opcode

Identify the operands

Execute

R6 ← R2 + R6


Example Instruction: JMP Instruction

JMP R3 ; PC ← R3

Opcode: IR[15:12] = 0001

Operand: Base register R3 given by IR[8:6]


Instruction Processing: JMP R3

Fetch

MAR ← PC

PC ← PC + 1


IR ← MDR

Decode

Identify the opcode

Identify the operand

Execute

PC ← R3

CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model

Documents

memory unit memory width7

memory capacity

memory locationwrite

processormemory memory

memory address registermdr

memory width interface

memory basic operationsload

computer systembuses