CHAPTER 4 Combinational Logic Design – Multiplexers (Sections 4.5)

CHAPTER 4CHAPTER 4

Combinational Logic Design – Combinational Logic Design – Multiplexers Multiplexers

(Sections 4.5)(Sections 4.5)

MultiplexerMultiplexer ““Selects” binary information from one of many Selects” binary information from one of many

input lines and directs it to a single output line.input lines and directs it to a single output line. Also know as the “selector” circuit,Also know as the “selector” circuit, Selection is controlled by a particular set of inputs Selection is controlled by a particular set of inputs

lines whose output depends on the combination of lines whose output depends on the combination of the data input lines.the data input lines.

For a 2For a 2nn-to-1 multiplexer, there are 2-to-1 multiplexer, there are 2nn data input data input lines and lines and n n selection lines whose bit combination selection lines whose bit combination determines which input is selected.determines which input is selected.

Multiplexer (cont.)Multiplexer (cont.)

4-to-1 MUX4-to-1 MUX

A

B

Y=A’B’D0+A’BD1+AB’D2+ABD3

=∑miDii=0

2n-1

A B Y

00

0

0

D0

1

1

11

D1

D2

D3

8-to-1 MUX8-to-1 MUX74LS1574LS15

55

YYww

8-to-1 MUX8-to-1 MUX

Y= C’B’A’D0+ C’B’AD1+ C’BA’D2+C’BAD3+ CB’A’D4+ CB’AD5+ CBA’D6+ CBAD7

=∑miDii=0

i=2n-1

Until now, we have examined single-bit Until now, we have examined single-bit data selected by a MUX. What if we want data selected by a MUX. What if we want to select m-bit data/words?to select m-bit data/words? Combine MUX blocks in parallel with Combine MUX blocks in parallel with common select and enable signalscommon select and enable signals

Example: Construct a logic circuit that Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see selects between 2 sets of 4-bit inputs (see next slide for solution).next slide for solution).

Multiplexer ExpansionsMultiplexer Expansions

Example: Quad 2-to-1 MUXExample: Quad 2-to-1 MUX Uses four 2-to-1 Uses four 2-to-1

MUXs with common MUXs with common select (S) and enable select (S) and enable (E).(E).

Select line chooses Select line chooses between Abetween Aii’s and B’s and Bii’s. ’s.

The selected four-The selected four-wire digital signal is wire digital signal is sent to the Ysent to the Yii’s’s

Enable line turns Enable line turns MUX on and off (E=1 MUX on and off (E=1 is on).is on).

Example: Quad 4-to-1 MUXExample: Quad 4-to-1 MUX

74LS153(P43)74LS153(P43)


A32-to-A32-to-1multiplexer using 1multiplexer using two two 74xx150ICs(P144)74xx150ICs(P144)


A 32-to-1 A 32-to-1 multiplexer using multiplexer using four 8-to-1 four 8-to-1 multiplexers and a multiplexers and a 2-to-4 2-to-4 decoder(P145)decoder(P145)

Implementing Boolean functions with Implementing Boolean functions with MultiplexersMultiplexers

E.g. Using an 8-to-1 multiplexer to realize the Boolean E.g. Using an 8-to-1 multiplexer to realize the Boolean function F=f(x,y,z)=∑(1,2,4,5,7)function F=f(x,y,z)=∑(1,2,4,5,7)

Y= C’B’A’D0+ C’B’AD1+ C’BA’D2+C’BAD3+ CB’A’D4+ CB’AD5+ CBA’D6+ CBAD7

=∑miDii=0

i=2n-1

F=f(x,y,z)=∑(1,2,4,5,7)

=x’y’z+x’yz’+xy’z’+xy’z+xyz

C=x,B=y,A=z

D0=D3=D6=0

D1= D2= D4= D5= D7=1


C=x,B=y,A=z

D0=D3=D6=0

D1= D2= D4= D5= D7=1

Using an 4-to-1 multiplexer to realize the Using an 4-to-1 multiplexer to realize the Boolean function F=f(x,y,z)=∑(1,2,4,5,7)Boolean function F=f(x,y,z)=∑(1,2,4,5,7)

D3

D2

D1

D0

4-1

MUX

AB

F

1 1

1

1

XYZ 00 01 11 10

0

1

1

DD00=Z=Z

DD11=Z’=Z’

DD22=1=1

DD33=Z=Z

X Y

F=f(x,y,z)=∑(1,2,4,5,7)=x’y’z+x’yz’+xy’z’+xy’z+xyz

ZZ’1Z

ZXZ YDD00=X=X

DD11=X’=X’

DD22=1=1

DD33=X=X

DD00=Y=Y

DD11=Y’=Y’

DD22=Y’=Y’

DD33=1=1

YY’Y1

XX’1X

F=X’Y’DF=X’Y’D00+X’YD+X’YD11+XY’D+XY’D22+XYD+XYD33

Implementing Boolean functions Implementing Boolean functions with Multiplexerswith Multiplexers

Exe. implement function using a 4-to-1 MUX

F(X,Y,Z) = Σm(1,2,6,7) F(A,B,C) = m(1,3,5,6).


•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)•There are n=3 inputs, thus we need a 2222-to-1 MUX-to-1 MUX•The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines


1

1

1 1

ABC 00 01 11 10

0

1

F(A,B,C) = F(A,B,C) = m(1,3,5,6).m(1,3,5,6).

D3

D2

D1

D0

4-1

MUX

AB

AB

F

When A=B=0, F=D0=C

When A=0, B=1, F=D1=C

When A=1, B=0, F=D2=CWhen A=B=1, F=D3=C’


00111111

11001111

11110011

00000011

11111100

00001100

11110000

00000000

FFCCBBAA

When A=B=0, F=CWhen A=B=0, F=C

When A=0, B=1, When A=0, B=1, F=CF=CWhen A=1, B=0, When A=1, B=0, F=CF=CWhen A=B=1, When A=B=1, F=C’F=C’

MUX implementation of MUX implementation of F(A,B,C) = F(A,B,C) = m(1,3,5,6)m(1,3,5,6)

AA

BB

CC

CC

CC

C’C’

FF

E.g. Consider the following Boolean E.g. Consider the following Boolean expression given in sum-of-product form: expression given in sum-of-product form:

F(x1,x2,x3)=xF(x1,x2,x3)=x11’’xx22

’’+x+x11xx22’’+x+x11xx33

Derive a circuit for using only 2-to-1 Derive a circuit for using only 2-to-1 multiplexers.multiplexers.



F(x1,x2,x3)=xF(x1,x2,x3)=x11’’xx22

’’+x+x11xx22’’+x+x11xx33

= x= x11’’xx22

’ ’ xx3 3 ’’ + x+ x11

’’xx22’ ’ xx3 3 + x+ x11xx22

’ ’ xx3 3 ’’

+ x+ x11xx22’ ’ xx3 3 + x+ x11xx22xx33

=∑(0,1,4,5,7)=∑(0,1,4,5,7)X1X2

X300 01 11 10

0

1 1

1 1

11

DD00=X=X22’’

D1=XD1=X22’+X’+X33

How to derive it only from How to derive it only from function?function?

DD00=X=X22’’

D1=XD1=X22’+X’+X33


D1

D0

2-1

MUX

A

X1

F

X2’

≥1X3


Exe. F(A,B,C,D)=∑m(1,2,4,9,10,11,12,14,15)Exe. F(A,B,C,D)=∑m(1,2,4,9,10,11,12,14,15)

Derive a circuit for using 4-to-1 Derive a circuit for using 4-to-1 multiplexers.multiplexers.

MUX as a Universal GateMUX as a Universal Gate We can construct OR, AND, and NOT gates We can construct OR, AND, and NOT gates

using 2-to-1 MUXs. Thus, 2-to-1 MUX is a using 2-to-1 MUXs. Thus, 2-to-1 MUX is a universal gate.universal gate.

ORORNOTNOT ANDAND

z = xz = x11+ x+ x11’x’x0 0

= = xx11xx00’ + ’ + xx11xx00 + + xx11’x’x0 0 = = xx11 + x + x0 0

z = 0x + 1x’ = x’z = 0x + 1x’ = x’ z = xz = x11xx00 + 0x + 0x00’ = x’ = x11xx00

11

xx11

HomeworkHomework

P179: 25.(1), 26.(2)P179: 25.(1), 26.(2)

CHAPTER 4 Combinational Logic Design – Multiplexers (Sections 4.5)

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