Chapter 3 Arithmetic for Computers

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Chapter 3Arithmetic for Computers

Chapter 3Arithmetic for Computers

授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.)E-mail: [email protected]: (05)5342601 ext. 4337

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IntroductionIntroduction

自然數字的二進位表示法二進位與十進位的轉換 (binary to decimal conversion)

二進位與十六進位的轉換 (binary to hexadecimal conversion)

十六進位與十進位的轉換負數表示法二進位數的邏輯運算 (and, or)

二進位數的算術運算 (+, -, *, /)

分數 (fraction) 及浮點表示法硬體如何實際執行加、減、乘、除。

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Signed and Unsigned Numbers

In any number base, the value of ith digit d is

Binary numbers (base 2)least significant bit: the rightmost bitmost significant bit: the leftmost bit0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1

Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a negative n

umber

How do we represent negative numbers?i.e., which bit patterns will represent which numbers?

iBased

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Example: ASCII Vs. Binary NumbersExample: ASCII Vs. Binary Numbers

What is the expansion in storage if the number 1 billion is represented in ASCII versus a 32 bit integer?

1 billion = 1000000000 (10 個 ASCII 符號 )1 ASCII = 8 bits所以需要 8*10=80 bits因此 80/32=2.5

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Sign and Magnitude: One's Complement Two's Complement

000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1

Issues: number of zeros, ease of operations

Which one is best? Why?

The drawbacks of the sign-magnitude representation:

It’s not obvious where to put the sign bit.

Adders for sign and magnitude may need an extra step to set the sign because we can’t know in advance what the proper sign will be.

Two zeros, positive and negative zero.

Possible Representations of Negative Numbers

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32 bit signed numbers:

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten

0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten

...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten

0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten

1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten

...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten

1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten

1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

maxint

minint

MIPS: 2’s complement

以 0 為前導的數為正值

以 1 為前導的數為負值

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Example: Binary to Decimal conversionExample: Binary to Decimal conversion

What is the decimal value of this 32-bits two’s complement number?1111 1111 1111 1111 1111 1111 1111 1100(2)

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21474836442147483648

002...222

202021...2121212293031

012293031

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Negating a two's complement number: invert all bits and ad

d 1

Converting n bit numbers into numbers with more than n bit

s:

MIPS 16 bit immediate gets converted to 32 bits for arithmetic

copy the most significant bit (the sign bit) into the other bits

0010 -> 0000 0010

1010 -> 1111 1010

"sign extension"

lbu: load byte unsigned

lb: load byte

Two's Complement Operations

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•MIPS offers two versions of the set on less than comparison•有號數的若小於則設定 (slt, slti): set on less than, set on less than immediate•無號數的若小於則設定 (sltu, sltiu): set on less than unsigned, set on less than immediate unsigned

• 範例．假設暫存器 $s0 含有以下的二進位數

1111 1111 1111 1111 1111 1111 1111 1111 而暫存器 $s1 含有以下的二進位數

0000 0000 0000 0000 0000 0000 0000 0001 經由以下兩個指令運算後，暫存器 $t0 及 $t1 的值為何？

slt $t0, $s0, $s1sltu $t1, $s0, $s1

» 解答$s0: signed=-1, unsigned=4294967295$s1: signed=1, unsigned=1

得到 $t0 = 1 及 $t1 = 0.

Signed versus Unsigned ComparisonSigned versus Unsigned Comparison

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Example : Negation ShortcutExample : Negation Shortcut

Negate 2(10), and then check the result by negating -2(10).

2(10) = 0000 0000 0000 0000 0000 0000 0000 0010

Negating this number by inverting the bits and adding one.1111 1111 1111 1111 1111 1111 1111 1101 11111 1111 1111 1111 1111 1111 1111 1110= -2

0000 0000 0000 0000 0000 0000 0000 0001 10000 0000 0000 0000 0000 0000 0000 0010= 2

0 變 1 ， 1 變 0

+

+

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Example Sign Extension ShortcutExample Sign Extension Shortcut

Convert 16-bit versions of 2 and -2 to 32-bit binary numbers.

The 16-bit binary version of the number 2 is2 = 0000 0000 0000 0010

Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word. 0000 0000 0000 0000 0000 0000 0000 0010

The 16-bit binary version of the number -2 is-2 = 1111 1111 1111 1110

Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word. 1111 1111 1111 1111 1111 1111 1111 1110

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Binary-to-Hexadecimal ShortcutBinary-to-Hexadecimal Shortcut

Convert the following hexadecimal and binary numbers into the other base.(a) ECA8 6420(16)

(b) 0001 0011 0101 0111 1001 1011 1101 1111(2)

E = 1110 0001 = 1C = 1100 0011 = 3A = 1010 0101 = 58 = 1000 0111 = 76 = 0110 1001 = 94 = 0100 1011 = B2 = 0010 1101 = D0 = 0000 1111 = F=>(a) 1110 1100 1010 1000 0110 0100 0010 0000=>(b) 13579BDF

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Just like in elementary school (carry/borrow 1s) 0111 0111 0110+ 0110 -0110 -0101 1101 0001 0001

Two's complement operations easy

subtraction using addition of negative numbersx – y = x + (-y)

Example: 0111-0110 = ?Solution: 0110=>1001+1=1010

0111+ 1010 10001

Addition & Subtraction

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Addition & Subtraction (cont.)Addition & Subtraction (cont.)

Overflow (result too large for finite computer word):

e.g., adding two n-bit numbers does not yield an n-bit number 0111

+ 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

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No overflow when adding a positive and a negative numberNo overflow when signs are the same for subtractionOverflow occurs when the value affects the sign:

overflow when adding two positives yields a negative or, adding two negatives gives a positiveor, subtract a negative from a positive and get a negativeor, subtract a positive from a negative and get a positive

Effects of Overflow (2’s complement)An exception (interrupt) occurs

Control jumps to predefined address for exceptionInterrupted address is saved for possible resumption

MIPS has two kinds of arithmetic instructions to recognize the 2’s complement and unsigned integer.

add, addi, and sub cause exceptions on overflow.

addu, addiu, and subu do not cause exceptions on overflow.

Detecting Overflow

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Overflow conditions for addition and subtractionOverflow conditions for addition and subtraction

operation Operand A Operand B

Result

Indicating overflow

A+B >=0 >=0 <0

A+B <0 <0 >=0

A-B >=0 <0 <0

A-B <0 >=0 >=0

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1016 08unused0

Logical OperationsLogical Operations

Shifts

邏輯左移指令 (sll) shift left logical ： R 形態格式邏輯右移指令 (srl) shift right logical ： R 形態格式

範例：假如暫存器 $s0 內容為

0000 0000 0000 0000 0000 0000 0000 1101 而指令 sll $t2, $s0, 8 被執行 $t2 的值將為多少？

解答 0000 0000 0000 0000 0000 1101 0000 0000

上述指令的機器語言為： sll $t2, $s0, 8

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• bit-by-bit And (and) 指令•and, andi

• bit-by-bit Or (or) 指令•Or, ori

•Example: Mask ( 遮罩 ) 如果暫存器 $t2 內含

0000 0000 0000 0000 0000 1101 0000 0000 而暫存器 $t1 內含

0000 0000 0000 0000 0011 1100 0000 0000 則在 MIPS 指令執行後

and $t0, $t1, $t2 #reg $t0 = reg $t1 & reg $t2 $t0 的值將會是

0000 0000 0000 0000 0000 1100 0000 0000 在 MIPS 指令執行後

or $t0, $t1, $t2 #reg $t0 = reg $t1 | reg $t2 $t0 的值將會是

0000 0000 0000 0000 0011 1101 0000 0000

Logical OperationsLogical Operations

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More complicated than addition

accomplished via shifting and addition

More time and more area

Let's look at 3 versions based on grade school algorithm

0010 (multiplicand)__x_1011 (multiplier)

Negative numbers: convert and multiply

there are better techniques, we won’t look at them

Multiplication

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First Version of the Multiplication Algorithm

Done

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

64-bit ALU

Control test

MultiplierShift right

ProductWrite

MultiplicandShift left

64 bits

64 bits

32 bits

• 第一版乘法運算的演算法及硬體– 乘積暫存器先預設為 0 。– 如果每個步驟須花費一個時脈週期，這一版的乘法運算就要花費 100 個時脈週期才能完成。

相當於以手算方式進行，被乘數 (multiplicand) 每次往左移 1bit ，乘數 (multiplier) 每次往右移 1bit 。

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•Example: First Multiply Algorithm

Fig 4.27

MultiplicationMultiplication

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Second Version

MultiplierShift right

Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

Done

1. TestMultiplier0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1


Yes: 32 repetitions

•第二版乘法運算的演算法及硬體– 32- 位元 ALU–乘積暫存器先預設為 0 。

在直式的乘法運算中，每次乘積均會產生一個部份積；因此，將目前的部份積左移一位，相當於將前一部份積往右移一位。優點：1. 只需右移電路。2. 被乘數暫存器只需 32bit 。3. ALU 只需 32bit 。

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Final Version

ControltestWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

Done

1. TestProduct0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Start

Product0 = 0Product0 = 1


Yes: 32 repetitions

優點：1. 乘數暫存器併入乘積暫存器的右半段。2. 省掉 multiplier 暫存器及右移電路。

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ExampleExample

0010x0011

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Multiplying Negative NumbersMultiplying Negative Numbers

Solution 1Convert to positive if required

Multiply as above

If signs were different, negate answer

Solution 2Booth’s algorithm

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Comparison of Multiplication of Unsigned and Twos Complement IntegerComparison of Multiplication of Unsigned and Twos Complement Integer

部分積以 2n bit 表示可解決被乘數為負值的問題，但若乘數為負值時，仍無解

0011 (+3)x 1001 (-7)00000011000000000000000011 . 00011011 (+27)

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Booth’s algorithmBooth’s algorithm

令 a 為乘數 (multiplier) ， b 為被乘數 (multiplicand)

Booth’s algorithm 的動作可表示成 (ai-1-ai)

其中上式值的意義如下：0 : do nothing+1 : add b-1 : subtract b

將被乘數相對於乘積暫存器往左移，相當於乘以 2 的冪次方，因此 Booth’s algorithm 可寫成下式的乘積項和

將上式整理可得

而且 a-1=0 ，因此 (1) 式可改寫成

313130

221

110

001 2)...(2)(2)(2)( baabaabaabaa

ii

iii

iii

ii

ii aaaaaaa 2222222 1

ab

aaaab

0

029

2930

3031

31 2...222a 的 2 補數

0011

0101

ai ai-1 operation

Do nothingAdd bSubtract bDo nothing

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Example: Booth’s AlgorithmExample: Booth’s Algorithm

2*-3 = 0010 * 1101Iteration Step Multiplicand Product

0 Initial values 0010 0000 1101 0

110=>prod=prod-Mcand 0010 1110 1101 0

Shift right Product 0010 1111 0110 1

201=>prod=prod+Mcand 0010 0001 0110 1


310=>prod=prod-Mcand 0010 1110 1011 0


411=> no operation 0010 1111 0101 1


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Booth’s AlgorithmBooth’s Algorithm

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Examples Using Booth’s AlgorithmExamples Using Booth’s Algorithm

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Examples Using Booth’s Algorithm (cont.)Examples Using Booth’s Algorithm (cont.)

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DivisionDivision

More complex than multiplication

Based on long division

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001111

Division of Unsigned Binary IntegersDivision of Unsigned Binary Integers

1011

00001101

100100111011001110

1011

1011100

Quotient

Dividend

Remainder

PartialRemainders

Divisor

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First Version of the Division AlgorithmFirst Version of the Division Algorithm

64-bit ALU

Controltest

QuotientShift left

RemainderWrite

DivisorShift right

64 bits

64 bits

32 bits

Done

Test Remainder

2a. Shift the Quotient register to the left,setting the new rightmost bit to 1

3. Shift the Divisor register right 1 bit

33rd repetition?

Start

Remainder < 0


Yes: 33 repetitions

2b. Restore the original value by addingthe Divisor register to the Remainder

register and place the sum in theRemainder register. Also shift the

Quotient register to the left, setting thenew least significant bit to 0

1. Subtract the Divisor register from theRemainder register and place the result in the Remainder register

Remainder > 0–

每一次演算法需移動被除數往右 1bit 。所以，將被除數放在 64bit 的左半部，餘數暫存器初值設為除數。

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Example : First Divide AlgorithmExample : First Divide AlgorithmUsing a 4-bit version of the algorithm to calculate 7/2

Iteration Step Quotient Divisor Remainder

0 Initial values 0000 0010 0000 0000 0111

1

Rem=Rem-Div 0000 0010 0000 1110 0111

Rem<0,+Div, sll Q Q0=0 0000 0010 0000 0000 0111

Shift Div right 0000 0001 0000 0000 0111

2

Rem=Rem-Div 0000 0001 0000 1111 0111

Rem<0,+Div, sll Q Q0=0 0000 0001 0000 0000 0111

Shift Div right 0000 0000 1000 0000 0111

3

Rem=Rem-Div 0000 0000 1000 1111 1111

Rem<0,+Div, sll Q Q0=0 0000 0000 1000 0000 0111

Shift Div right 0000 0000 0100 0000 0111

4

Rem=Rem-Div 0000 0000 0100 0000 0011

Rem>=0, sll Q, Q0=1 0001 0000 0100 0000 0011

Shift Div right 0001 0000 0010 0000 0011

5

Rem=Rem-Div 0001 0000 0010 0000 0001

Rem>=0, sll Q, Q0=1 0011 0000 0010 0000 0001

Shift Div right 0011 0000 0001 0000 0001

初值是被除數的值

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Second version of the Division AlgorithmSecond version of the Division Algorithm

第一版的除法器中，除數暫存器最多只有一半的位元是有用的，因此可將 ALU 寬度減半將餘數左移一位元相當於將除數右移一位元

Controltest

QuotientShift left

Write

32 bits

64 bits

32 bits

Shift left

Divisor

32-bit ALU

Remainder

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Third version of the Division AlgorithmThird version of the Division Algorithm

Done. Shift left half of Remainder right 1 bit

Test Remainder

3a. Shift the Remainder register to the left, setting the new rightmost bit to 1

32nd repetition?

Start

Remainder < 0


Yes: 32 repetitions

3b. Restore the original value by addingthe Divisor register to the left half of theRemainder register and place the sum

in the left half of the Remainder register.Also shift the Remainder register to theleft, setting the new rightmost bit to 0

2. Subtract the Divisor register from theleft half of the Remainder register andplace the result in the left half of the

Remainder register

Remainder 0

1. Shift the Remainder register left 1 bit

–>

Write

32 bits

64 bits

Shift leftShift right

Remainder

32-bit ALU

Divisor

Controltest

藉由同時將運算元和商同時移位來加速除法運算。

商餘數

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Example : Third Divide AlgorithmExample : Third Divide Algorithm

Using a 4-bit version of the algorithm to calculate 7/2 Iteration Step Divisor Remainder

0Initial values 0010 0000 0111

Shift Rem left 1 0010 0000 1110

1Rem=Rem-Div 0010 1110 1110

Rem<0,+Div, sll R, R0=0 0010 0001 1100

2Rem=Rem-Div 0010 1111 1100

Rem<0,+Div, sll R, R0=0 0010 0011 1000

3Rem=Rem-Div 0010 0001 1000

Rem>=0, sll R, R0=1 0010 0011 0001

4Rem=Rem-Div 0010 0001 0001

Rem>=0, sll R, R0=1 0010 0010 0011

5 Rem=Rem-Div 0010 0001 0011

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Floating Point (a brief look)

We need a way to represent

numbers with fractions, e.g., 3.1416

very small numbers, e.g., .000000001

very large numbers, e.g., 3.15576 109

Representation:

sign, exponent, significand: (–1)sign * significand * 2exponent

more bits for significand gives more accuracy

more bits for exponent increases range

IEEE 754 floating point standard:

single precision: 8 bit exponent, 23 bit significand

double precision: 11 bit exponent, 52 bit significand

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Floating PointFloating Point

+/- .significand x 2exponent

Point is actually fixed between sign bit and body of mantissa

There is one bit to the left of the radix point.

Exponent value is biased representationA fixed value is subtracted from the field to get the true exponent valueThe bias equals (2k-1-1)

Sig

n bi

t

BiasedExponent

Significand or Mantissa

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IEEE 754 floating-point standard

Leading “1” bit of significand is implicit

Exponent is “biased” to make sorting easier

all 0s is smallest exponent all 1s is largest

bias of 127 for single precision and 1023 for double precision

summary: (–1)sign * (1+significand) * 2exponent – bias

Example:

decimal: -.75 = -3/4 = -3/22

binary: -.11 = -1.1 x 2-1

floating point: exponent = 126 = 01111110

IEEE single precision: 10111111010000000000000000000000

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IEEE 754 FormatsIEEE 754 Formats

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Example: Show the IEEE 754 binary representation of the number -0.75 (10) in single and double precision

Solution:-0.75 = -(0.11)2

= -(1.1)2 * 2-1

single precision ：1 01111110 100000…0

(126)10

double precision ：1 01111111110 1000 … 00000

(1022)10

IEEE 754 floating-point standardIEEE 754 floating-point standard

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Example 1Example 1

(a) Convert the decimal number -1.5 to a 32-bit floating-point number with IEEE 754 format.(b) Convert a 32-bits IEEE 754 format floating-point number 43A0C000 to the decimal number.

Solution:

(a) 1.5=1.12=1.1*20

S=1, C=E+127=127=01111111, F=1000 0000 0000 0000 0000 000(b)43A0C000=0100 0011 1010 0000 1100 0000 0000 00002

S=0, C=10000111=135=E+127, =>E=8, F= 0100 0001 1000 0000 0000 1.01000001102*28=101000001.12= 321.5

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Example 2Example 2

What decimal number is represented by this word?

Solution:符號位元為 -1 ，指數欄位為 129 ，有效數字欄位為

1.01 。

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 17 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0.5

225.11

2)25.01()1(

2)1()1(

2

)127129(1

)127(

ExponentS dSignifican

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IEEE 754單精密度表示IEEE 754單精密度表示

指數值介於 1 到 254 之間-126~127

指數和假數都是 0 的情況，可視符號位元分成正零和負零。+0 : 0 00000000 00000000000000000000000-0 : 1 00000000 00000000000000000000000

指數全為 1 ，假數全為 0 時，視符號位元代表正負無限大。+∞ : 0 11111111 00000000000000000000000-∞ : 1 11111111 00000000000000000000000

指數全為 1 ，假數部分為非 0 ，則表示 Not a Number, NaN正規化的非零值：

(-1)s * 1.F * 2e-127

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Example 3Example 3

(a) What are the smallest negative number, largest negative number, smallest positive number and the largest positive number for 32 bit normalized floating-point number.(b) What would be the range of exponential digit can represent in the IEEE 754 format?Solution:(a)最小的指數為 :-126最大的指數為 :127最小的假數為 :1.00000000000000000000000最大的假數為 :1.11111111111111111111111所以最大正值 :1.11111111111111111111111*2127

最小正值 :1.0*2-126

最小負值 :-1.11111111111111111111111*2127

最大負值 :- 1.0*2-126

(b) -126~127

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Floating-Point Arithmetic +/-Floating-Point Arithmetic +/-

Floating-point arithmetic +/-的步驟Check for zeros

Align significands (adjusting exponents)

Add or subtract significands

Normalize result

Round the number

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Example: Assume that we can store four decimal digits of the significand and two decimal digits of the exponent. 9.999x101+1.610x10-1

Step 1: 1.610 x 10-1=0.01610 x 101

Step 2: Addition of the significands 9.999 + 0.016 = 10.015 The sum is 10.015 x 101

Step 3: Normalization 10.015 x 101=1.0015 x 102

Step 4: Round the number 1.002 x 102

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• 浮點數加法運算• 範例．試著將 0.5 和 -0.4375 以二進位方式進行加法運算» 解答．

0.5 = (0.1)2

= (1.0)2 * 2-1

-0.4375 = - (0.0111)2

= - (1.11)2 * 2-2

步驟 1. 比較兩個數的指數，將指數大小調到與較大者相同： - (1.11)2 * 2-2 = - (0.111)2 * 2-1

步驟 2. 將兩數之有效數字相加： (1.0)2 * 2-1 - (0.111)2 * 2-1 = (0.001)2 * 2-1

步驟 3. 將總和正規化： (0.001)2 * 2-1 = (1.0)2 * 2-4

步驟 4. 將結果四捨五入

Floating-Point AdditionFloating-Point Addition

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Floating-Point Arithmetic x/Floating-Point Arithmetic x/

Floating-Point Arithmetic x/的步驟Check for zero

Add/subtract exponents

Multiply/divide significands (watch sign)

Normalize

Round the number

The sign of the result depends on the signs of the original operands.

All intermediate results should be in double length storage

52

Floating Point MultiplicationFloating Point Multiplication

2. Multiply the significands

4. Round the significand to the appropriatenumber of bits

Still normalized?

Start

Yes

No

No

YesOverflow orunderflow?

Exception

3. Normalize the product if necessary, shiftingit right and incrementing the exponent

1. Add the biased exponents of the twonumbers, subtracting the bias from the sum

to get the new biased exponent

Done

5. Set the sign of the product to positive if thesigns of the original operands are the same;

if they differ make the sign negative

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Floating Point MultiplicationFloating Point Multiplication

0.5*-0.4375

Solution:0.5= 0.1(2) =1.0*2-1

-0.4375 = - 0.0111(2) = -1.11*2-2

Step 1: adding the exponents-1+-2=-3-3+127=124

Step 2: Multiplying the significand 1.0 * 1.11 = 1.111.11 * 2-3

Step 3 :Rounding the product 1.110 * 2-3

Step 4 :Check the sign - 1.11 * 2-3 =-0.21875

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Floating Point Complexities

Operations are somewhat more complicated (see text)

In addition to overflow we can have “underflow”

Accuracy can be a big problem

IEEE 754 keeps two extra bits, guard and round

four rounding modes

positive divided by zero yields “infinity”

zero divide by zero yields “not a number”

other complexities

Implementing the standard can be tricky

Not using the standard can be even worse

see text for description of 80x86 and Pentium bug!

55

Accurate ArithmeticAccurate Arithmetic

若兩個值進行運算，若要減去某較小值時，需進行指數部分的對齊，因此須對 significand 進行右移，進而造成有效位元的損失。在運算過程中， significand 通常儲存在較長的 register ，因此，回存到 floating-point 格式時，會損失ㄧ些額外的位元。所以需要 guard 和 round 等兩個位元。

56

The use of guard bitsThe use of guard bits

X = 1.00…00x21, Y = 1.11…11x 20 =0.11…11x21

Y 會損失ㄧ個 bit

加入 4 個 guard bits

Y 會損失ㄧ位數

加入 2 個 guard bits

57

Rounding with Guard DigitsRounding with Guard Digits

Add 2.56x100 to 2.34x102, assuming that we have three significant decimal digits. Round to the nearest decimal number with three significant decimal digits.

Solution2.56 x 100 = 0.0256 x 102

2.34 x 102Guard bit Round bitWithout guard and round digits

58

Chapter Three Summary

Computer arithmetic is constrained by limited precision

Bit patterns have no inherent meaning but standards do exist

two’s complement

IEEE 754 floating point

Computer instructions determine “meaning” of the bit patterns

Performance and accuracy are important so there are manycomplexities in real machines (i.e., algorithms and implementation).

We are ready to move on (and implement the processor)

you may want to look back (Section 4.12 is great reading!)

59

Floating-point ArithmeticFloating-point Arithmetic

A FP operation may produce one of these conditions:

Exponent overflow

Exponent underflow

Significand underflow

Significand overfolw

60

AppendixAppendix

61

Example: C Bit FieldsExample: C Bit Fields

The following C code allocates three fields with a word labeled receiver: a 1-bit field named ready, a 1-bit field named enable, and an 8-bit field named receivedByte. It copies receivedByte into data, set ready to 0, and sets enable to 1.int data;struct{

unsigned int ready: 1;unsigned int enable: 1;unsinged int receivedByte: 8;

} receiver;…

data = receiver. receivedByte;receiver.ready = 0;receiver. Enable = 1;

What is the compiled MIPS code? Assume data and receiver are allocated to $s0 and $s1.

62

Example: C Bit Fields (Answer)Example: C Bit Fields (Answer)

The field look like this in a word

Solution 1:sll $s0, $s1, 22 #move 8-bit field to left endsrl $s0, $s0, 24 #move 8-bit field to right endandi $s1, $s1, 0xFFFE #bit 0 set to 0ori $s1, $s1, 0x0002 #bit 1 set to 1

Solution 2:srl $s0, $s1, 2andi $s0, $s0, 0x00FF

receivedByte enable ready

01291031

63

Problem: Consider a logic function with three inputs: A, B, and C.

Output D is true if at least one input is trueOutput E is true if exactly two inputs are trueOutput F is true only if all three inputs are true

Show the truth table for these three functions.

Show the Boolean equations for these three functions.

Show an implementation consisting of inverters, AND, and OR gates.

Review: Boolean Algebra & Gates

64

An ALU (arithmetic logic unit)

Let's build an ALU to support the andi and ori instructionswe'll just build a 1 bit ALU, and use 32 of them

c = a . bba

000

010

001

111

b

ac

b

ac

a c

c = a + bba

000

110

101

111

10

01

c = aa

a0

b1

cd

0

1

a

c

b

d

1. AND gate (c = a . b)

2. OR gate (c = a + b)

3. Inverter (c = a)

4. Multiplexor (if d = = 0, c = a; else c = b)

65

Selects one of the inputs to be the output, based on a control input

Lets build our ALU using a MUX:

S

CA

B

0

1

Review: The Multiplexor

note: we call this a 2-input mux even though it has 3 inputs!

66

1-bit logical unit for AND and OR1-bit logical unit for AND and OR

b

0

1

Result

Operation

a

67

Different Implementations

Let's look at a 1-bit ALU for addition:

cout = a b + a cin + b cin

sum = a xor b xor cin

Sum

CarryIn

CarryOut

a

b

a00001111

b00110011

CarryIn01010101

Sum01101001

CarryOut00010111

Inputs Outputs

b

CarryOut

a

CarryIn

68

Building a 32 bit ALU

b

0

2

Result

Operation

a

1

CarryIn

CarryOut

Result31a31

b31

Result0

CarryIn

a0

b0

Result1a1

b1

Result2a2

b2

Operation

ALU0

CarryIn

CarryOut

ALU1

CarryIn

CarryOut

ALU2

CarryIn

CarryOut

ALU31

CarryIn

The adder created by directly linking the carries of 1-bit adders is called a ripple carry adder.

69

Two's complement method: just negate b and add.

How do we negate?

Invert each bit and then add 1

A 1-bit ALU that performs AND, OR and addition on a and b or a and b:

What about subtraction (a – b) ?

0

2

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b

減法如同對運算元的反相值做加法運算而且最低有效位元本身還是有個進位輸入訊號a + (¬b) + 1 = a + (-b) = a - b減法運算ALU 0: Operation = 2, Binvert = 1, 及 CarryIn = 1 ALU 1-31: Operation = 2 及 Binvert = 1

70

Need to support the set-on-less-than instruction (slt)

remember: slt is an arithmetic instruction

produces a 1 if rs < rt and 0 otherwise

use subtraction: (a-b) < 0 implies a < b

Need to support test for equality (beq $t5, $t6, $t7)

use subtraction: (a-b) = 0 implies a = b

Tailoring the ALU to the MIPS

71

Supporting slt

Can we figure out the idea?

bit 0 的電路圖，以bit 31 的 set 值作為

less 的輸入

bit 31 的電路圖，以 + 結果的符號位元值，作為 set 的值。

Set=1 表結果為負值 => a<b 。Set=0 表結果為正值 => a>b 。

72

Seta31

0

ALU0 Result0

CarryIn

a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Binvert

CarryIn

Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

• 支援小於即設定 (slt) 指令• 範例： slt $t0, $s1, $s2

– ai ：暫存器 $s1 的位元 i– bi ：暫存器 $s2 的位元 i– 結果：假如 $s1 < $s2 0…001 否則 0…000 32 位元 ALU– 觀察：假如 $s1 - $s2 <0, 則 $s1 < $s2– 結果 0 = 加法器的符號位元– 控制訊號 / 輸入

• Operation = 3• Less 1-31 = 0• Binvert = 1• CarryIn 0 = 1• Less 0 = Set

73

• 支援條件分支指令– 假使兩個暫存器相等或假使不相等時作分支– 觀察

• if a=b then a-b = 0• if a-b = 0 then Result = 0…00

– Zero = 0 不等時– Zero = 1 相等時

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

Constructing an ALUConstructing an ALU

74

• The value of the three ALU control line and the corresponding ALU operation

Bnegate00011

Operation0001101011

andoraddsubtractset on less than

Function

Operation

CarryInBnegate

CarryOut

Result

Less

Constructing an ALUConstructing an ALU

75

ALU Symbol

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut

76

Conclusion

We can build an ALU to support the MIPS instruction set

key idea: use multiplexor to select the output we want

we can efficiently perform subtraction using two’s complement

we can replicate a 1-bit ALU to produce a 32-bit ALU

Important points about hardware

all of the gates are always working

the speed of a gate is affected by the number of inputs to the gate

the speed of a circuit is affected by the number of gates in series

(on the “critical path” or the “deepest level of logic”)

77

Is a 32-bit ALU as fast as a 1-bit ALU?

Is there more than one way to do addition?

two extremes: ripple carry and sum-of-products

Can you see the ripple? How could you get rid of it?

c1 = b0c0 + a0c0 + a0b0

c2 = b1c1 + a1c1 + a1b1 c2 =

c3 = b2c2 + a2c2 + a2b2 c3 =

c4 = b3c3 + a3c3 + a3b3 c4 =

Not feasible! Why?

Problem: ripple carry adder is slow

78

An approach in-between our two extremes

Motivation:

If we didn't know the value of carry-in, what could we do?

When would we always generate a carry? gi = ai bi

When would we propagate the carry? pi = ai + bi

Did we get rid of the ripple?

c1 = g0 + p0c0

c2 = g1 + p1c1 c2 =

c3 = g2 + p2c2 c3 =

c4 = g3 + p3c3 c4 =

Feasible! Why?

Carry-lookahead adder

79

Carry-lookahead adderCarry-lookahead adder

全加器的進位可表示成

以簡潔的符號表示成

寫成通式

)()()( 1111112 baCarryInaCarryInbCarryIn

)()()( 0000001 baCarryInaCarryInbCarryIn

)()()( 1111112 bacacbc

)()()( 0000001 bacacbc

iii

iiiii

iiiiiii

cpg

cbaba

bacacbc

)()(

)()()(1

80


因此進位輸入可表示成

使用 4 位元加法器為基本單位

0012301231232334

00120121223

0010112

0001

cppppgpppgppgpgc

cpppgppgpgc

cppgpgc

cpgc

121314153

8910112

45671

01230

ppppP

ppppP

ppppP

ppppP

81


四位元 ALU 進位公式

121314151314151415153

891011910111011112

45675676771

01231232330

gpppgppgpgG

gpppgppgpgG

gpppgppgpgG

gpppgppgpgG

0012301231232334

00120121223

0010112

0001

cPPPPGPPPGPPGPGC

cPPPGPPGPGC

cPPGPGC

cPGC

82

Can’t build a 16 bit adder this way... (too big)

Could use ripple carry of 4-bit CLA adders

Better: use the CLA principle again!

Use principle to build bigger adders

CarryIn

Result0--3

ALU0

CarryIn

Result4--7

ALU1

CarryIn

Result8--11

ALU2

CarryIn

CarryOut

Result12--15

ALU3

CarryIn

C1

C2

C3

C4

P0G0

P1G1

P2G2

P3G3

pigi

pi + 1gi + 1

ci + 1

ci + 2

ci + 3

ci + 4

pi + 2gi + 2

pi + 3gi + 3

a0b0a1b1a2b2a3b3

a4b4a5b5a6b6a7b7

a8b8a9b9

a10b10a11b11

a12b12a13b13a14b14a15b15

Carry-lookahead unit

Chapter 3 Arithmetic for Computers

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