Chapter 2 Logic Gates By Taweesak Reungpeerakul. 242-208 CH22 Contents Inverter AND Gate OR Gate NAND Gate NOR Gate XOR and XNOR Gates Integrated Circuit.

Chapter 2

Logic Gates

By Taweesak Reungpeerakul

242-208 CH2 2

Contents

Inverter AND Gate OR Gate NAND Gate NOR Gate XOR and XNOR Gates Integrated Circuit Logic Gates

242-208 CH2 3

2.1 Inverter (INV) Symbols

Truth TableIn Out

0 11 0

Timing Diagram

Logic Expression: Out = In

1

1

In Out

In

Out

0

0

1

1

242-208 CH2 4

2.2 AND Gate Symbols

Truth TableA B Out0 0 00 1 01 0 01 1 1

Timing Diagram

Logic Expression: Out = AB

AOut

B B

AOut

&A

B

A

B

Out

242-208 CH2 5

2.3 OR Gate Symbols

Truth TableA B Out0 0 00 1 11 0 11 1 1

Timing Diagram

Logic Expression: Out = A+B

AOut

B B

AOut

≥1A

B

A

B

Out

242-208 CH2 6

2.4 NAND Gate Symbols

Truth TableA B Out0 0 10 1 11 0 11 1 0

Timing Diagram

Logic Expression: Out = AB

AOut

B B

AOut

&

A

B

Out

A

B

242-208 CH2 7

2.5 NOR Gate Symbols

Truth TableA B Out0 0 10 1 01 0 01 1 0

Timing Diagram

Logic Expression: Out = A+B

A

B

AOut

B B

AOut

≥1

Out

A

B

242-208 CH2 8

2.6 XOR Gate Symbols

Truth TableA B Out0 0 00 1 11 0 11 1 0

Timing Diagram

Logic Expression: Out = A B+AB; AB

A

B

B

AOut

=1AOut

B

Out

A

B

242-208 CH2 9

XNOR Gate Symbols

Truth TableA B Out0 0 10 1 01 0 01 1 1

Timing Diagram

Logic Expression: Out = A B+AB; AB

A

B

AOut

B B

AOut

=1

Out

A

B

242-208 CH2 10

2.7 Integrated Circuit Logic Gates

CMOS: Complementary Metal-Oxide Semiconductor

Low Power Dissipation DC Power Supply: 5 V & 3.3 V CMOS Series: 74 + letter(s) +

numbersLetters:

HC, HCT = High-speed CMOS LV, LVC = Low-voltage CMOS BCT = BiCMOS (combine CMOS&TTL)

Numbers: 00= Quad 2-input NAND 02= Quad 2-input NOR 04= Hex inverter

TTL: Transistor-Transistor Logic Not Sensitive to Electrostatic

Discharge Switching Speed DC Power Supply: 5 V TTL Series: 74 + letter(s) + numbers

Letters: S = Schottky TTL LS = Low-power Schottky TTL F = Fast TTL

Numbers: 08= Quad 2-input AND 10= Triple 3-input NAND 32= Quad 2-input OR

242-208 CH2 11

2.7 IC Logic Gate (cont.) Packages DIP

IC Gate Config.

242-208 CH2 12

Performance Characteristics & Parameters

Propagation Delay Time:

tP , tPHL , tPLH

DC Power Supply: 3.3, 5V

Power Dissipation (PD)

PD = VCC (ICCH+ICCL)/2 I/O Logic LevelsTTL: VIL =0.8 V, VIH =2 V

VOL =0.4 V, VOH =2.4V

Speed-power Product (SPP)

SPP = tP*PD

Fan-out and LoadingFan-out: max # gates

connected at the output pin

Unit loads = IOH/IIH or IOL/IIL Data Sheets

242-208 CH2 13

Contents (Session 2)

Boolean Operations & Expressions Rules of Boolean Algebra DeMorgan’s Theorems Simplification Using Boolean Algebra Standard Forms of Boolean Algebra Karnaugh Map

242-208 CH2 14

2.8 Boolean Operations & Expressions Boolean Addition

is equivalent to the OR operation.

0+0 = 00+1 = 11+0 = 11+1 = 1

Boolean multiplication is equivalent to the AND operation.

0·0 = 00·1 = 01·0 = 01·1 = 1

242-208 CH2 15

2.9 Rules of Boolean Algebra

A+B = B+AAB = BAA+ (B+C) = (A+B)

+CA(BC) = (AB)CA(B+C) = AB+AC

A+0=A A·A=AA+1=1 A·A=0A·0=0 A=A

A·1=AA+A=AA+A=1A+AB=AA+AB=A+B(A+B)(A+C)=A+BC

242-208 CH2 16

2.10 DeMorgan’s Theorems

The complement of a product of variables is equal to the sum of the complements of the variables.XY = X + Y

The complement of a sum of variables is equal to the product of complements of the variables.X + Y = X ·Y

242-208 CH2 17

Examples of DeMorgan’s theorem

Ex#1: (AB+C)(BC)

= (AB+C) +(BC)

= (AB)C +(B+C)

= (A+B)C + B+C

Question: (A+B)C D

Ans: (A ·B)+C+D

Ex# 2: AB + CDE

= (AB) · (CDE)

= (A+B) · (CD+E)

= (A+B) · (CD+E)

Question: A+B+C+ DE

Ans: A B C+D+E

242-208 CH2 18

2.11 Boolean Analysis of Logic Circuits

Truth TableA B C D

(AB+C)D0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 01 1 1 1 1

A

D

C

BAB

AB+C

(AB+C)D

242-208 CH2 19

2.12 Simplification using Boolean Algebra

EX#1: AB+A(B+C)+B(B+C)

= AB+AB+AC+BB+BC

= AB + AC + B + BC

= B + AC

Question: AB+AC+ABC

Ans: A+B C

EX#2: A B C+A B C+A B C+A B C+A B C

= B C+A B C+A B C+A B C

= B C+ B C+A B C

= BC+B(C+AC)

= BC+B(C+A)

= BC+B C+AB

242-208 CH2 20

2.13 Standard Forms of Boolean Expressions

Sum-of-Products (SOP):2 or more product terms are

summedby Boolean addition such asAB+ABC+AC

Ex# 1: (A+B)(C+D) SOP form= AC+AD+BC+BD

Ex# 2: (A + B) + C= AC + BC

Standard SOP Form:all variables in the domain

appearin each product term such asABC+ABC+ABC

Ex# 1: AB+ABC standard SOP= AB(C+C)+ABC =

ABC+ABC+ABCEx# 2: B+ABC= B(A+A)+ABC = AB+AB+ABC= AB(C+C)+AB(C+C)+ABC = ABC+ABC+ABC+ABC+ABC

242-208 CH2 21

Standard Forms (cont.)

Product-of-Sum (POS):

2 or more sum terms are multiplied

such as (A+B)(A+B+C)

Standard POS:all variables in the domain

appear ineach sum term such as(A+B+C)(A+B+C)

Ex# 1: (A+C)(A+B+C) standard POS= (A+C+BB)(A+B+C)

=(A+B+C) (A+B+C) (A+B+C)Question: (A+C)(A+B) std.

POSAns: (A+B+C) (A+B+C) (A+B+C)(A+B+C)

242-208 CH2 22

Std. SOP to std. POS

Example: ABC+ABC+ABC+ABC+ABC101 011 100 001 000

3 variables23 = 8 possible combinationsRemained terms: 111, 110, 010Std. POS = (A+B+C)(A+B+C)(A+B+C)

242-208 CH2 23

2.14 Boolean Expressions and Truth Tables SOP Truth TableEX: ABC+ABC+ABC+ABC

000 010 101 110 out=1

A B C Out0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 0

POS Truth TableEX: (A+B+C)(A+B+C)

(A+B+C) 100 010 011 out=0

A B C Out0 0 0 10 0 1 10 1 0 00 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1

242-208 CH2 24

2.15 The Karnaugh Map The Karnaugh map is an array of cells in which each

cell represents a binary value of the input variables. The number of cells is 2n, n is number of variables

3 VariablesAB

C

00

10

11

01

10

BCA 0100 1011

1

0

ABCABC

ABCABC

ABCABC

ABCABC Question: 4 variables Karnaugh map

242-208 CH2 25

BCA 0100 1011

1

0

1

2.16 Karnaugh Map SOP Minimization

Ex1: Map and minimize the following std. SOP expression on a Karnaugh map: A B C+ABC+ABC+A B

C 000 001 110 100

BCA 0100 1011

1

0

1 1

11

1

11

Answer: A B+AC

AB

AC

242-208 CH2 26

SOP Minimization (cont.)

Ex2: Map and minimize the following SOP expression on a Karnaugh map: A B +ABC+A B C

110 111 010 011

BCA 0100 1011

1

0

BCA 0100 1011

1

0

1 1

11

1 1

11

Answer: B

B

242-208 CH2 27

Karnaugh Map Simplification

Grouping 1s- Each group must contain 1,2,4,8,or 16

- Each cell in a group must be adjacent to one or more cells in that same group, but all cells in the group do not have to be adjacent to each other.- Always include the largest possible number of 1s in a group- Each 1 on the map must be included in at least one group. The 1s already in a group can be included in another group as long as the overlapping groups include non-common 1s.

242-208 CH2 28

A B C

Group the 1s in each of the Karnaugh maps

BCA 0100 1011

1

0

BCA 0100 1011

1

0 1

1

1

1

1

1

1

1 1

1 AB

CD

00

10

11

01

00 01 11 10

1

1

1

1

1 1

1

1

1

1 1

BCABC

AC BC

AB

ABC D

242-208 CH2 29

A+B

BCA 0100 1011

1

0

2.17 Karnaugh Map POS Minimization

Ex1: Map and minimize the following std. POS expression on a Karnaugh map:

(A+B+C)(A+B+C)(A+B+C)(A+B+C)000 001 111 110

BCA 0100 1011

1

0

0 0

00

0 0

00

Answer: (A+B)(A+B)

A+B

242-208 CH2 30

POS Minimization (cont.)

Ex2: Map and minimize the following POS expression on a Karnaugh map:

(A+B)(A+B+C)(A+B+C)

000 001 010 011

BCA 0100 1011

1

0

BCA 0100 1011

1

00 000

Answer: A

0 000

A

242-208 CH2 31

AB

CD

00

10

11

01

00 01 11 10

00

0

0

0 0

Karnaugh maps Simplification of POS Expressions

(B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D)

0000 1000 0010 0110 1011 1001 1010

0

(A+B)

(A+C+D)

Answer: (B+D)(A+B)(A+C+D)

(B+D)

242-208 CH2 32

AB

CD

00

10

11

01

00 01 11 10

Converting Between POS and SOP Using Karnaugh Map

(B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D)

0000 1000 0010 0110 1011 1001 1010

AB

CD

00

10

11

01

00 01 11 10

0 0

0 0

0

0 0

(A+B)

(A+C+D)

Min POS: (B+D)(A+B)(A+C+D)

(B+D)

Min SOP: AB+BC+AD

0 0

0 0

0

0 0

1

1

1 11

11

1

1

AD

BC

AB

242-208 CH2 33

Mapping Directly from a Truth Table

A B C Out0 0 0 10 0 1 00 1 0 00 1 1 01 0 0 11 0 1 01 1 0 11 1 1 x

ABC

00

10

11

01

10

1

1

1

x

Out = AB+BC

242-208 CH2 34

7-segment decoding Logic

Digit D C B A a b c d e f g 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 2 0 0 1 0 1 1 0 1 1 0 1 3 0 0 1 1 1 1 1 1 0 0 1 4 0 1 0 0 0 1 1 0 0 1 1 5 0 1 0 1 1 0 1 1 0 1 1 6 0 1 1 0 1 0 1 1 1 1 1 7 0 1 1 1 1 1 1 0 0 0 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 1 0 1 1 10 1 0 1 0 x x x x x x x 11 1 0 1 1 x x x x x x x 12 1 1 0 0 x x x x x x x 13 1 1 0 1 x x x x x x x 14 1 1 1 0 x x x x x x x 15 1 1 1 1 x x x x x x x

7-segment decoding logic 7-segment display

Binary coded decimal input

A

D

C

Ba

a

de

c

gf

b gf

ed

c

b

242-208 CH2 35

DC

BA

00

10

11

01

00 01 11 10

Karnaugh Map Minimization of the Segment Logic

SOP for segment a:DC BA+DCBA+DCBA+ DCBA+DCBA+DCBA+DC

BA+DCBA

1 1

1 1

1

x x

D

1 1

1

x x x x

BCA

CA

Minimum SOP expression: D+B+CA+CA