Chapter 2: Computer-System Structures

Chapter 2: Computer-System

Structures

2

Topics

Computer System Operation I/O Structure Storage Structure Storage Hierarchy Hardware Protection General System Architecture

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Computer-System Operation

CPU and device controllers connected through a common bus that provides access to shared memory.

Each device controller is in charge of a specific type of device.

§2.1

disk disk printer

Diskcontroller

Printercontrollercpu

Tape-drivecontroller

Tape drives

System bus

Memory controller

memory

裝置控制器

4

The CPU and the device controllers can execute concurrently, competing for memory cycles.

A memory controller synchronizes access to the memory.

Computer-System Operation

disk disk printer

Diskcontroller

Printercontrollercpu

Tape-drivecontroller

Tape drives

System bus

Memory controller

memory

同步化

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Bootstrap program

When powered up or reboot, an initial program, called bootstrap program, initializes the system, including:– CPU registers– Device controllers– Memory contents– Load the OS and start it

The bootstrap program locate and load the OS kernel into memory.

The OS starts executing the first process, such as

“init,” and waits for some event to occur.

Interrupt

拔靴帶 (啟動帶引程式 )

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Interrupt Hardware may trigger an interrupt at any

time by sending a signal to the CPU, usually by way of the system bus.

Software may trigger an interrupt by executing a special operation called a system call.

For example: the completion of an I/O operation, division by zero, invalid memory access, and a request for some OS service.

Different service routines are provided for different type of interrupts.

中斷

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Interrupt Handling

When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a fixed location.

The fixed location usually contains the starting address where the service routine for the interrupt is located.

The interrupt service routine executes; on completion, the CPU resumes the interrupted computation.

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Interrupt Time Line For a Single Process Doing Output

CPU

I/Odevice

User Processexecuting

I/O interruptprocessing

Idle

transferring

I/Orequest

Transferdone

I/Orequest

Transferdone

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Common Functions of Interrupts

Interrupts transfers control to the interrupt service routine, generally through the interrupt vector, which contains the addresses of all the service routines.

Interrupt architecture must save the address of the interrupted instruction for returning to normal execution.

Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.

A trap is a software-generated interrupt caused either by an error or a user request.

An operating system is interrupt driven.

中斷向量

陷阱

功能解除

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I/O Structure Depending on the controller, there may

be more than one attached device. For example: the small computer-

systems interface (SCSI) controller can have seven or more devices attached to it.

The device controller maintains some local buffer storage and a set of special-purpose registers.

§2.2

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I/O Interrupts

To start an I/O operation:– CPU loads appropriate registers within

the device controller– Device controller then examines the

contents of these registers to determine what action to take.

– Once the action is complete, the device controller informs the CPU that it has finished its operation by triggering an interrupt.

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|

|

|

||

|

BUS

CharacterTransmitted

Data buffer register

Controlbits

Control/status register

Device

Device

Controller

|

|

Device Controller

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Example Control/Status Register

. . . . .0/1 . . . .0/1 . . . .0/1 . . . . .

"OPERATION COMPLETE" flag - 1 means operation is complete

"READ" flag-1 means controllershould read a character from the device

"WRITE" flag-1 means controllershould write a characterto the device

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I/O Methods

Once the I/O is started, two courses of action are possible: Synchronous I/O Asynchronous I/O

user

kernel

Requesting processwaiting

Device driver

Interrupt handler

hardware

Data transfer

time

(a)

Requesting process

Device driver

Interrupt handler

hardware

Data transfer

time

(b)

user

kernel

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Synchronous I/O

After I/O starts, control returns to user program only upon I/O completion. – Waiting for I/O may be accomplished by:

wait instruction idles the CPU until the next interrupt

wait loop Loop:jmp Loop

– At most one I/O request is outstanding at a time, no simultaneous I/O processing.

– Also excludes the possibility of overlapping useful computation with I/O.

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Asynchronous I/O After I/O starts, control returns to user

program without waiting for I/O completion. The I/O then can continue while other system operations occur.– A System call (request to the operating system), is

needed to allow user to wait for I/O completion.– In order to keep track of many I/O requests at the

same time, Device-status table contains entry for each I/O device indicating its type, address, and state.

– Operating system indexes into I/O device table to determine device status and to modify table entry to reflect the occurrence of the interrupt.

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Device-Status Table

device: card reader 1Status: idle

Device: line printer 3Status: busy

Device: disk unit 1Status: idle

Device disk unit 2Status: idle

Device: disk unit 3Status: busy

Request forline printeraddress:38546Length:1372

Request fordisk unit 3

File: xxxOperation: readAddress: 43046Length: 20000

Request fordisk unit 3

File: yyyOperation: writeAddress: 03458Length: 500

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Input Device

Interactive systems may allow users to type ahead.

Interrupts may occur, signaling the arrival of characters from the terminal, while the device-status block indicates that no program has requested input from this device.

A buffer must be provided to store the typeahead characters until some program wants them.

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Direct Memory Access (DMA) Structure

Used for high-speed I/O devices able to transmit information at close to memory speeds.

Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.

Only one interrupt is generated per block, rather than the one interrupt per byte.

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Storage Structure

Main memory (RAM)– only large storage media that the CPU can access directly.

It is not possible for programs and data to reside in main memory permanently– Main memory is usually too small– Main memory is a volatile storage device

Secondary storage – extension of main memory that provides large nonvolatile storage capacity.

Magnetic disks – provide storage of both programs and data. Most programs are stored on a disk until they are loaded into memory.

§2.3

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Von Neumann Machine

A typical instruction-execution cycle will first fetch an instruction from memory and will store it in the instruction register.

It is then decoded and cause operands to be fetched from memory and stored in some internal register.

After the instruction on the operands has been executed, the result may be stored back to memory.

抓取

解碼

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Cycle and Clock

Cycle: A basic unit of computation, one period of a computer clock.

Each instruction takes a number of clock cycles.

Clock rate: The fundamental rate in cycles per second at which a computer performs its most basic operations such as adding two numbers or transfering a value from one register to another.

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Main Memory

Main memory and the registers built into the processor itself are the only storage that the CPU can access directly.

To allow convenient access to I/O devices, memory-mapped I/O set aside ranges of memory addresses and mapped to the device registers.

Read and writes to these memory addresses cause the data to be transferred to and from the device registers.

§2.3.1

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Memory-mapped I/O

'X'

'X''X*

Character sent to thebus and then to thecontroller register

Driver movescharacter tofixed locationin the addressspace

Realmemory

Physicaladdressspace

記憶體對照

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Memory-mapped I/O

Appropriate for devices that have fast response times, such as video controllers.– In PC, each screen location is mapped to

a memory location. Displaying text on the screen is almost as easy as writing the text into the appropriate memory-mapped locations.

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Memory-mapped I/O

Also convenient for devices such as the serial and parallel ports used to connect modems and printers.– CPU transfers data through these kinds

of devices by reading and writing a few device registers, called an I/O port.

– CPU writes data to the data register and uses control register to signal the readiness of the data

埠

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Pseudocode for Writing X

Move contents of location m to location d.Set WRITE flag in location d+1 to 1.Move contents of location d+1 to a CPU register.Test the OPERATION COMPLETE flag in the register.If flag is 0, branch to LOOP: {WRITE operation is not complete}.... next instruction....{WRITE operation is complete}

LOOP:

Assume: X is in location m Data buffer register is in location d Control/status register is in location d+1

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Writing X Using Memory Mapped I/O

Physicaladdressspace

Location m

'X*

Location d

Location d+1

'X*

...0/1...0/1..

1. Moves 'X' to location d Real

memoryDataBus

3. 'X' goes to the bus

Any reference to location d+1 is areference to the control/statusregister

Driver seesthese flags aspart of memory

6.Test "OPERATION COMPLETE" flag

2.Set "WRITE"flag to 1

4. 'X' goesto the databuffer register

7. "OPERATION COMPLETE" flag is set to 1 after 'X' goes to the device

"WRITE" flag set to 1as a result of step 1

Device

Controller

Data bufferregister

'X*

...0/1...0/1..

Control/Statusregister

5. 'X' goes to the device

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Busy-waiting

The biggest drawback: the driver must continually test a flag -- monopolizes the CPU for status checking.

Unacceptable when other processes are waiting

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Programmed I/O (PIO)

The CPU uses polling to watch the control bit, constantly looping to see whether the device is ready

Interrupt driven I/O The CPU does not poll the control bit,

but instead receives an interrupt when the device is ready for the next byte.

程式控制

中斷驅動

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Activities with programmed I/O

t1t2

Controllerwrites character

Process requestscontroller to writecharacter

Time

CPU spends allthis time checkingthe control/statusregister - noother processmakes progress

Process detectsthat character has been written

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Activities with interrupt driven I/O

t1t2

Controllerwrites character

Process requestscontroller to writecharacter

Time

CPU spends thistime working onanother process

Controller interruptsCPU, indicating thatcharacter has beenwritten

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Interrupt Line

A CPU can detect a controller interrupt through an interrupt line

Normally the CPU tests the interrupt line during the instruction cycle

CPU Controllerinterrupt line

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Magnetic Disks Tracks, Sectors, Cylinders. 1 Kilobyte = 1024 bytes

1 Megabyte = 10242 bytes1 Gigabyte = 10243 bytes

Transfer rate = the rate at which data flow between the drive and the computer.

Positioning time (random-access time) = time to move the disk arm to the desired cylinder (seek time) + time for the desired sector to rotate to the disk head (rotational latency).

§2.3.2

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Moving-Head Disk Mechanism

Track t

Sector s

Cylinder c

platter

spindleRead-writehead

actuator

arm

rotation

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Storage Hierarchy Storage systems organized in hierarchy

according to– Speed– Cost– Volatility

The design of a complete memory system must balance all these factors: uses only as much expensive memory as necessary, while providing as much inexpensive, nonvolatile memory as possible.

§2.4

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Storage-Device Hierarchy

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Caching Needed information is copied into faster

storage system – the cache– temporarily.

Main memory can be viewed as a fast cache for secondary storage.

When a piece of information is needed, first check whether it is in the cache. If it is, use it directly. If it is not, use info from the main storage system and put a copy in the cache for later usage.

§2.4.1緩衝儲存

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Internal programmable registers, such as index registers, provide a high-speed cache for main memory.

The programmer implements the register-allocation and replacement algorithms to decide which info to keep in registers and which to keep in main memory.

There are also caches implemented totally in hardware.– Instruction cache– Data cache

Caching

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The movement of information between levels of a storage hierarchy may be either explicit or implicit.

For instance, – data transfer from cache to CPU and

registers is usually a hardware function, with no OS intervention.

– Transfer of data from disk to memory is usually controlled by the OS.

Caching

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Coherency In a hierarchical storage structure, the same

data may appear in different levels of the storage system.

For example: integer A in file B is to be incremented by 1.– Disk –> main memory –> cache –> internal

register. In multitasking environment, must ensure

that, if several processes wish to access A, then each of these processes will obtain the most recently updated value of A.

§2.4.2凝聚性、一貫性

42

It is more complicated in multiprocessor environment where a copy of A may exist simultaneously in several CPU’s local cache.

Must make sure that an update to the value of A in one cache is immediately reflected in all other caches where A resides – cache coherency.

Coherency

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Hardware Protection

OS sharing system resources among several programs simultaneously may cause processes to be adversely affected by a bug in one program.

OS must ensure that an incorrect (or malicious) program cannot cause other programs to execute incorrectly.

If a user program fails, the hardware will trap to the OS.

§2.5

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Dual-Mode Operation

Sharing system resources requires protecting the operating system and all other programs and their data from any malfunctioning program.

Provide hardware support to differentiate between at least two modes of operations.1.User mode – execution done on behalf of a user.

2.Monitor mode (also supervisor mode or system mode) – execution done on behalf of operating system.

§2.5.1雙模式

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Dual-Mode Operation Mode bit added to computer hardware to indicate

the current mode: monitor (0) or user (1). When an interrupt or fault occurs hardware

switches to monitor mode.

Privileged instructions can be issued only in monitor mode.

monitor user

Interrupt/fault

set user mode

享有特權的

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Dual-Mode Operation

The lack of a hardware-supported dual mode can cause serious shortcomings in an OS.– MS-DOS was written for Intel 8088,

which has no mode bit, and therefore no dual mode.

– Pentium provide dual-mode operation. As a result, NT and OS/2 provide greater protection for the OS.

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I/O Protection

By defining I/O instructions to be privileged instructions, users cannot issue I/O instructions directly; they must do it through the OS.

Must ensure that a user program could never gain control of the computer in monitor mode (Ex: a user program that, as part of its execution, stores a new address in the interrupt vector).

§2.5.2

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Memory Protection Must provide memory protection at least for

the interrupt vector and the interrupt service routines.

In order to have memory protection, add two registers that determine the range of legal addresses a program may access:– base register – holds the smallest legal physical

memory address.– Limit register – contains the size of the range

Memory outside the defined range is protected.

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A Base And A limit Register Define A Logical Address Space

0

256000

420940

300040

880000

1024000

300040

120900

Base register

Limit register

monitor

Job 1

Job 2

Job 3

Job 4

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Protection Hardware

When executing in monitor mode, the operating system has unrestricted access to both monitor and user’s memory.

The load instructions for the base and limit registers are privileged instructions.

base

CPUaddress yes yes

no no

memoryTrap to operating systemMonitor – addressing error

≧ ＜

Base limit

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CPU Protection Timer – Prevent a user program form getting

stuck in an infinite loop, the computer will be interrupted after specified period to ensure operating system maintains control.– Timer is decremented every clock tick.– When timer reaches the value 0, an interrupt

occurs. Timer commonly used to implement time

sharing by calculating the time slice before each context switch (see Chapter 4).

Time also used to compute the current time.

§2.5.4

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General-System Architecture Given that the I/O instructions are privileged,

how does the user program perform I/O? System call – the method used by a process

to request action by the operating system.– Usually takes the form of a trap to a specific

location in the interrupt vector.– Control passes through the interrupt vector to a

service routine in the OS, and the mode bit is set to monitor mode.

– The monitor verifies that the parameters are correct and legal, executes the request, and returns control to the instruction following the system call.

§2.6

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Use of A System Call to Perform I/O

Trap to monitor

ResidentmonitorCase n

read Perform I/O

ReturnTo user

User program

System call n