Chapter 16: Design for Testability Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-1 Chapter 16: Design for Testability Department of Electronic Engineering National Taiwan University of Science and Technology Prof. Ming-Bo Lin
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Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-1
Chapter 16: Design for Testability
Department of Electronic Engineering
National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-2
Syllabus
ObjectivesFault DetectionTest vector generationTestable circuit designBoundary-scan standard
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-3
Objectives
After completing this chapter, you will be able to:Describe various fault modelsUnderstand the fundamentals of fault detectionUnderstand the difficulties of sequential circuit testsUnderstand the basic principles of test vector generationDescribe the basic principles of testable circuit designUnderstand the principle of boundary scan standard (IEEE1149.1)
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-4
Syllabus
ObjectivesFault Detection
Fault modelsFault detectionDifficulty of sequential circuit test
Test vector generationTestable circuit designBoundary-scan standard
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-5
Terminology Definition
What is a defect?What is an error?What is a fault?
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-6
Fault Models
Stuck-at-0 faultStuck-at-1 faultBridge fault
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-7
Fault Models
Stuck-open faultStuck-closed (stuck-on) fault
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-8
Fault Models
Fault equivalenceFault collapseFault coverage
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-9
Fault Detection
Controllability Observability
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-10
Fault Detection
A testable faultAn untestable fault
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-11
Fault Detection
An example of complete test set
Test vectors are {(0,1), (1,0), (1,1)}
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-12
Difficulty of Sequential Circuit Test
A homing sequenceA preset homing sequence
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-13
Difficulty of Sequential Circuit Test
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-14
Difficulty of Sequential Circuit TestA transfer sequence A circuit is strongly connectedSo what are the difficulties of testing sequential circuits?
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-15
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-20
Fault Simulation
The fault simulation process is repeated until:All faults are coveredAt least an acceptable number of faults are covered, orSome predefined stopping point is reached
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-21
Fault Simulation
Types of fault simulationThe row methodThe column method
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-22
Fault Simulation
The row method
Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,1,0)}.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-23
Fault Simulation
The column method
Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1), (1,1,0)}.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-24
Ad hoc testingScan-path methodsBuilt-in self test (BIST)
Boundary-scan standard
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-34
Ad hoc Testing
Basic principles are to increase observabilitycontrollability
MethodsProviding more control and test points Using multiplexers to increase the number of internal control and test points Breaking feedback paths Using state registers to reduce the additional of I/O pins required for testing signals
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-35
Ad hoc Testing
An example of exhaustive test
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 16-36