Chapter 11: Timer Subsystem Esteban Rodriguez-Marek Eastern Washington University Department of Engineering & Design.

Chapter 11: Timer Subsystem

Esteban Rodriguez-MarekEastern Washington University

Department of Engineering & Design

2 of 65

Chapter 11: Timer SUbsystem

Overview The programmable timer subsystem of the

68HC11 can be used in any situation where an accurate time interval or measurement is required.

The heart of the subsystem is a free running counter (TCNT), which increments every integral number of clock cycles, depending on configuration.

Has three major functions: output compare input capture pulse accumulator

3 of 65


Timer Subsytem Functions Output compare – continually

compares the stored value in an output compare register with the value in TCNT and when equal, asserts a change in output.

Input capture – used to measure pulse widths, frequency, speed, or any other quantity of a periodic signal.

Pulse accumulator – an 8-bit counter that can count input edges or measure pulse width (depending on the operating mode used).

4 of 65


Registers The timer subsystem has more registers

than any other. They are: Control Registers:

TCTL1 – timer control register 1 (Output compare)

TCTL2 – timer control register 2 (Input capture)

TMSK1 –Main timer interrupt mask register 1 (output compare and input capture interrupt)

5 of 65


Registers

TMSK2 – Miscellaneous timer interrupt mask register 2 (Timer overflow and PA interrupts)

PACTL – pulse accumulator control register

OC1M – action mask register (dedicated to OC1)

OC1D – action data register (dedicated to OC1)

6 of 65


Registers Data Registers:

TCNT – timer counter register TIC1 through TIC3 – timer input

capture registers 1, 2, and 3 TOC1 through TOC5 – timer output

compare registers 1, 2, 3, 4, and 5 PACNT – pulse accumulator count

register

7 of 65


Registers Status Registers:

TFLG1 – Main timer interrupt flag register 1 (Output compare and input capture status flag)

TFLG2 – Miscellaneous timer interrupt flag register 2 (Timer overflow and PA status flag)

8 of 65


Pins Each of the port A pins has a

corresponding timer subsystem function. Some have two possible functions. If the timer function is not required

(or not enabled), the corresponding port A pin can be used as a general purpose input or output pin depending on the specific pin.

9 of 65


Pins The following is a list of the port A pins and

their designated timer functions: PA0 – input capture 3 (IC3) PA1 – input capture 2 (IC2) PA2 – input capture 1 (IC1) PA3 – output compare 5 or 1 (OC5/OC1) PA4 – output compare 4 or 1 (OC4/OC1) PA5 – output compare 3 or 1 (OC3/OC1) PA6 – output compare 2 or 1 (OC2/OC1) PA7 – pulse accumulator input or output

compare 1 (PAI/OC1)

10 of 65


MC68HC11E9 Block diagram

11 of 65


Registers

12 of 65


Registers

13 of 65

Chapter 11: Timer SUbsystemThe Free-Running Counter

(TCNT) The heart of the timer subsystem is the 16-bit

timer counter register (TCNT) at address $100E, $100F.

For every set of clock pulses from the system clock (E), the register increments.

A program can read it at any time to get timing information.

The timer subsystem uses TCNT as a timing reference for most of its operations.

A program cannot write to the TCNT register. Only the system clock can change the register contents.

14 of 65


(TCNT)

The TCNT register is known as a free-running counter.

When the MCU is reset, register TCNT is also reset to zero. After this it increments at a fixed rate.

A prescaler is available to slow down the count rate by a factor of 1, 4, 8, or 16, depending upon the configuration.

15 of 65


(TCNT)

The prescaler can only be set once in a program, and it must be done within the first 64 system clock cycles.

Example: (Set prescaler for a factor of 8.)

LDX #TMSK2;load address of TMSK2 register

BCLR $00,X,$01 ;PR0 = 0 (Mmm’-> M)BSET $00,X,$02 ;PR1 = 1(M+mm -> M)

16 of 65


(TCNT) After executing the instructions in the example

above, the free-running counter (TCNT) will increment every eight clock cycles.

If the timer overflow interrupt enable bit (TOI) in register TMSK2 is set, an interrupt is also asserted.

If it is not set, the MCU will have to poll flag register TFLG2 to determine if an overflow has occurred.

An overflow occurs every time the register counts from $FFFF to $0000. This causes the timer overflow flag (TOF) in register TFLG2 to set.

17 of 65


(TCNT)

18 of 65


Clearing Timer Flags The flag bits in TFLG1 and TFLG2 are

cleared by writing a 1 to the bit to be cleared.

ex) LDAA #80 ; sequence to clear TOF STAA TFLG2,X ex) Suppose TFLG2 has $A0 BCLR TFLG2,X,$7F ; it will clear TOF

; (M(mm)’ M) ex) Suppose TFLG2 has $A0 BSET TFLG2,X,$80 ; (M+mm M)

- Bit7 and 5 in TFLAG will be cleared. - it is NOT a good way to clear flag bits.

19 of 65


Output Compare The output compare module can be used to

generate waveforms such as square waves, variable-duty-cycle waves (PWM), and single pulses.

It can also trigger an execution sequence to begin at a specified time without generating an external output.

Output compare functions can be used to generate time delays that do not depend on executing a program loop a certain number of times.

An output compare function can generate repetitive signals such as a flashing light.

The ability to do PWM can be used to implement a simple D/A converter using only a few extra components.

20 of 65


Output CompareNote : T0C1~TOC5 are at $1016 ~ $101F

21 of 65


Output CompareNote : OC2 ~OC5 are assigned into PA6 ~ PA3 respectively.

22 of 65


Sequence of Operations

There are five output compare functions and pins labeled OC1 to OC5.

Each has an associated 16-bit timer output compare register labeled TOC1 to TOC5 ($1016 to $101F), respectively.

A software instruction writes to the output compare register TOCx. When timer counter register TCNT counts up to the value stored in an output compare register, the MCU automatically sets the associated output compare flag (OcxF) in timer flag register TFLG1. This event is called a successful compare.

23 of 65



A successful compare will occur every time a match occurs between an output compare register and the counter register.

To write a value to an output register, use a double-byte instruction not two single-byte instructions. The latter could cause an erroneous compare.

Ex) LDX #TOC5STD $00,X

24 of 65


General Timer Software Configure the control registers (and

enable the subsystem) Write to the data register if required. Wait for a flag to set. Clear the flag. Read from or write to a data register

as required. Repeat if desired.

25 of 65


One-Shot Pulse Example This example will generate a pulse on pin

OC2 that will be high for 10ms. OC2 is also port A, pin 6 (PA6). Once a port A

pin is configured for timer use, it cannot be used as a general-purpose pin.

Initially, the software sets pin PA6/OC2 high, which is the start of the pulse.

It then configures OC2 to drive the output low upon a successful compare.

Finally, the software writes a value to the output compare register TOC2 that represents the count that will be in TCNT at the end of the 10ms pulse.

26 of 65


One-Shot Pulse Example The value to be stored in TOC2 is calculated

based on a 2MHz clock frequency and a timer prescale of 1.

Each clock cycle takes 0.5s so a 10ms pulse will require 20,000 cycles.

By the time TOC2 is written to, seventeen clock cycles have elapsed, meaning that the pulse has been on that long already.

Therefore, the value that should be written to TOC2 is the current value of TCNT plus 19,983 (20,000 – 17).

27 of 65


One-Shot Pulse Example An alternative way to initially set pin OC2

high is to use the timer compare force register (CFORC).

To force a compare, a one is written to the corresponding bit (FOCx) in the CFORC register. In this case, writing a one to FOC2 would force a compare action for OC2 (i.e., it makes OC2 changed even though a compare action is NOT performed).

28 of 65


An example (1)

* With E = 2 MHz and prescale = 1* Drive one-shot high pulse for 10 ms* REMINDER, see template listing in Appendix D, Cross Assembly

REGBAS EQU $1000 ;Starting address for register ;block

PORTA EQU $00 TCNT EQU $0ETOC2 EQU $18TCTL1 EQU $20TFLG1 EQU $23PWIDTH EQU 20000

29 of 65


An example (2)ORG $100LDD TCNT,X ;prevent premature STD TOC2,X ;OC2 compare

PULSE BSET PORTA,X $40 ;drive PA6/OC2 high (M+mm ->M)

LDAA #$80 ;configure OC2 to drive output lowSTAA TCTL1,X ;and disconnect other OCx's

LDAA #$40 ;clear OC2F if setSTAA TFLG1,X

LDD TCNT,X ;arm TOC2 for 10-ms triggerADDD #PWIDTH-17STD TOC2,X

30 of 65


An example (3)PULSE1 BRCLR TFLG1,X $40 PULSE1 ; ?Mmm=0

;wait for trigger by* ;polling for OC2F high* ;now output OC2

lowBCLR PORTA,X $40 ; Mmm’ ->M

;clear latch for PA6

LDAA #$40 ;then clear OC2FSTAA TFLG1,X ;before

BCLR TCTL1,X $80 ;disconnecting OC2BRA * ;end for now

31 of 65


Input Capture An input capture function records the

time (TCNT value) when an active transition occurred.

The active transition can be rising, falling, or either. This makes it useful for applications the require measuring the time between edges.

By using software, the MCU application program can calculate period, frequency, or any other related quantity such as speed.

32 of 65


Input Capture Referring to the diagram in next slide, it

can be seen how the MCU software can find the waveform period by subtracting two successive edge times to find their difference.

It can then calculate frequency by dividing 1 by the period. Recall that frequency is the inverse of period.

The pulse width is the difference between the TCNT values when the edges occurred.

33 of 65


Input Capture

Note : IC3 ~IC1 are assigned into PA2 ~ PA0 respectively. TIC1~TIC3 are at $1010 ~ $1015.

34 of 65


Sequence of Operations When an edge is detected by the input

capture pin, the value of the timer counter register (TCNT) is latched into the corresponding input capture register (TICx).

The function also sets the input capture flag (ICxF) in timer flag register 1 (TFLG1).

If the corresponding input capture interrupt enable bit (ICxI) in timer mask register 1 (TMSK1) is set, the detected edge also generates an interrupt.

35 of 65



Typically, the application program reads the value in the timer input capture register (TICx). It then clears flag ICxF so as to rearm itself to capture the next edge.

To detect whether a flag sets, the program can poll register TFLG1 or respond to an interrupt.

36 of 65

Chapter 11: Timer SUbsystemAn example for input

capture operation (1)* Measure time between a rising and a falling edge on IC1.

RISETIME EQU $10PULSEWIDTH EQU $12

ORG $100

LDAA #$10 ;config. to capture rising edge

STAA TCTL2,XLDAA #$04 ;clear flag IC1F if setSTAA TFLG1,X

37 of 65

Chapter 11: Timer SUbsystemAn example for input

capture operation (2)

* wait for rising edgePOLLRISE BRCLR TFLG1,X $04 POLLRISE

LDD TIC1,X ;store the rise timeSTD RISETIMELDAA #$20 ;config. to capture falling

edgeSTAA TCTL2,XLDAA #$04 ;clear flag IC1FSTAA TFLG1,X

* wait for falling edgePOLLFALL BRCLR TFLG1,X $04 POLLFALL

LDD TIC1,X ;read the fall timeSUBD RISETIME ;width = fall - riseSTD PULSEWIDTH ;store widthBRA * ;stop here for now

38 of 65


Pulse Accumulator The pulse accumulator is an 8-bit

counter that can count input edges or measure pulse width depending on the operating modes used.

It is not as accurate as the input capture functions for pulse-width measurement.

39 of 65


Pulse Accumulator However, the pulse accumulator can

identify a wide pulse from a narrow pulse much more easily.

This makes it useful for decoding signals that use pulse width as part of their codes.

40 of 65


Function Description The pulse accumulator has one input pin

(PAI) at port A pin PA7. This is a bidirectional pin whose

direction is configured by the data direction for PA7 bit (DDRA7) in the pulse accumulator control register (PACTL).

DDRA7

PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0$1026PACTL

41 of 65


Function Description

Normally, bit DDRA7 is zero when using the pulse accumulator. However, pin PA7 still drives the pulse accumulator if bit DDRA7 is set.

Control register PACTL has a pulse accumulator system enable bit (PAEN) which must be logic 1 in order to use the function.

42 of 65


Function Description Two other bits, pulse accumulator mode

(PAMOD) and pulse accumulator edge control (PEDGE), establish the function’s operating modes. PAMOD=0 ; External event counting mode

(pin acts as clock) PAMOD=1 ; Gated time accumulation mode

(pin acts as clock enable for E divided by 64 clock. In this mode, PACNT is used as a timer. PACNT is incremented every 64th E-clock cycle.)

43 of 65


Function Description The pulse accumulator count register

(PACNT) can be read and written to. This means that the pulse accumulator can start counting from a preset count instead of zero.

The function also makes use of registers TFLG2 and TMSK2.

44 of 65


Function Description PA edge interrupt activates during a

pulse edge. Edge may be rising or falling:

PEDGE = 0: Falling PEDGE = 1: Rising

Flag in Pulse Accumulator Input Edge Flag bit PAIF (TFLG2).

Enable bit for interrupt: PAII (TMSK2)

45 of 65


Function Description PA overflow interrupt activates

whenever counter PACNT counts past $FF towards $00.

Pulse accumulator overflow bit (PAOVF) is in TFLG2.

Enable bit (PAOVI) is in TMSK2.

46 of 65


Function DescriptionNote : PAI is the pin, PA7

47 of 65


Event Counting: Short counts

For counting short (i.e. <256) counts: Write 2’s complement of preset number of

edges to PACNT Ex. IF we want to count $18 edges, write

$E8 ($18 = 00011000, two’s complement is 11101000 = $E8)

When we reach $E8 + $17 = $FF one more count will set the PAOVF

48 of 65


Example (short counts) (1)*INITPA: initializes PA for counting rising edges,* but does not enable interruptsINITPA

pshx ;preserves IXldx #REGBBAS ;point to reg blkbset PACTL,X $50 ;PAEN=PEDGE=1pulx ;restore IXrts

49 of 65


Example (short counts) (2)*CNTSPA: Counter (short) for PA. Loads PA function with

preset and enables it for PAOVF overflow interruptCNTSPA

psha ;preserve registersbclr tflg2,x $DF ;Clear PAOVF (i.e. set it to 1)bset tmsk2,x $20 ; paovi = 1nega ;two’s complementstaa pacnt,x ;store to PA countercli ;enable interruptspula ;restore regsrts

50 of 65


Example (short counts) (3)*RPAOV: Interrupt handler for PA overflowRPAOV

ldx #REGBASbclr tmsk2,x $20 ; paovi = 0bclr tflg2,x $DF ; Clear PAOVFjsr go_to_desired_subroutinerts

51 of 65

Chapter 11: Timer SUbsystemEvent Counting: Long

counts For counting long (i.e. >256) counts we

need to keep track of PA overflows. Ex: WE need to count $302 events.

Store $FE (complement of $02) in PACNT. After 2 events have occurred, an overflow

occurs. After that, we need to count 3 more

overflows. Use D reg: A will have multiples of 256,

B will have remainder

52 of 65


Example: Long counts (1)

OVCNT rmb 2; A value needs to ;be stored here to check how many ;events need to be counted

org $180;Note INITPA from previous example;is also used in this example

53 of 65


Example: Long counts (2)CNTLPA;Counter for long PA. Loads PA with preset values and ;enables it for overflow interrupt; ACCD = preset, max = 65535;OVCNT = overflow count

psha ;preserve regspshbbclr tflg2,x $DF ;clear PAOVFbset tmsk2,x $20 ;paovi=1tstb ;test for remainder countbeq NOINC ;if none, skip incainca

54 of 65


Example: Long counts (3)NOINC

negb ;two’s complement remainter; and store it in PACNT

stab pacnt,xstaa OVCNT ;Store overflow countcli ;enable interruptspulb ;restore regspularts

55 of 65


Example: Long counts (4)RPAOV;Handles PA overflow by decrementing count. Main app;program checks if preset count is achieved by checking;RAM variable OVCNT for zero

ldx #regbas ;point to regsbclr tflg2,x $DF ;clear paovfdec OVCNT ;decr. overflow countrti

56 of 65


Gated Time Accumulation Set PAEN = PAMOD = 1 PA now counts up once every 64 clock

cycles when PAI is active. It does not count edges. PEDGE specifies input that will inhibit

time accumulation: PEDGE = 0: Counter will not increment if PAI

is low PEDGE = 1: Counter will not increment if PAI

is high

57 of 65


Gated Time Accumulation If PAI changes level, PACNT stops

counting. It will resume from the previous value

when the input returns to enabling level. Flag and interrupt bits work identically to

event counting mode.

58 of 65


Example: PW discriminator Objective: Discriminate a narrow pulse from a wide

one. Do this by writing a value to PACNT that is halfway

between narrow and wide pulse widths. If narrow arrives, counter accumulates and trailing

edge is detected before overflow occurs. When wide arrives, counter accumulates and

overflows before trailing edge. Thus, if PAIF (edge flag) sets first, pulse was narrow. If PAOVF (Overflow flag) sets first, pulse was wide.

59 of 65


PW discriminator code (1) Specs:

Logic 1 = 0.25ms (narrow) Logic 0 = 0.5ms (wide)

Halfway = 0.375ms PACNT counts every 64 cycles, or 32us. 375us/32us = roughy 12 = $0C Two’s complement of $12 is $F4 System will use a low pulse for each bit (i.e.

idle line is high).

60 of 65


PW discriminator code (2)

ORG $180STBLK equ $20ENDBLKequ $2F;stblk and endblk: 1st and last add. of block ;where data is stored;program will read data and store bits in the ;above locations

61 of 65


PW discriminator code (3)

INPApshapshbpshxpshy ;preserve regsldy #STBLK ;initialize pointer to dataldx #regbas ;reg block

62 of 65


PW discriminator code (4);config. PA in gated modeldaa #%01110000staa pactl,x ;low level enables accumulationldaa #$30 ;enable local interruptsStaa tmsk2,xStaa tflg2,x ;and clear flags if setLdaa #$F4 ;preset pulse accumulatorStaa pacnt,x

NEXTBYTEldab #8 ;loop from 8:1clr 0,y ;clear data byte

63 of 65


PW discriminator code (5)NEXTBIT

cli ;enable interrupt and wait forwai ;either interrupt to shift in a bitdecb ;decrease bit countbne NEXTBIT ;until 8 bits shifted ininy ;increase byte pointercpy #ENDBLK ;until last byte readbne NEXTBYTEsei ;mask interruptspuly ;recover registerspulxpulbPularts

64 of 65


PW discriminator code (6)RPAO;PA overflow handler;if overflow occurred first, bit = 0

ldaa 0,y ;get old data byteclc ;shift in a zero bit (clc = clear carry)rola ;rotate carry bit instaa 0,y ;and store it

WAIT1 ;inhibit rising edge interruptbrclr tflg2,x $10 WAIT1bclr tflg2,x $CF ;clear flags PAOVF and PAIFldaa #$F4 ;restore acc. presetstaa pacnt,xrti

65 of 65


PW discriminator code (7)RPAIE;PA edge detection handler;if rising edge occurred first, bit = 1

ldaa 0,y ;get old data bytesec ;shift in a one bit (sec = set carry)rola ;rotate carry bit instaa 0,y ;and store itbclr tflg2,x $CF ;clear flags PAOVF and PAIFldaa #$F4 ;restore acc. presetstaa pacnt,xrts

Chapter 11: Timer Subsystem Esteban Rodriguez-Marek Eastern Washington University Department of Engineering & Design.

Documents