Chapter 11 Software -Based Self -Testing€¦ · System-on-Chip Test ArchitecturesEE141 Ch. 11 –Software-Based Self-Testing -P. 22 Component Tests for PARWAN ALU Test Pattern alu_code

EE141System-on-Chip Test Architectures Ch. 11 – Software-Based Self-Testing - P. 1

Chapter 11Chapter 11

SoftwareSoftware--Based SelfBased Self--TestingTesting



�Introduction

�Software-based Self-Testing Paradigm

�Processor functional fault self-testing

�Processor structural fault self-testing

�Processor self-diagnosis

�Testing global interconnect

�Testing nonprogrammable cores

�Instruction-level DFT

�DSP-based AMS component testing

�Concluding remarks


Fabrication versus Test CapitalFabrication versus Test Capital


Test Paradigm ShiftTest Paradigm Shift

�Functional testing

�Structural testing

�BIST

• Embedded hardware tester

• Area, performance, design overhead

• Limited at-speed testing

�SBST

• Embedded software tester

• Use self-tested memory and processor to test

other on-chip components



�Introduction











A SoftwareA Software--Based SelfBased Self--Testable SoCTestable SoC


SelfSelf--Test FlowTest Flow

�Memory self-testing

�Processor self-testing

�Global interconnect testing



SBST vs. BISTSBST vs. BIST

�BIST places the system in nonfunctional

mode

�SBST handles testing as an application

• Minimized DFT circuitry

• Reduce external tester performance requirement

• Greater test accuracy

• Excessive test power and overkill problems

eliminated



�Introduction











Processor ModelProcessor Model

�RTL level

�System-graph (S-graph)

• Node: a register that can

be explicitly modified by

an instruction

• Edge: data flow

between registers


Node LabelingNode Labeling

�assign label 0 to OUT

�K = 0

�while there exists unlabeled nodes

• Assign K+1 to unlabeled nodes whose contents can be transferred to any register(s) labeled K by

executing a single class T or B instruction

• K = K + 1

�end while


Edge LabelingEdge Labeling

�Edges of an instruction that reads a register

to OUT are labeled 1

�A instruction’s edges are labeled K+1 if its

destination register is labeled K


FunctionalFunctional--Level Fault ModelsLevel Fault Models

�Register decoding fault

�Instruction decoding and control fault

�Data storage fault

�Data transfer fault

�Data manipulation fault


Test Generation ProceduresTest Generation Procedures

�Utilize the S-graph and the node/edge labels

to facilitate test generation

�The knowledge gained from edges and

nodes with lower labels is utilized in

generation tests for those with higher labels


Test Generation ComplexityTest Generation Complexity

�nR: number of registers

�nI: number of instructions

�Register decoding fault

• O(nR3)

�Instruction decoding and control fault

• O(nI2) if the instruction labels do not exceed 2.



�Introduction











Test FlowTest Flow

�Test preparation

• One major challenge is extraction of instruction-

imposed I/O constraints

�Self-testing


PARWAN SHU I/O and PARWAN SHU I/O and

An Example Test Application SequenceAn Example Test Application Sequence


SHU Input Spatial ConstraintsSHU Input Spatial Constraints

Control Inputs Flag Inputs Data Inputs

asl asr v c z n s (data_in[7]) data_in[6:0]

lda 0 0 0 0 data_in≡ 0 s X X

and 0 0 0 0 data_in≡ 0 s X X

add 0 0 c⊕s X data_in≡ 0 s X X

sub 0 0 c⊕s X data_in≡ 0 s X X

asl 1 0 0 0 data_in≡ 0 s X X

asr 0 1 0 0 data_in≡ 0 s X X


SHU Temporal ConstrainSHU Temporal Constrain


Constrained Component Test GenerationConstrained Component Test Generation

�I = IC; F = FC; VC = Φ; TC = Φ;

�while I≠Φ and F ≠Φ

• pick i from I;

• if not Vi,C⊆ VC

– (Ti,C, Fdet) = constrainedTG(F, Vi,C);

– TC = TC∪ Ti,C;

– F = F - Fdet;

– VC = VC∪ Vi,C;

• end if

• I = I - { i };

�end while


Component Tests for PARWAN ALUComponent Tests for PARWAN ALU

Test Pattern

alu_code in_1 in_2

lda 100 (1111 1111,0110 0011,82) ZZZZ ZZZZ

sta 110 ZZZZ ZZZZ (1111 1111,0110 0011,82)

cma 001 ZZZZ ZZZZ (1111 1111,0110 0011,35)

and 000 (1111 1111,0110 0011,98): odd (1111 1111,0110 0011,98): even

sub 111 (1111 1111,0110 0011,24): odd (1111 1111,0110 0011,24): even

add 101 (1111 1111,0110 0011,26): odd (1111 1111,0110 0011,26): even


Test Program for Observing ALU OutputsTest Program for Observing ALU Outputs

lda addr(y) // load

add addr(x)

sta data_out // store AC

lda 11111111

brav ifv // branch if overflow

and 11110111

label ifv brac ifc // branch if carry

and 11111011

label ifc braz ifz // branch if zero

and 11111101

label ifz bran ifn // branch if negative

and 11111110

label ifn sta flag_out


Processor SelfProcessor Self--TestingTesting


VCCVCC--Based Test Program Synthesis FlowBased Test Program Synthesis Flow

� M = partitioning();

� T = extractTemplate();

� foreach m∈ M

• Tm = rankTemplate();

• while Tm≠ ϕ or fault coverage not acceptable

– t = highest ranked template in Tm;

– F = deriveMappingFunction(t,m);

– generateVCC();

– Pm,t = constrainedTG();

– processor-level fault simulation;

– Tm = Tm - { t };

• end while

� end foreach


Test Generation Using VCCsTest Generation Using VCCs


A Test Program Synthesis ExampleA Test Program Synthesis Example


Functionally Untestable Delay FaultsFunctionally Untestable Delay Faults

�Faults for which no functional test exists

�In PARWAN, paths that start at S1 and end

at the inputs of IR or AC are functionally

untestable


PARWAN Datapath Constraints for thePARWAN Datapath Constraints for the

““NOP; add;NOP; add;”” SequenceSequence

A7-A0 B7-B0 S2-S0 IR AC

Cycle 1 V1A V1B 100 (NOP)

Cycle 2 V2A V1B 101 (add) Latch

Constraint X...X C...C OZR Care


Delay Fault Test Program Generation Delay Fault Test Program Generation

FlowFlow


Functional Random Instruction TestingFunctional Random Instruction Testing

�FRITS



�Introduction










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System-on-Chip Test Architectures Ch. 11 – Software-Based Self-Testing - P. 33

ChallengesChallenges

�Faults in functionality critical nodes tend to

fail all diagnostic programs

�A test program may activate multiple modules

�Some faults cannot be detected by SBST at

all


PrinciplesPrinciples

�Reduce the variety of instructions in each test

program

�Reduce the number of instructions in each

test program

�Create multiple copies of the same test

program to observe different outputs of the

target module


Diagnostic Test Program Generation FlowDiagnostic Test Program Generation Flow



�Introduction











Maximum Aggressor Fault ModelMaximum Aggressor Fault Model


Data Bus TestingData Bus Testing

�Must be tested from both directions

�Vector 1

• Data may be from or to the processor

�Vector 2

• Test for target core to processor

– Processor reads from core

• Test for processor to target core

– Processor writes target core

– The written vector is read back for comparison


Address Bus TestingAddress Bus Testing

�Unidirectional


Functional MA TestingFunctional MA Testing

�Many of the MA faults can never occur during

normal system operations

�FMA tests meet the system constraints and

can be conducted while operating in the

functional mode



�Introduction











Test FlowTest Flow



�Introduction











InstructionInstruction--Level DFT ConceptLevel DFT Concept

�Inserts test circuitry into the design in the

form of test instructions

• Less intrusive than gate-level DFT

• More attractive for applying at-speed test and for

power/thermal management

�Reuse existing hardware as much as

possible to reduce area overhead


The Example ProcessorThe Example Processor


Testability InstructionsTestability Instructions

�s2r (move SR to Rn)

• Improve the observability of SR

• SR => ALU => C => Rn

�r2s (move A to SR)

• Improve the controllability of SR

• A => ALU => SR


� Read exception signals from Rn

• Allows the processor to set the values of the exception signals from

Rn

• Set T o 1. Then, R27 => controller

� Pipeline register access

• For the hard-to-control registers buried deeply embedded in the

pipeline

• Loading data from general purpose registers to B

EE14148


Test Optimization InstructionsTest Optimization Instructions

�load2 (consecutive load to Ri and Rj)

• Reduce the test program size

�xor_all (signature computation)

• Perform a sequence of XOR operations on the

register file

• Reduce test program run time



�Introduction










EE14150


DSPDSP--Based BIST for AMS ComponentsBased BIST for AMS Components

�Utilize on-chip DSP resources to facilitate

stimulus generation and response analysis



�Introduction











�SBST has the potential to alleviate many

problems associated current structural BIST

techniques

�One major challenge is extracting functional

constraints imposed by the processor

instruction set

�Further research

• Automatic constraint extraction

• Generalized for AMS components

Chapter 11 Software -Based Self -Testing€¦ · System-on-Chip Test ArchitecturesEE141 Ch. 11 –Software-Based Self-Testing -P. 22 Component Tests for PARWAN ALU Test Pattern alu_code

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