Addressing Modes and Formats Chapter 11 Instruction Sets
Feb 23, 2016
Addressing Modes and Formats
Chapter 11Instruction Sets
Team MembersJose AlvarezDaniel MonsalveMarlon Calero Alfredo GuerreroOskar PioAndres Manyoma
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Addressing ModesAn addressing mode is the method by which an
instruction references memoryTypes of addressing modes:
ImmediateDirect IndirectRegisterRegister IndirectDisplacement (Indexed)Stack
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Immediate AddressingSimplest form of addressingActual data is stored in instructionValue of the operand is stored within instructionData sizes vary by processor and by instructionNo memory reference (other than instruction
fetch) required to obtain operandSize of number limited to size of address field
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Immediate Addressing Diagram
Instruction Opcode Operand
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Direct AddressingInstruction points to location of stored value, but
value itself is out of memorySingle memory reference to access dataNo additional calculations needed to work out
effective addressFrequently used for global variables in high level
languageLimited address space
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Direct Addressing Diagram7
Address AOpcode
Instruction
Memory
Operand
Indirect AddressingMemory pointed to by address field contains the
address of the operandLarge address space 2n where n = word lengthMultiple memory accesses to find operandHence slower
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Indirect Addressing Diagram9
Address AOpcode
Instruction
Memory
Operand
Pointer to operand
Register AddressingSpecified instruction contains required operandLimited number of registersSmall address field needed
Leads to shorter instructions, but faster fetch cycle
No memory accessFast executionLimited address space
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Register Addressing Diagram11
Register Address ROpcode
Instruction
Registers
Operand
Register Indirect AddressingVery similar to indirect addressingOnly one main difference between the twoAlgorithms:
Register Indirect: EA = (R) Indirect: EA = (A)
Advantages/disadvantages also similar to those of indirect addressing:Advantage: Large address space (2n)Disadvantage: Extra memory reference
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Register Indirect Addressing Diagram
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Register Address ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Displacement AddressingVery powerful addressing modeCombines capabilities of direct and register
indirect addressing ( EA = A + (R) )Three common uses for displacement addressing
Relative addressingBase-register addressing Indexing
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Displacement Addressing (continued)Relative addressing
Implicitly referred to in PC. If most memory references near to instruction being executed, use of relative addressing saves address bits in instruction
Base-register addressingConvenient means of implementing segmentation
Indexed addressingAddress field references a main memory address;
referenced register contains positive displacement from that address
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Displacement Addressing Diagram
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Register ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Address A
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Stack AddressingLinear array of locationsOther names: Pushdown list, last-in-first-out queueStack is a reverse block of locationsHas a pointer associated with itStack locations in memory are register indirect
addressed
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Stack Addressing Diagram18
x86 Addressing Modes (continued)8 addressing modes available
ImmediateRegister operandDisplacementBaseBase with displacementScaled index with displacementBase with index and displacementBase scaled index with displacementRelative
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x86 Addressing Mode Calculation
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ARM Addressing Modes
Arm has a rich set of addressing modes.Typically they are classified with respect to the type of
instruction.Load/Store AddressingData Processing Instruction AddressingBranch InstructionsLoad/Store Multiple Addressing
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ARM Addressing ModesLoad/StoreLoads and stores Instructions are the only instructions
that reference memory, always done indirectly through a base register plus offset.
3 alternatives are : Offset Preindex Postindex
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ARM Data Processing Instruction Addressing & Branch InstructionsData Processing
Or mixture of register and immediate addressingBranch
Immediate Instruction contains 24 bit valueShifted 2 bits left
On word boundary Effective range +/-32MB from PC
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ARM Load/Store Multiple AddressingLoad/store subset of general-purpose registers 16-bit instruction field specifies list of registersSequential range of memory addressesIncrement after, increment before, decrement
after, and decrement beforeBase register specifies main memory address Incrementing or decrementing starts before or
after first memory access
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Instruction FormatsLayouts of bits in an instructionIncludes opcodeIncludes (implicit or explicit) operand(s)Usually more than one instruction in an instruction
set
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Instruction LengthAffected by and affects:
Memory size Memory organization Bus structure CPU complexity CPU speed
Tradeoff between powerful instruction repertoire and saving space
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Instruction Length (continued)Should be equal to or multiple of memory transfer
lengthShould be multiple of character length (usually 8
bits)Word length of memory is “natural” unit of
organization
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Allocation of BitsTradeoff between number of opcodes and power
of the addressing capabilityMore opcodes mean more bits in the opcode fieldIn an instruction format, this reduces number of
bits available for addressingInterrelated factors that determine the use of
addressing bits:
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Allocation of Bits (continued)Number of addressing modes: can be implicit,
but sometimes one or more mode bits are neededNumber of operands: today’s machines provide
for two operands, each requiring its own mode indicator
Register versus memory: one operand address is implicit and consumes no instruction bits, but causes awkward programming and many instructions (a total of 8 to 32 user-visible registers is desirable)
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Allocation of BitsNumber of register sets: most machines have
one set of 32 general-purpose registers to store data and addressesArchitectures like Pentium have more specialized
sets, that by a functional split the instruction uses fewer bits
Address range: related to number of address bits, has severe limitations (which is why direct addressing is rarely used) With displacement addressing, the range is opened
up to the length of the address register
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Allocation of BitsAddress granularity: a factor for addresses that
reference memory rather than registers In a system with 16- or 32-bit words, an address can
reference a word or a byte at the designer’s choice Byte addressing is convenient for character
manipulation but requires more address bits
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PDP-8 Instruction Format32
PDP-10 Instruction Format33
Variable-Length InstructionMake it difficult to decouple memory fetchesFetch part, then decide whether to fetch more,
and maybe miss in cache before instruction is complete
Fixed length allows full instruction to be fetched in one access
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PDP-11Designed to provide powerful and flexible
instruction set within constraints of 16-bit minicomputer
Employs set of eight 16-bit general-purpose registers
Two of these registers have additional significanceOne is used as a stack pointer for special-purpose
stack operationsThe other is used as the program counter, which
contains the address of the next instruction
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PDP-11 (continued) PDP-11 instructions set and addressing capability
are complexThis increases both hardware cost and
programming complexityThe advantage is that more efficient or compact
programs can be developed
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PDP-11 Instruction Format37
VAXMost architectures provide a relatively small
number of fixed instruction formatsTo avoid problems two criteria were used in
designing the VAXAll instructions should have the “natural” number of
operandsAll operands should have the same generality in
specification
VAX instruction begins with a 1-byte opcode, which suffices to handle most VAX instructions
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VAX Instruction Examples39
VAX Instruction FormatsThe remainder of the instructions consists of up
to six operand specifiersIs, at minimum, a 1-byte format in which the
leftmost 4 bits are the address mode specifier The only exception to this rule is the literal mode,
which is signaled by the pattern 00 in the leftmost 2 bits, leaving space for a 6-bit literal
Because of this exception, a total of 12 different addressing modes can be specified
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VAX Instruction FormatsAn example uses an 8-, 16-, or 32-bit
displacement. An indexed mode of addressing may be used. In this case, the first byte of the operand specifier consists of the 4-bit addressing mode code of 0100 and a 4-bit index register identifier.
The remainder of operand specifier consists of base address specifier, which may be one or more bytes.
The VAX instruction set provides for a wide variety of operations and addressing modes. This gives the programmer a very powerful and flexible tool for developing programs.
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Questions1) How many x86 addressing modes were
presented?
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Ans: 9- Imme, Reg operand, Displacement, Base, Base with Displacement, Scaled Index with Displacement, Base with index and Displacement, Base with scaled Index and Displacement, Relative.
2) What are the most common addressing modes?Ans: Immediate, direct, indirect, register, register indirect, displacement, stack
3) How many ARM Addressing modes are there?Load/Store addressing, Data Process Inst Addr, Branch Inst, Load/Store multiple Addr.
Questions4) How many factors can go into determining the
use of determining addressing bits?
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Ans: # of Addr. Modes, # of Operands, Register vs Mem, # of reg sets, Address Range, Address Granularity
5) What is the fastest Addressing mode?Ans: Immediate Opt code + Operand
6) What is an advantage of using Direct addressing mode? Ans: Simplicity Opt code + lower address
space.7) What addressing mode combines the capabilities of direct & reg indirect addr?
Ans: Displacement
Questions
8) Which addressing mode it’s also known as pushdown list addressing mode.
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Ans: Stack Addressing mode.9) Which of the addressing modes is the simplest?
Ans: immediate addressing mode
10) More opcodes mean more ___ in the opcode field?Ans: Bits
Thank You
[APPLAUSE]
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