Chapter 1 2 3 and 4c

Contents

Abstract

Chapter1: Multiple Access Techniques

1.1 Introduction

1.2 FDMA

1.3 TDMA1.4 CDMA

Chapter 2: Types of CDMA Techniques

2.1 Introduction

2.2 General Classification of CDMA

2.3 pseudo Random Noise Code

Chapter 3: Design of CDMA transmitter and receiver

3.1 Introduction

3.2 DS- CDMA Transmitters

3.3 DS-CDMA RECEIVER

Chapter 4: Implementation of DS-CDMA Transmitter and Receiver

4.1 Introduction

4.2 CDMA Transmitter

4.3 CDMA Receiver

Chapter 5: Future Scope and Conclusion

List of Figures:

2.1 FDMA scheme

2.2 FDMA spectrum

2.3 TDMA scheme 1

2.4 TDMA/ FDMA hybrid

2.5 CDMA

2.6 Basic CDMA transmissions

2.7 Simple direct sequence modulator

2.8 Direct sequence signals

3.1 CDMA types

3.2 Classification of CDMA

3.3 Block diagram of DSSS transmitter

3.4 Receiver of DSSS signal

3.5 Direct-sequence spreading

3.6 DS-concept before and after dispreading

3.7 Near far effect illustrated

3.8 Block diagram of FH-CDMA transmitter and receiver

4.1 Block diagram of DS- CDMA transmitter

4.2 Block diagram of BPSK modulator

4.3 Phase accumulator

4.4 Block diagram of DS-CDMA receiver

5.1 Flow chart for PN sequence generator

2

5.2 Simmulation results for PN sequence generator

5.3 DDFS flow chart

5.4 Simmulation results for phase accumulator

5.5 Simmulation results for DDFS

5.6 BPSK modulator flow chart

5.7 Simmulation results for DS-CDMA transmitter

5.8 BPSK demodulator flow chart

5.9 Matched code filter flow chart

5.10 Simmulation results for multiplier

5.11 Simmulation results for accumulator

5.12 Simmulation results for single user DS-CDMA

transmitter and receiver

5.13 Simmulation results for four user DS-CDMA transmitter

and receiver

3

Abstract

The DS - CDMA is expected to be the major medium access technology in

the future mobile systems owing to its potential capacity enhancement and the

robustness against noise. The CDMA is uniquely featured by its spectrum-

spreading randomization process employing a pseudo-noise (PN) sequence,

thus is often called the spread spectrum multiple access (SSMA). As different

CDMA users take different PN sequences, each CDMA receiver can discriminate

and detect its own signal, by regarding the signals transmitted by other users as

noise-like interferences.

In this project Direct sequence principle based CDMA transmitter and

receiver will be implemented in VHDL for FPGA. The digital frequency

synthesizer principle is used in generating the carrier signals both at transmitter

and receiver modules. The transmitter module mainly consists of symbol

generator, programmable PN sequence generator, digital local oscillator,

spreader and BPSK modulator blocks. The receiver module consists of BPSK 4

demodulator, matched filter, programmable PN sequence generator and

threshold detector blocks. The CDMA receiver gets this input and recovers the

data using matched filter.

Modlesim Xilinx Edition 5.8 (MXE) tool will be used for functional

simulation and logic verification at each block level and system level. The Xilinx

Synthesis Technology (XST) of Xilinx ISE tool will be used for synthesis of

transmitter and receiver on FPGAs. Applications of the developed CDMA system

for ADHOC networks and defense communication links will be studied. The

possible extensions of work in view of advancements in software defined radio

principles will be discussed.

Chapter 1

INTRODUCTION

1.1 INTRODUCTION

In communication systems an attractive approach for economical, spectral

efficient, and high quality digital cellular and personal communication services is the use

of Direct sequence code division multiple access (DS-CDMA) technique. Due to its

improved privacy and security, increased capacity.

VHDL implementation of DS-CDMA transmitter and receiver has been proposed

in this thesis. Every mobile handset and every wireless base station operates on the same

frequency spectrum .In order to discriminate one conversation from the other, every

handset broadcast a unique code sequence is called as pseudo noise code. In this project

pseudo noise code is generated by using two six bit LFSRs.Code signal is called as chip

signal. The chips modulated by the carrier using adigital modulation technique BPSK.

The carrier is generated by using the technique discrete digital frequency synthesizer.

CDMA base stations must be able to discriminate this different code sequences in order

to distinguish one transmission from other .This discrimination is accomplished by means

of a matched code filter .A matched code filter is a filter whose frequency spectrum is

5

exactly designed to match the frequency spectrum of the input signal. Here matched code

filter generating the pseudo noise code, generated noise code is correlated with the

received code and detecting original data.

1.2 LITERATURE SURVEY

Cellular technology has grown tremendously both in terms of traffic and services,

the need for data high speed data transmission has increased[1-3]. The mobile

telecommunication industry faces the problem providing technology that be able to

support a variety of services ranging from voice communication with a bit rate of few

Kbps to wireless multimedia in which bit rate up to 2 Mbps[3,4]. This tremendous growth

has also been fueled by the recent improvements in the capacity of wireless links due to

the use of multiple access techniques. The idea is to transmit signals simultaneously

through a linear band limited channel without inter channel or inter symbol interference.

To design multi channel transmission must concentrate on reducing cross talk between

adjacent channels.

One of the most promising cellular standards is IS-95 CDMA system[4]. the

advantages of CDMA standard over other standards are security, optimum subscriber

power management , efficient power control, compatability, multipath fading. The

forward link frequency of CDMA is in the range of (869-894) MHZ and the reverse link

frequency is in the range of (824-849)MHZ[2-5]. In mobile communication transmission

from the base station to mobile user are on the forward link and the transmission from

mobile user to base station are on the reverse link. In the recent years the CDMA on

FPGA platform has attracted attention of academic research and industry [5].

The Spartan TM-3E family of Field-Programmable Gate Arrays (FPGAs) is

specifically designed to meet the needs of high volume, cost-sensitive consumer

electronic applications [5]. The five-member family offers densities ranging from

100,000 to 1.6 million system gates. Because of their exceptionally low cost, Spartan -3E

FPGAs are ideally suited to a wide range of consumer electronics applications, including

broadband access, home networking, display/projection, and digital television equitment.

I.3 PROBLEM FORMULATION

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In the spread spectrum based multi user systems unique codes are to be assigned

to different users to differentiate them. For the identification of unique user, the code

must undergo some operations, so the data may not be diverted to wrong user.

Autocorrelation is the procedure by which matching of one signal is done with the same

signal.

Low cross correlation between the desired user and other user is important to

suppress the multiple access interference .Good autocorrelation properties are required

for reliable synchronization and reliable separation on the multipath components. To get

low crosscorrelation orthogonal codes are required to generate.

1.4 OBJECTIVE OF THESIS

The main objective of this thesis is to implement the CDMA transmitter

and receiver inside a single FPGA. VHDL coding for all the modules were done

and simulated.

For DS-CDMA communication system the transmission side PN sequence

generator, spreader and modulator, reception side not only requires dispreading

device for the extraction of transmission signal, but also demodulator for

detection of code signal. Thus when hardware arrangements used for these

devices the circuit size increased and number of processing steps required for

software. It is required to implement the system using less number of processing

steps.

1.5 ORGANIZATION OF THESIS

The project is organized into 6 chapters namely introduction, multiple

access techniques, classification of CDMA, design of DS-CDMA transmitter and

receiver, software implementation of DS-CDMA, and conclusion.

Chapter 1 discusses the general idea of the project, which covers the

introduction, project objective, project background.

Chapter 2 shows the review of the multiple access techniques, such as

TDMA and FDMA, and disadvantages of these techniques. And also describing

the basic principle of CDMA.

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Chapter 3 describes the classification of CDMA, detailed description DS-

CDMA. And also describing the pseudorandom noise code, generation of code.

Chapter 4 introduces the methodology of the project, block diagrams of

DS-CDMA transmitter and receiver and design considerations of DS-CDMA

system.

Chapter 5 explains regarding software implementation of CDMA

transmitter and receiver using flowcharts. This part discusses on the work

involved for simulation of transmitter and receiver.

Chapter 6 consists of conclusion and proposed works to enhance the

project in future.

Chapter2

MULTIPLE ACCESS TECHNIQUES

2.1 INTRODUCTION

Multiple access schemes are used to allow many simultaneous users to use the

same fixed bandwidth radio spectrum. In any radio system, the bandwidth that is

allocated to it is always limited. For mobile phone systems the total bandwidth is

typically 50 MHz, which is split in half to provide the forward and reverse links of the

system. Sharing of the spectrum is required in order increase the user capacity of any

wireless network. FDMA, TDMA and CDMA are the three major methods of sharing the

available bandwidth to multiple users in wireless system. There are many extensions, and

hybrid techniques for these methods, such as OFDM, and hybrid TDMA and FDMA

systems. However, an understanding of the three major methods is required for

understanding of any extensions to these methods.

2.2 FREQUENCY DIVISION MULTIPLE ACCESS

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For systems using Frequency Division Multiple Access (FDMA), the available

bandwidth is subdivided into a number of narrower band channels. Each user is allocated

a unique frequency band in which to transmit and receive on. During a call, no other user

can use the same frequency band. Each user is allocated a forward link channel (from the

base station to the mobile phone) and a reverse channel (back to the base station), each

being a single way link. The transmitted signal on each of the channels is continuous

allowing analog transmissions. The channel bandwidth used in most FDMA systems is

typically low (30 kHz) as each channel only needs to support a single user. FDMA is

used as the primary subdivision of large allocated frequency bands and is used as part of

most multi-channel systems.

The following figures show the allocation of the available bandwidth into several

channels.

Figure 2.1 FDMA showing that the each narrow band channel is allocated to a single user

9

Figure 2.2 FDMA spectrums, where the available bandwidth is subdivided into narrower

band channels

2.3 TIME DIVISION MULTIPLE ACCESS

Time Division Multiple Access (TDMA) divides the available spectrum into

multiple time slots, by giving each user a time slot in which they can transmit or receive.

Figure 8 shows how the time slots are provided to users in a round robin fashion, with

each user being allotted one time slot per frame. 

Figure 2.3 TDMA schemes where each user is allocated a small time slot

TDMA systems transmit data in a buffer and burst method, thus the transmission

of each channel is non-continuous. The input data to be transmitted is buffered over the

previous frame and burst transmitted at a higher rate during the time slot for the channel.

TDMA can not send an analog signal directly due to the buffering required, thus is only

used for transmitting digital data. TDMA can suffer from multipath effects as the

transmission rate is generally very high, resulting in significant inter-symbol

interference. 

TDMA is normally used in conjunction with FDMA to subdivide the total

available bandwidth into several channels. This is done to reduce the number of users per

channel allowing a lower data rate to be used. This helps reduce the effect of delay spread

on the transmission. Figure 4 shows the use of TDMA with FDMA. Each channel based

on FDMA, is further subdivided using TDMA, so that several users can transmit of the

one channel. This type of transmission technique is used by most digital second

generation mobile phone systems. For GSM, the total allocated bandwidth of 25MHz is

divided into 125, 200 kHz channels using FDMA. These channels are then subdivided

further by using TDMA so that each 200 kHz channel allows 8-16 users.

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Figure 2.4 TDMA / FDMA hybrid, showing that the bandwidth is split into frequency

channels and time slots

2.4 CODE DIVISION MULTIPLE ACCESS

Code Division Multiple Access (CDMA) is a spread spectrum technique that uses

neither frequency channels nor time slots. With CDMA, the narrow band message

(typically digitized voice data) is multiplied by a large bandwidth signal that is a pseudo

random noise code (PN code). All users in a CDMA system use the same frequency band

and transmit simultaneously. The transmitted signal is recovered by correlating the

received signal with the PN code used by the transmitter. Figure 5 shows the general use

of the spectrum using CDMA.

Figure 2.5 Code division multiple access (CDMA)

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CDMA technology was originally developed by the military during World War II.

Researchers were spurred into looking at ways of communicating that would be secure

and work in the presence of jamming. Some of the properties that have made CDMA

useful are:

Signal hiding and non-interference with existing systems.

Anti-jam and interference rejection

Information security

Accurate Ranging 

Multiple User Access

Multipath tolerance

For many years, spread spectrum technology was considered solely for military

applications. However, with rapid developments in LSI and VLSI designs, commercial

systems are starting to be used. 

2.4.1 CDMA Process Gain

One of the most important concepts required in order to understand spread

spectrum techniques is the idea of process gain. The process gain of a system indicates

the gain or signal to noise improvement exhibited by a spread spectrum system by the

nature of the spreading and despreading process. The process gain of a system is equal to

the ratio of the spread spectrum bandwidth used, to the original information bandwidth.

Thus, the process gain can be written as:

Where BWRF is the transmitted bandwidth after the data is spread, and BW info is

the bandwidth of the information data being sent.

Figure 6 shows the process of a CDMA transmission. The data to be transmitted

(a) is spread before transmission by modulating the data using a PN code. This broadens

the spectrum as shown in (b). In this example the process gain is 125 as the spread

spectrum bandwidth is 125 times greater the data bandwidth. Part (c) shows the received 12

signal. This consists of the required signal, plus background noise, and any interference

from other CDMA users or radio sources. The received signal is recovered by

multiplying the signal by the original spreading code. This process causes the wanted

received signal to be despread back to the original transmitted data. However, all other

signals that are uncorrelated to the PN spreading code become more spread. The wanted

signal in (d) is then filtered removing the wide spread interference and noise signals.

Figure 2.6 Basic CDMA transmissions.

2.4.2 CDMA Generation

CDMA is achieved by modulating the data signal by a pseudo random noise

sequence (PN code), which has a chip rate higher then the bit rate of the data. The PN

code sequence is a sequence of ones and zeros (called chips), which alternate in a random

fashion. Modulating the data with this PN sequence generates the CDMA signal. The

CDMA signal is generated by modulating the data by the PN sequence. The modulation

is performed by multiplying the data (XOR operator for binary signals) with the PN

sequence. Figure 7 shows a basic CDMA transmitter. 13

Figure 2 .7 Simple direct sequence modulator

The PN code used to spread the data can be of two main types. A short PN code

(typically 10-128 chips in length) can be used to modulate each data bit. The short PN

code is then repeated for every data bit allowing for quick and simple synchronization of

the receiver. Figure 8 shows the generation of a CDMA signal using a 10-chip length

short code. Alternatively a long PN code can be used. Long codes are generally

thousands to millions of chips in length, thus are only repeated infrequently. Because of

this they are useful for added security as they are more difficult to decode. 

Figure 2.8 Direct sequence signals

2.4.3 CDMA Forward Link Encoding

The forward link, from the base station to the mobile, of a CDMA system can use

special orthogonal PN codes, called Walsh codes, for separating the multiple users on the

same channel. These are based on a Walsh matrix, which is a square matrix with binary

elements and dimensions that are a power of two.  It is generated from the basis that

Walsh (1) = W1 = 0 and that:

14

Where Wn is the Walsh matrix of dimension n. For example:

Walsh codes are orthogonal, which means that the dot product of any two rows is

zero. This is due to the fact that for any two rows exactly half the number of bits match

and half do not. 

Each row of a Walsh matrix can be used as the PN code of a user in a CDMA

system. By doing this the signals from each user is orthogonal to every other user,

resulting in no interference between the signals. However, in order for Walsh codes to

work the transmitted chips from all users must be synchronized. If the Walsh code used

by one user is shifted in time by more than about 1/10 of chip period, with respect to all

the other Walsh codes, it looses its orthogonal nature resulting in inter-user interference.

This is not a problem for the forward link as signals for all the users originate from the

base station, ensuring that all the signal remain synchronized. 

2.4.4 CDMA Reverse Link Encoding

The reverse link is different to the forward link because the signals from each user

do not originate from a same source as in the forward link. The transmission from each

user will arrive at a different time, due to propagation delay, and synchronization errors.

Due to the unavoidable timing errors between the users, there is little point in using

Walsh codes as they will no longer be orthogonal. For this reason, simple pseudo random

sequences are typically used. These sequences are chosen to have a low cross correlation

to minimize interference between users. 

15

The capacity is different for the forward and the reverse links because of the

differences in modulation. The reverse link is not orthogonal, resulting in significant

inter-user interference. For this reason the reverse channel sets the capacity of the system.

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Chapter 3

TYPES OF CDMA TECHNIQUES

3.1 INTRODUCTION

Based on the modulation method the CDMA technique can be classified into three

categories.

CDMA: direct sequence (DS)

CDMA: frequency hopping (FH)

CDMA: time hopping (TH)

Frequency

Time

Figure 3.1 CDMA types

[1] In DS-CDMA, spectrum is spread by multiplying the information signal with a

pseudo-noise sequence, resulting in a wideband signal.

[2] In FH-CDMA. In the frequency hopping spread spectrum, a pseudo-noise

sequence defines the instantaneous transmission frequency. The bandwidth at each

moment is small, but the total bandwidth over, for example, a symbol period is large.

17

Direct sequence

Frequency hopping

Time hopping

Frequency hopping can either be fast (several hops over one symbol) or slow (several

symbols transmitted during one hop).

[3] In TH-CDMA, in the time hopping spread spectrum, a pseudo-noise sequence

defines the transmission moment.

CDMA Properties

Multiple access capability

Protection against multipath interference

Privacy, interference rejection

Anti-jamming capability

Low probability of interception

3.2 GENERAL CLASSIFICATION OF CDMA

Figure 3.2. Classification of CDMA

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3.2.1 Direct Sequence

In DS-CDMA the modulated information-bearing signal (the data signal) is

directly modulated by a digital, discrete time, discrete valued code signal. The data

signal can be either an analogue signal or a digital one. In most cases it is a digital signal.

In the case of a digital signal, the data modulation is often omitted and the data signal is

directly multiplied by the code signal and the resulting signal modulates the wideband

carrier. It is from this direct multiplication that the direct sequence CDMA gets its name.

Data

Figure 3.3 Block diagram of a DS-SS transmitter

In figure 3 a block diagram of a DS-CDMA transmitter is given. The binary data

signal is modulated by the code signal. This code signal consists of a number of code bits

called “chips” that can be either +1 or –1. The spreaded signal is modulated by a RF

carrier. For the modulation, various modulation techniques can be used, but usually some

form of phase shift keying (PSK) like binary phase shift keying (BPSK), differential

binary phase shift keying (D-BPSK), quadrature phase shift keying (QPSK), or minimum

shift keying (MSK) is employed.

The following figure shows the block diagram of DSSS receiver.

19

Modulator

SpreadingDevice

Carriergenerator

Codegenerator

Data

Figure 3.4 Receiver of a DS-SS signal

After transmission of the signal, the receiver (shown in Figure 4) dispreads the SS

signal using a locally generated code sequence.

In Direct-Sequence CDMA, the user signal is multiplied by a pseudo-noise code

sequence of high bandwidth. This code sequence is also called the chip sequence. The

resulting coded signal is transmitted over the radio channel.

Direct sequence spread spectrum systems are so called because they employ a

high speed code sequence, along with the basic information being sent, to modulate their

RF carrier. The high speed code sequence is used directly to modulate the carrier, thereby

directly setting the transmitted RF bandwidth.

The most practical, all digital version of SS is direct sequence. A direct sequence

system uses a locally generated pseudo noise code to encode digital data to be

transmitted. The local code runs at much higher rate than the data rate. Data for

transmission is simply logically modulo-2 added (an EXOR operation) with the faster

pseudo noise code. The composite pseudo noise and data can be passed through a data

scrambler to randomize the output spectrum (and thereby remove discrete spectral lines).

A direct sequence modulator is then used to double sideband suppressed carrier modulate

20

Despreading (matched filter)

DataDemodulator

CodeGenerator

CarrierGenerator

the carrier frequency to be transmitted. The resultant DSB suppressed carrier AM

modulation can also be thought of as binary phase shift keying (BPSK). Carrier

modulation other than BPSK is possible with direct sequence. However, binary phase

shift keying is the simplest and most often used SS modulation technique.

An SS receiver uses a locally generated replica pseudo noise code and a receiver

correlator to separate only the desired coded information from all possible signals. A SS

correlator can be thought of as a very special matched filter -- it responds only to signals

that are encoded with a pseudo noise code that matches its own code. Thus, an SS

correlator can be "tuned" to different codes simply by changing its local code. This

correlator does not respond to man made, natural or artificial noise or interference. It

responds only to SS signals with identical matched signal characteristics and encoded

with the identical pseudo noise code.

A PNcode is a sequence of chips valued -1 and 1 (polar) or 0 and 1 (non-polar)

and has noise-like properties. This results in low cross-correlation values among the

codes and the difficulty to jam or detect a data message

A usual way to create a PNcode is by means of at least one shift-register. When

the length of such a shift-register is n, the following can be said about the period NDS of

the above mentioned code-families:

`In direct-sequence systems the length of the code is the same as the spreading-

factor with the consequence that:

21

Figure 3.5 Direct-sequence spreading

This can also be seen from figure 5, where we show how the PNcode is combined

with the data-signal, the generation of PNcodes is relatively easy, a number of shift-

registers are all that is required. For this reason it is easy to introduce a large processing-

gain in Direct-Sequence systems.

Figure 3.6 DS-concept, before and after despreading

In the receiver, the received signal is multiplied again by the same (synchronized)

PNcode. Since the code existed of +1s and -1s, this operation completely removes the

code from the signal and the original data-signal is left. Another observation is that the

despread operation is the same as the spread operation. The consequence is that a

possible jamming-signal in the radio channel will be spread before data-detection is

performed. So jamming effects are reduced

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DSSS disadvantage

The main problem with applying Direct Sequence spreading is the so-called Near-

Far effect which is illustrated in figure below. This effect is present when an interfering

transmitter is much closer to the receiver than the intended transmitter. Although the

cross-correlation between codes A and B is low, the correlation between the received

signal from the interfering transmitter and code A can be higher than the correlation

between the received signal from the intended transmitter and code A. The result is that

proper data detection is not possible.

Figure3.7: near-far effect illustrated

Another spread spectrum technique: Frequency-Hopping is less effected by this Near-Far

effect.

2.2.2 Frequency hoping

Frequency hopping is the easiest spread spectrum modulation to use. Any radio

with a digitally controlled frequency synthesizer can, theoretically, be converted to a

frequency hopping radio. This conversion requires the addition of a pseudo noise (PN)

code generator to select the frequencies for transmission or reception. Most hopping

systems use uniform frequency hopping over a band of frequencies. This is not absolutely

necessary, if both the transmitter and receiver of the system know in advance what

frequencies are to be skipped. Thus a frequency hopper in two meters, could be made that

skipped over commonly used repeater frequency pairs. A frequency hopped system can

use analog or digital carrier modulation and can be designed using conventional narrow

band radio techniques. De-hopping in the receiver is done by a synchronized pseudo

noise code generator that drives the receiver's local oscillator frequency synthesizer.

23

The wideband frequency spectrum desired is generated in a different manner in a

frequency hopping system. It does just what its name implies. That is, it "hops" from

frequency to frequency over a wide band. The specific order in which frequencies are

occupied is a function of a code sequence, and the rate of hopping from one frequency to

another is a function of the information rate. The transmitted spectrum of a frequency

hopping signal is quite different from that of a direct sequence system. Instead of a [(sin

x)/x]^2-shaped envelope, the frequency hopper's output is flat over the band of

frequencie. hopping system. The bandwidth of a frequency hopping signal is simply w

times the number of frequency slots available, where w is the bandwidth of each hop

channel.

When applying Frequency Hopping, the carrier frequency is 'hopping' according to a

unique sequence (an FH-sequence   of length NFH). In this way the bandwidth is increased

by a factor NFH(if the channels are non-overlapping):

Also in frequency hopping CDMA, the carrier frequency of the modulated

information signal is not constant but changes periodically. During time intervals T, the

carrier frequency remains the same, but after each time interval the carrier hops to

another (or possibly the same) frequency. The hopping pattern is decided by the

spreading code. The set of available frequencies the carrier can attain is called the hop-

set.

The frequency occupation of an FH-SS system differs considerably from a DS-SS

system. A DS system occupies the whole frequency band when it transmits, whereas an

FH system uses only a small part of the bandwidth when it transmits, but the location of

this part differs in time.

The difference between the FH-SS and the DS-SS frequency usage is illustrated in

Figure 7. Suppose an FH system is transmitting in frequency band 2 during the first time

period. A DS system transmitting in the same time period spreads its signal power over

the whole frequency band so the power transmitted in frequency band 2 will be much less

than that of the FH system. However, the DS system transmits in frequency band 2

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during all the time periods while the FH system only uses this band part of the time. On

average, both systems will transmit the same power in the frequency band.

The block diagram for an FH-CDMA system is given in Figure 8. The data signal

is baseband modulated. Using a fast frequency synthesizer that is controlled by the code

signal, the carrier frequency is converted up to the transmission frequency.

The inverse process takes place at the receiver. Using a locally generated code

sequence, the received signal is converted down to the baseband. The data is recovered

after (baseband) demodulation. The synchronisation/tracking circuit ensures that the

hopping of the locally generated carrier synchronises to the hopping pattern of the

received carrier so that correct despreading of the signal is possible.

Within frequency hopping CDMA a distinction is made that is based on the

hopping rate of the carrier. If the hopping rate is (much) greater than the symbol rate the

modulation is considered to be fast frequency hopping (F-FH). In this case the carrier

frequency changes a number of times during the transmission of one symbol, so that one

bit is transmitted in different frequencies. If the hopping rate is (much) smaller that the

symbol rate, one speaks of slow frequency hopping (S-FH). In this case multiple

symbols are transmitted at the same frequency.

Data

Figure 3.8 Block diagram of an FH-CDMA transmitter and receiver

FHSS advantages

On the other hand, Frequency-Hopping is less effected by the Near-Far effect than

Direct-Sequence. Frequency-Hopping sequences have only a limited number of ``hits''

with each other. This means that if a near-interferer is present, only a number of

25

BasebandModulator

Up converter

CodeGenerator

FrequencySynthesizer

DownConverter

FrequencySynthesizer

DataDemodulator

CodeGenerator

Data

“frequency-hops'' will be blocked in stead of the whole signal. From the ``hops'' that are

not blocked it should be possible to recover the original data-message

FHSS disadvantages

A disadvantage of Frequency-Hopping as opposed to Direct-Sequence is that

obtaining a high processing-gain is hard. There is need for a frequency-synthesizer able

performs fast-hopping over the carrier-frequencies. The faster the ``hopping-rate'' is, the

higher the processing gain

3.3. PSEUDO-RANDOM NOISE CODES

A PNcode used for DS-spreading exists of NDS units called chips, these chips can

have 2 values: -1/1 (polar) or 0/1. As we combine every data symbol with a complete

PNcode, the DS processing gain is equal to the code-length. To be usable for direct-

sequence spreading, a PNcode must meet the following constraints:

The sequences must be building from 2-leveled numbers.

The codes must have a sharp (1-chip wide) autocorrelation peak to enable

code-synchronization.

The codes must have a low cross-correlation value, the lower this cross-

correlation, the more users we can allow in the system. This holds for both full-

code correlation and partial-code correlation. The latter because in most situations

there will not be a full-period correlation of two codes, it is more likely that codes

will only correlate partially (due to random-access nature).

The codes should be ``balanced'': the difference between ones and zeros in

the code may only be 1. This last requirement stands for good spectral density

properties (equally spreading the energy over the whole frequency-band).

Codes that can be found in practical DS-systems are: Walsh-Hadamard codes, M-

sequences, Gold-codes and Kasami-codes. These code sets can be roughly divided into

two classes: orthogonal codes and non-orthogonal codes. Walsh sequences fall in the first

category, while the other group contains the so-called shift-register sequences

26

3.3.1 Shift-Register sequences

Shift-Register sequences are not orthogonal, but they do have a narrow

autocorrelation peak. The name already makes clear that the codes can be created using a

shift-register with feedback-taps. By using a single shift-register, maximum length

sequences (M-sequences) can be obtained. Such sequences can be created by applying a

single shift-register with a number of specially selected feedback-taps. If the shift-register

size is n then the length of the code is equal to . The number of possible codes is

dependent on the number of possible sets of feedback-taps that produce an M-sequence.

These sequences have a number of special properties, M-sequences are balanced: the

number of ones exceeds the number of zeros with only 1.

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Chapter 4

DESIGN OF CDMA TRANSMITTER AND RECEIVER

4.1 INTRODUCTION

In this project two CDMA communication systems are implemented, one with

Maximum Length (ML) sequence PN code and other with gold code. In the PN sequence

generator section both the ML sequence and gold code generators are described. The

following specifications are considered for design and implementation of the CDMA

transmitter and receiver.

(1) Type of PN sequence : ML / gold code

(2) LFSR size : 6 bit in case of ML sequence

Two 6 bit LFSR’s in case of gold sequence

(3) PN sequence length : 64 in case of ML sequence

128 in case of gold sequence

(4) Maximum number of : 64 in case of ML sequence

Communication links 128 in case of gold sequence

(5) Type of modulation : BPSK

(6) Type of demodulation : Coherent BPSK demodulation with 15 outputs

Digital words

(7) Type of correlator : Matched filter

(8) Type of signal synthesis : ROM based direct digital frequency synthesis

(9) Phase resolution chosen in DDFS: 5.625O

(10) Threshold type : constant threshold value, adjustable

(11) Front end design entry: VHDL

(12) Backend synthesis : Xilinx Spartan 3E FPGA

Following tools are used while developing, testing, implementing and

programming the CDMA transmitter and receiver blocks.

Simulation - Modelsim Xilinx Edition (MXE)

28

Synthesis - Xilinx Synthesis Technology (XST) of Xilinx ISE

4.2 DS- CDMA TRNSMITTER

The top level block diagram of CDMA transmitter which is implemented in this

project is given in the below figure.

Figure 4.1 Block diagram of CDMA transmitter.

The main blocks of CDMA transmitter are listed below.

Clock distributor

PN sequence generator

Signal spreader

BPSK modulator

4.2.1 CL

Data sampler

Information bits

PN sequence generator

Phase register

Phase increment register

COS LUT

Phase translator

Clk & control ckt

CDMA SIGNAL

BPSK modulator

Phase accumulatorRst

29

The clock distributor of CDMA transmitter derives different clock signals from

master clock, which are required for Spread spectrum signal generation.

4.2.2 PN sequence generator

The important block of DS-CDMA communication system is the PN sequence

generator. The PN sequence generator can be implemented using LFSR’s to generate

several types of PN sequences as discussed in previous chapters. Two types of PN

sequence generators implemented in this project. They are ML sequences and gold codes.

ML sequence generator

A 6-bit LFSR for generating ML sequence of 64bit length will be used to generate the PN

code.

Gold code generator

A gold code PN sequence generator with two 6-bit LFSR’s for generating 128 bit

gold code will be used.

4.2.3 Signal spreader

The function of signal spreader is to generate PN sequence when the information

bit is ‘1’ and generate the complement of the PN sequence if the information bit is ‘0’.

The digital implementation of signal spreader is achieved by using XOR gate controlled

inverter action. The spreaded chip signal is used for modulation by BPSK modulator.

4.2.4 BPSK modulator

The BPSK modulator produces the band pass spread spectrum signal which is

suitable for transmission from the spreaded signal. The BPSK modulator is implemented

using pure digital architecture. The Direct Digital Frequency Synthesis (DDFS) technique

with phase shifting provision is used for the signal generation. The high level block

diagram and various blocks of BPSK modulator are given below.

30

Figure 4.2 the block diagram of BPSK modulator

The various blocks of BPSK modulator are

Phase accumulator

Phase translator

LUT for phase to amplitude conversion.

PIPO n bit generic register

The Parallel in Parallel Out shift register cells are required in phase accumulator

block to hold frequency and phase values. Synchronization is required between the phase

increment register and phase register. This is achieved by connecting a common clock

signal.

N bit generic adder

The N-bit generic adder is implemented in VHDL with simple ripple carry adder

logic.

Phase Accumulator

The phase accumulator consists of phase increment register, adder and phase

register. The following figure shows the inner blocks of phase accumulator.

Frequency register

Phase reg Phse shift controller

Cos LUT

BPSK_OUT

Phase accumulator

31

Modulating data

The phase increment register stores the instantaneous phase increment values

resulting from frequency modulation control block. This is fed to a 6 bit adder as one of

its input. The other input for adder is phase register output. The phase register holds the

instantaneous phase for each clock pulse. The accumulated phase also is represented by 6

bits, which limits the maximum phase by 111111, and addition by 1 to maximum value

causes the phase to become 000000 This is expected and desired since the Look Up

Tables are programmed to consider 63 as highest phase value and phase increment by one

results next cycle of waveform. Since 6 bits are used to represent the 0O to 360O the

increment in digital phase value by one causes effective increment of 5.625O (results by

dividng 360O with 64 maximum possible combinations of 6 bits) . This also implies that

outputs can’t have more that 64 samples for one cycle.

The output of phase accumulator when the phase increment value is

000001 (decimal four) is given in below figure. It can be observed that the resulting

phase value after each clock pulse is incremented by one to the previous phase value.

Figure Modelsim output for Phase accumulator

Phase shifter

The phase shifter block shifts the instantaneous phase produced by phase

accumulator, according to the spreaded bits. Since in DDFS with 6 bit phase

representation 32 (100000) corresponds to 180O phase, the phase shifter adds the 32

(100000) when symbol ‘1’ is given and adds 0 (000000) when symbol ‘0’ is given. Phase

shifter is implemented by using 6 bit adder.

COS – LUT

32

6

Figure 4.3 Phase Accumulator

Phase increment register

Phase register

The COS LUT is used as phase to amplitude converter, which takes digital phase

from phase accumulator and gives corresponding amplitude value of COS wave.

4.3 DS-CDMA RECEIVER

The DS-CDMA receiver implemented in this project with the specification mentioned

in the above sections consists of following blocks.

Clock distributor

BPSK demodulator

Serial to parallel converter

PN code generator

Matched filter

Threshold detector

The high level block diagram of CDMA receiver is shown in the below figure.

33

Figure 4.4 Block diagram of DS-CDMA receiver

34

Since clock distributor and PN sequence generators are same as the transmitter blocks

they are not repeated here.

4.3.1 BPSK demodulator

Digital coherent BPSK demodulator principle is used in this project for receiving

the DS-CDMA signals. The BPSK demodulator produce 15 (-7 to 7) digital words, unlike

in conventional BPSK demodulator which produces only two symbols (‘1’ and ‘0’). This

is necessary due to the low power spectral density of DS-CDMA signals and it is only

possible to detect the information bits after correlation. This dynamic range of BPSK

demodulator can be changed, for a given specification. Each block of BPSK demodulator

is illustrated in the following sections.

Multiplier

A signed multiplier is used to multiply the incoming signal with the LO output.

The multiplication is performed in 2’s complement and the 15 bit result is given to the

accumulator.

Local oscillator

The Local oscillator produces 6 bit signed bits representing the COS signal. The

same principle DDFS which is used in transmitter is used in the receiver.

Integrate and dump

The accumulator in the receiver corresponds to the integrator in the analog

equivalent. The accumulator accumulates the outputs of multiplier for one symbol

duration and outputs at the beginning of next symbol. The symbol timing recovery issues

are not addressed in this project, hence the symbol clock derived from clock distributor is

used in the integrate and dump circuit.

Scaling device

The scaling device accepts the output of integrate dump circuit and scales its

value to 4 bit signed number range, i.e., -7 to +7. This circuit is used in instead of

decision device which we find in conventional BPSK demodulator.

Serial to parallel converter

The serial to parallel converter, as shown in the high level block diagram of

BPSK demodulator accepts the outputs of the BPSK demodulator and produces parallel

vector with an array of 128 words. This parallel 128 words constitute the most recent 128

outputs of the BPSK demodulator. This becomes input to the correlator.

35

4.3.2 Matched code filter

Matched filter based correlator is used in this project for receiving the DS-CDMA

signals. The correlator accepts the 127 demodulator outputs and multiplies with 127

length PN sequence which is a sequence of +1 and -1. The outputs of multipliers are

accumulated to produce the correlator output. The magnitude of the correlator output

peaks whenever exact match occurs between the PN sequence and BPSK demodulator

outputs. The output of the matched filter is given to the threshold detector, for detecting

the information bits.

PN sequence generator

The PN sequence generator is same as the one which is discussed in transmitter,

except in the output type. In the transmitter side the output of PN sequence generator

continuously produces PN sequence on one bit output. But in the receiver side, since the

complete PN sequence is required every time for correlating with the outputs of BPSK

demodulator it is provided as a parallel vector. Another difference is the ‘1’ of PN

sequence is provided as +1 and ‘0’ is provided as -1, which is the required form for

correlator.

Threshold detector

The threshold detector compares the magnitude of the correlator output with the

threshold value. If the magnitude of the correlator output is higher than the threshold

value, then it rises a flag indicating that one bit is detected. If the sign of the correlator

output is positive, then it will be interpreted as ‘1’. Otherwise it will be declared as ‘0’.

This is the detected information bit.

Multiply and accumulate

This block multiplies the parallel converted demodulated output with PN

sequence represented in -1 (for 0) and +1 (for 1) format.

Decision device

This device decides the demodulated bit is ‘1’ or ‘0’ based on the multiply and

accumulated value is positive or negative.

36

Chapter 5

VHDL IMPLEMENTATION OF CDMA TRANSMITTER AND

RECEIVER

5.1 INTRODUCTION

The FPGA/VHDL combination is a powerful tool for realizing sophisticated

communications and cost effective design schemes. FPGA chosen to realize CDMA

transmitter and receiver because they can implement a wide range of logic gates upto

millions of gates.

Traditional gate arrays contain a number of building blocks or primitive cell

etched on a single silicon substrate. The connections between cells are permanent and

made later. These are non-reprogrammable high-density devices containing about 5

millions gates. The FPGAs have sikilar structure to gate arrays however they have

programmable elements. The programmable cell is called Logic Element (LE) in case of

alter device and Configurable Logic Block (CLB) in Xilinx devices.

VHDL is VHSIC hardware description language common language for

designers. This is the high level language and simulation, synthesis tools are available.

VHDL supports for versatile design reconfiguration and multiple level of abstraction.

A VHDL specification can be executed in order to achieve high level of

confidence in its correctness before commencing design and may simulate one to two

orders of magnitude faster than a gate level description. A VHDL specification for a part

can form the basis for a simulation model to model to verify the operation of the part in

the wider system. Behavioural simulation can reduce design time by allowing design

problems to detected early on, avoiding the need to rework designs at gate level.

Behavioural simulation also permits design optimization by exploiting alternative

architecturers, resulting better design. VHDL permits technology independent design

through support for top down design and logic synthesis.

37

5.2 CDMA TRANSMITTER:

Main blocks in CDMA transmitter are PN-sequence generator, direct digital

frequency synthesizer, BPSK modulator.

5.2.1 PN Sequence generator:

Fig: 5.1 Flow chart for PN Sequence generator

38

Rst=1

Clk=1

C=127

g1=Key 1g2=Key 2

C=C+1

Z=0

Z=g1(6) XOR g2(2) XOR g2(4)

Chip=Z

C=0 g1(2to6) =g1(1to5)g2(2to6) g2(1to5)

g1(1)=g1(3)XOR g1(5)g2(1)=g2(2)XORg2(3)XOR g2(6)

Yes

No

Yes

No

YesNo

A linear feedback shift register (LFSR) is the heart of any digital system.

LFSR’s are the functional building blocks of circuits like the pseudo random

noise code generators commonly used in code division multiple access (CDMA)

systems.

LFRS’s sequence through (2N –1) states, where N is the number of

registers in the LFSR. Here the elements from the taps of the shift register are

linearly combined using modulo-2 addition and are then feedback to the register

depending on the tapping. Here we use two 6-bit LFRS’s to generate two

random number sequences each of 64 bits. The input to the two LFSR’s is the

same, but the tapping varies.

The length of the shift register, the number of taps, and their positions in

the LFSR, are important to generate PN sequences with desirable

autocorrelation and cross-correlation properties.

Fig 5.2 Simmulation results for PN-sequence generator

39

.5.2 Direct Digital Frequency Synthesizer

Direct Digital Frequency Synthesizer is a technique to produce desired out put

with full digital control .Entity is DDFS, Components used in this block are phase

accumulator and COS look up table (LUT_ COS). Inputs given to this entity phase

increment word, Rst and Clk

Figure 5.3 Direct Digital Frequency Synthesizer Flow chart

40

x = 000000y = 000001

rst=1

Clk = 1 x<= x + y

Z<=x

yes

No yes

Phase bits

LUT _COS

Phase to amplitude Converter

No

The phase accumulator consists of a 6-bit frequency register, which stores a

digital phase increment word followed by a 6-bit full adder and a phase register.

The digital input phase increment “000001” word is held in the phase increment register.

Rising edge of each clock pulse phase increment word “000001” added to the data

previously held in the phase register. Initial data in the phase register is “000000”,

represents zero degrees. Rising edge of first clock pulse “000001” added to “000000”.

Then resultant data in the phase register is “000001” represents the (5.6 0). At the next

clock pulse “000001” adder to “000001”. The phase increment word represents a phase

angle step that is added to previous value at each rising edge of clock to produce linearly

increasing digital value. Final value of phase accumulator is 111111 (3600). Again in next

clock pulse phase accumulator output is initialized to 000000.

The number held in the Accumulator is used to address a look-up table

(LUT_COS) held in ROM which converts phase information to a series of discrete

digitized samples of the amplitude of a cosine wave

Frequency of the carrier generated is fc

fc= fclk/64 = fck/26

Figure 5.4 Simmulation results for phase acccumulator

41

Figure 5.5 Simmulation results for DDFS

5.2.3 BPSK Modulator

Entity is BPSK modulator. Input ports are rst, data_clk (Dclk), samples_clk (clk),

data bit. Out put port is BPSK _OUT. To implement this entity three components

used are phase accumulator, LUT_COS, adder_nbit.

Phase accumulator is instantiated to generate instantaneous phase values.

LUT_COS is instantiated to convert phase values into amplitude bits of Cosine wave.

Adder_nbit is instantiated to implement phase translator.

42

Figure 5.6: BPSK Modulator flow chart

43

Dclk=1

Rst=1

Read data bit

_Clk=1

Read phase bits(Y) FromPhase accumulator

X=100000

DataBit=1Z=X+Y

Z = YLUT_COS

BPSK_OUT =000000

C = C+1 C=64

BSK_OUT

NO

YESNO

YES

YES

NO

NO

YES

YES

NO

Rising edge of each data_clk pulse data bit enters into BPSK modulator. Another

clk used in this entity is samples_clk. Frequency of samples_ clk is 64 times the data clk.

Rising edge of each samples_ clk pulse, phase accumulator values is incremented by ‘1’.

Phase accumulator generates instantaneous phase values from “000000” to “111111” i.e,

64 values.

If the data bit is ‘1’ then “100000” added to phase accumulator value. This

addition is carried by adder _ nbit. Adder _nbit output is given as input to LUT_COS,

which converts phase bits into amplitude bits. Addition of “100000” to phase

accumulator indicates 1800 phase shift of cosine wave if data bit is’1’. If data bit is ’0’

phase accumulator value directly given as input to LUT_COS.

After completion of 64 samples_ clk pulses, rising edge of next data_clk pulse

occurs then next data bit enters into the BPSK Modulator.

Figure 5.7 Simmulation results for CDMA transmitter

44

5.3 CDMA RECEIVER

CDMA receiver consists of BPSK demodulator, matched code filter

5.3.1 BPSK Demodulator

Entity is Bpsk-demodulator. Inputs given to this entity are Amp-bits Received

from the channel, clk, demodulated-out value, Rst. Components used in this block are

phase accumulator, LUT_COS Multiplier, Accumulator, Threshold detector and decision

device.

Phase-accumulator and LUT_COS components are instantiated to generate carrier

in synchronization with carrier generated in transmitter. Multiplier instantiated to

multiply Received amplitude bits and carrier amplitude bits generated in Bpsk-

demodulator. Accumulator is instantiated to accumulate the multiplier output. Threshold

detector is instantiated to detect whether the accumulated sum is +ve or –ve.

Decision device is instantiated to take the decision about the chip_out, if

accumulator output is –ve then chip_out is ‘0’. If accumulator output is +ve then chip_out

is ‘1’.

Rising edge of each clock pulse Amplitude bits from the channel enters into this

block. Received amplitude bits multiplied with the locally generated cosine wave

amplitude bits and accumulated. After completion of the “64” clock pulses. Accumulated

sum is given as the input to the Threshold detector. Threshold detector compares the

accumulated sum with the reference (0). Decision device decides whether the input is ‘0’

or ‘1’based on the output of threshold detector. If threshold detector output is “-ve”

received chip is ‘0’. If threshold detector output is +ve then received chip is ‘1’.

45

Figure 5.8: BPSK Demodulator flow chart

46

C=0X=000000Y=000001

rst=1

clk=1

Read Amp_bits from channel

Phase=X

LUT_COS

Z=Z+A*I

C=C+1C=64

Z >0 Chip=1 Chip=0

X=X+Y

Chip =0

Phase to amplitude converterI

NO

YES

YES NO

YES

NO

NO YES

5.3.2 Matched code filter

To implement implement this entity five components are used PN sequence

generator, multiplier and accumulator, threshold detector, decision device. Inputs given to

this entity are BPSK demodulator out put, rst, clk. Out put from this entity is data bit .

If rst =1 out put from matched code filter remains zero, otherwise rising edge of

each clock pulse received chip from BPSK modulator enters into this block, and it is

multiplied with locally generated chip, multiplied value accumulated using accumulator.

Then counter is incremented, this process repeated until the conter value I=127. When

I=127 accumulated sum is given as input to the threshold detector. Threshold detector is

instantiated to detect whether the accumulated sum is positive or negative. Decision

device is instantiated to take decision about the data bit received. If threshold detector out

put is negative then received bit is ‘0’ , other wise received bit is ‘1’.

After detection of data bit, in next clock pulse counter I is initialized to zero

process is repeated to detect next received data bit. In this block PN sequence generator is

instaniated to generate chips.

47

BPSK demodulator out(O

Demodulated out put Demodulated out put Figure: 5.9 Matched Code Filter

48

Rst=1

I = 0 Z = 0

Clk=1Input chipFrom PN_gen

Z = Z + P*O

I = I + 1I = 127

Z > 0Data = 1 Data = 0

Data = 0

NO

YES

YESNO

Yes

No

Yes No

Figure 5.10 Simmulation results for multiplier

Figure 5.11 Simmulation results for accumulator

49

Figure 5.12 Simmulation results for single user CDMA transmitter and receiver

Figure 5.13 Simmulation results for four user CDMA transmitter and receiver

50

CHAPTER 6

CONCLUSION

CDMA is one of the most impartant multiple access technique .In this project the

transmitter and receiver were implemented on FPGA. After synthesis simulations are

agreed before synthesis simmulations. The transmitter was connected to the receiver

before synthesis was done to verify functionality of the transmitter and receiver. This has

been tested using an arbitrary chosen data stream, where these data have been transmitted

through implemented transmitter and then received by our implemented receiver. A

comparison has been done between the transmitted and received data and satisfactory

results have been achieved. Increasing the number of bits using the same topology, it is

possible to reach the standard rates specified for CDMA.

This work has the following applications.

Custom CDMA communication setup with specified PN sequence length and

number of users

Standard CDMA systems designs such as used for mobiles and GPS

Implementation of a CDMA communication system with DSSS technique in VHDL

has the following advantages

The design is fully reconfigurable

The number of bits and PN sequence can be changed very easily

Useful for both FPGA and ASIC implementations.

Disadvantages

Complex hardware is involved in receiver design which increases the cost of the

system.

FUTURE SCOPE

The concept can be extended to design the GPS system which is CDMA system

with 1023 chip length technique.

FHSS technique can also be implemented and compared.

51

REFERENCES

[1] William C.Y.Lee, Mobile Cellular Telecommunications Systems, McGraw-Hill

International Edditions , 1997.

[2]

52

STUDENT BIO-DATA

Name : B. Sree devi

Father Name: B. lachi reddy

Roll. No. 04004D0615

Date of Birth: 04-08-1972

Nationality: Hindu

Communication Address: H.NO. 1-7-1292, Advocates colony

Town/Village: Hanamkonda Mondal: Hanamkonda District: Warangal

PIN Code: 506001

Ph.No: 9704024475

E-mail: [email protected]

Permanent Address: H.NO. 1-7-1292, Advocates colony

Town/Village: Hanamkonda Mondal: Hanamkonda District: Warangal

PIN Code: 506001

Ph.No: 9704024475

E-mail: [email protected]

Qualifications: AMIE

Area of Interest: Communications, signal processing

Declaration:

I here by declare that the above mentioned information is true to my knowledge.

And I bear complete responsibility for the correctness of the above mentioned

information.

Signature

53