Chapter 01

H. Huang Transparency No.1-1

The HCS12/MC9S12 Microcontroller

Copyright © 2010 Delmar Cengage Learning

Chapter 1: Introduction to HCS12/MC9S12

The HCS12 Microcontroller

Han-Way Huang

Minnesota State University, Mankato

September 2009




Number System Issue

• Computer hardware uses binary numbers to perform all operations.• To display numbers produced by the computer, both the octal and hexadecimal numbers have been used to shorten the representation.• Human beings are used to decimal number system. Conversion is often needed to convert numbers between the internal (binary) and external (decimal) representations. • It is common for mixed use of different number bases.• A prefix is used to indicate the base of a number.

Modulus Math• Computers perform modulus math because it uses a limited number of bits (e.g., 8, 16, or 32 bits) to represent numbers.

Table 1.1 Prefixes for number basesBase

BinaryOctal

DecimalHexadecimal

(shorthand hex)

Prefix Example

%10001010@12346712345678

$392

%@

$




What is a computer?

Software

Hardware

Computer Hardware Organization

Control Unit

Datapath

ArithmeticLogic Unit

Registers

Processor

Common Bus (address, data, & control)

Memory

ProgramStorage

Data Storage

OutputUnits

InputUnits

Figure 1.1 Computer Organization




The Processor• A processor consists of arithmetic logic unit (ALU), control unit, and registers.• The ALU can perform many different operations.• An ALU that can perform 4 operations is shown in Figure 1.1.

OpCode

Adde

rAND

OR

SUM

Carry

Result

Cout

MUX3

CIN 1

MUX2inverters

MUX1

A B

ciYX

2Comparator

(=?) 01

00

11

n

n

n

n

nn

10

01

10

0 1

Figure 1.1 An ALU that implements ADD, SUB, AND, and OR operations

0pcode00 = ADD01 = SUB10 = AND11 = OR




Control Unit

• The control unit decodes machine codes and performs the operations specified by the machine code.• A machine instruction has several fields. A mandated field is the opcode field.• Instruction execution is timed by a clock signal. • The frequency of the clock signal used in an 8-bit or 16-bit microcontroller is from a few mega hertz to several hundred mega Hertz• The control unit uses a program counter to keep track of the address of the instruction to be executed next.• The fetched instruction is placed in the instruction register when is decoded, and executed.• Program instructions are normally stored in sequential locations in memory.• The processor may not execute instructions in sequential due to the need to execute instructions based on the condition or the need to repeat a certain group of instructions.• The processor uses conditional and unconditional branch (or jump) instructions to change the program flow.




Registers• A register is a storage location inside the CPU.• A register is used to hold data or address during the execution of an instruction.• A register, very close to the ALU, provides fast access to operands for program execution.• Some processors provide a dedicated register (often called an accumulator) as one of the operands of most of the instructions.• Freescale HCS12, Microchip PIC18, Intel 8051 microcontrollers use this approach.• Other processors provide many general-purpose registers in the CPU that can be used as operands of instructions. • Atmel AVR and AVR32, Microchip PIC24 and PIC32, Freescale Coldfire use this approach.

Microprocessor• A processor implemented in a single integrated circuit (IC).• The first microprocessor, Intel 4004, was introduced in 1968.• The Intel 8008, the first 8-bit microprocessor from Intel, was introduced in 1972.• A microprocessor requires peripheral ICs to interface with I/O devices.• A microprocessor does not have peripheral functions such as timers, A/D converters, D/A converters, parallel I/O ports, and memory.• The designer need to add peripheral ICs and memory devices to the microprocessor in order to build a product.




Microcontroller• A microcontroller incorporates the processor and one or more of the following peripheral functions and memory in one very large scale integrated circuit (VLSI):

1. Memory2. Timer functions3. Serial communication interface such as UART, I2C, SPI, CAN, and Ethernet4. A/D converter5. D/A converter6. Direct memory access 7. Parallel I/O ports8. Memory component interface9. Software debug support

• Microcontrollers have been used in almost every product that requires a certain amount of intelligence. • Microcontrollers have been used as controllers for displays, printers, keyboards, modems, charge card phones, palm-top computers, home appliances such as washing machines and microwave ovens, automobile control, and so on.




Embedded Systems• An embedded system is a computer designed to perform a dedicated function.• An embedded system performs one or a few predefined tasks, with very specific requirements.• Embedded systems are often mass-produced and benefitting from economic scale.• Software written for embedded systems is often called firmware.




Memory Technologies

Magnetic Memory• Magnetic drums, magnetic tapes, and magnetic disks are the three major magnetic memory devices that have been invented.• Only magnetic disks are still being widely used today• Hard disks are rarely used in an embedded system

Optical Memory• Compact disk (CD) and digital video disc (DVD) are two major optical memory devices.• CD was introduced in 1982.• CD has two versions: CD-R and CD-RW.• The capacity of a 12-inch CD is 700 MB.• A 12-inch DVD has the capacity of 4.7 GB• DVD has two versions: DVD-R and DVD-RW versions.

Semiconductor Memory• Semiconductor memory can be classified on the basis of volatility and read-writability.• On the basis of volatility, semiconductor memory is divided into volatile and non-volatile memory.• On the basis of read-writability, semiconductor memory is divided into random-access memory (RAM) and read-only memory (ROM).




Random-access memoryThere are four types of RAM:

Dynamic random-access memory (DRAM): • The one-bit cell of DRAM consists of one transistor and one capacitor.• The information is stored in the capacitor whereas the transistor controls the access of the information stored in the capacitor.• Periodic refresh is required to maintain the contents of a DRAM chip

Static random-access memory (SRAM): • The one-bit of SRAM consists of 4 to 6 transistors.• No periodic refresh operation is required to maintain the information stored in SRAM.

Magneto RAM (MRAM):• The one-bit cell of MRAM consists of two magnetic plates each of which can hold a magnetic field, separated by a thin insulating layer. One of the plates is a permanent magnet set to a particular polarity.• A MRAM chip combines a magnetic device with standard silicon-based microelectronics to achieve the attributes of non-volatility, high-speed operation, and unlimited read and write endurance




Ferroelectric RAM (FRAM)• FRAM uses the state change of ferroelectric crystal to store information.• FRAM technology is mainly developed by Ramtron International.• FRAM is nonvolatile and has an access time about 55 ns in 2007.• Due to its lower density, FRAM is mainly used in niche applications.

Read-Only Memory• ROM is nonvolatile.• There are several types of ROM technologies.

Mask-Programmed ROM (MROM)• The contents of MROM is programmed when it is manufactured.• To be cost-effective, many thousands of copies of MROM chip must be manufactured.• MROM is one of the major ROM technologies to hold application programs

Programmable ROM (PROM)• PROM was invented in 1956 by Win-Tsing Chow.• The setting of each bit is locked by a fuse or antifuse.• PROM is programmed by blowing a fuse or an antifuse.• PROM can only be programmed once using a special programmer.




Erasable programmable ROM (EPROM) • EPROM was invented by an Israelis engineer Dov Frohman in 1971. • An EPROM cell must be erased before it is programmed.• EPROM is electrically programmable many times.• EPROM is erased by ultraviolet light (through a window).• EPROM can only be erased in bulk (whole chip in one erasure operation).

Electrically erasable programmable ROM (EEPROM)• EEPROM was invented by George Perlegos of Intel in 1983.• An EEPROM cell must be erased before it is programmed.• EEPROM is electrically erasable and programmable many times.• EEPROM can be erased one location, one row, or whole chip in one operation

Flash memory• Flash memory was invented by Fujio Masuoka in 1984.• Flash memory is electrically erasable and programmable many times.• Flash memory can only be erased in bulk or a sector at a time• Flash can achieved the density of DRAM and is the most widely used nonvolatile memory technology.




Computer software

• Computer programs are known as software• A program is a sequence of instructions

Machine instruction

• A sequence of binary digits which can be executed by the processor

0001 1000 0000 0110: A [A] + [B]0100 0011: A [A] + 1

1000 0110 0000 0110: A 6

• Hard to understand, enter, debug, and maintain for human being




Assembly language

• Defined by assembly instructions• An assembly instruction is a mnemonic representation of a machine instruction

ABA: A [A] + [B]DECA: A [A] – 1

• Assembly programs must be translated into machine instructions before it can be executed -- translated by an assembler• There are two kinds of assembler: native assembler and cross assembler.• Programmers need to work on the program logic at a very low level and cannot achieve high productivity.




High-level language

• Syntax of a high-level language is similar to English• A translator (called compiler) is required to translate the program written in a high-level language:

1. There are two types of compilers: native compiler and cross compiler.2. High-level languages allow the user to work on the program logic at higher level

and achieve higher productivity.

Source code

• A program written in assembly or high-level language

Object code

• The output of an assembler or compiler




line

1:

2:

3:

4:

5:

6:

addr.

2000

2003

2006

2009

machine code

= 00002000

B6 1000

BB 1001

BB 1002

7A 1100

source code

org $2000

ldaa $1000

adda $1001

adda $1002

staa $1100

end




Memory System Operation• A block diagram of a memory system is shown in Figure 1.2.• Each memory location has two components: address and contents.• The organization of a memory chip is indicated by m x n, where m is the number of locations in the chip and n indicates the number of bits in one location.• The notation [reg] and [addr] specifies the contents of a register and the memory location at addr, respectively.

address

RDWR

data

OE

WE

Microprocessor Memory system

Figure 1.2 Block diagram of a simplified memory system




Read Operation• The processor places the address of the memory location that it intends to read on the address bus and asserts the RD signal.• The RD signal enables the memory chip to send out the contents of the selected location on the data bus and the processor gets the data.

Write Operation• The processor places the address of the location that it intends to write on the address bus.• The processor also places the data that it intends to write on the data bus and asserts the WE signal.• In responds to the WE signal, the memory chip stores the data on the data bus in the selected memory location.




Program ExecutionTo understand how processor executes the program, we need to answer the followingquestions:

Where does the processor start to execute program after power on?• From a fixed location such as address 0: PIC18, Atmel avr, and 8051• Fetch the starting address from a fixed location: HCS12

How does the processor update the program counter (PC)?• Increment the program counter by the length of the instruction just executed.• Increment or decrement by the amount specified in the current instruction—conditional and unconditional branch instructions.• Set to the new address specified by the current instruction—jump (or goto) instruction or subroutine call instruction.

Program Counter Circuit• A common building block of PC is the D flip-flop with set and reset capability (Figure 1.3).• The program counter circuit that can be forced to 0, incremented by 1, incremented by a field in the instruction, and loaded with a jump target is shown in Figure 1.4.




set reset

D

CLK

Q

Figure 1.3 Block diagram of a D flip-flop with set and reset

1 Branchoffset

0 1MUX1Branch

10

MUX

2

Jump target

adder

Jump

Ds

Qs

reset

CLK

Figure 1.4 A simplified block diagram of the program counter (PC) of an 8-bit microcontroller

PowerOn

Clk

16

16

16

16PC




Architecture of the Processor X

• Processor X has a separate data memory and program memory spaces.• Processor X is used to explain the instruction execution process.• The instruction set of processor X is given in Table 1.3. • Processor X has an 8-bit accumulator A and a 16-bit register ptr.• Processor X instructions can use an 8-bit value to specify a data memory location from 0 to 255 to be accessed.• For data memory locations with address higher than 255, the processor uses the 16-bit register ptr to specify the address. • Processor X uses a MDR register to hold data to be written and read from data memory.• The instruction set implemented by processor X is given in Table 1.3.




Instruction sequence example

ld 0x20,#0 ; place 0 in data memory at 0x20ld 0x21,#20 ; place 20 in data memory at 0x21ld ptr,#0x2000 ; load 0x2000 into the ptr register

loop: ld A,@ptr ; load the memory contents pointed to by ptrand A,#0x03 ; and the value 0x03 with accumulator Abnz next ; branch if the result is not 0inc 0x20 ; increment the memory location at 0x20 by 1

next: dbnz 0x21,loop ; decrement memory location at 0x21 and branch; if the contents of 0x21 is not zero yet

Table 1.3 The instruction set of the processor XAssembly instruction mnemonic

Machine code meaning

ld addr,#valld ptr,#data16ld A,@ptrand A,#valbnz addr,offsetinc addrdbnz addr,offset

75 aa xx90 yyyyE054 xx70 zz05 aaD5 aa zz

Load the 8-bit value (val) into memory location at addr.Load the 16-bit value (data16) into the register ptr.Load the contents of memory location pointed to by ptr into A.And the 8-bit value (val) with A and leave the result in A.Branch to a location that is offset from the next instruction if the value at addr is zero.Increment the contents of memory location at addr.Decrement the contents of memory location at addr and branch if the result is not zero. The branch distance is offset.

Note: aa : an 8-bit value that represent an 8-bit addressxx : an 8-bit value yyyy: a 16-bit valuezz: distance of branch from the first byte of the instruction after the branch instruction.Machine code are expressed in hex format.




Instruction Execution ProcessAssume that processor X executes the instruction sequence in the previous out of reset.

Instruction ld 0x20,#0 (machine code 75 20 00)Step 1Processor X places 0 (contents of PC) on the address bus to perform a read from programprogram memory.Step 2The 8-bit value at the location 0x0000 is the instruction opcode 0x75. At the end of this read cycle, the PC is incremented to 0x0001. The opcode byte 0x75 is fetched. Figure 1.5 shows the opcode read cycle.Step 3Recognizing that 0x75 is the opcode of a load instruction, processor performs two more read operations. The first read returns the address 0x20 whereas the second read returns the value 0.Step 4Processor places 0x20 on the data memory address bus and places 0 on the data bus andthen performs a write operation to write the value 0 to location 0x20.




752000752114902000

5403

E0

70020520D5210A

Program memory Address bus

CPU

Program memory data bus

0x75

0x0000

Figure 1.5 Instruction 1—opcode read cycle

0x0000

Before read

PC

0x0001

After read

PC

xxxxxxxxxxxxxxxxxx

xxxx

xx

xxxxxxxx

Data memory Address bus

CPU

Data memory data bus

0x75

0x20

Figure 1.6 Instruction 1—data memory write cycle

0x0003

Before write

PC

0x0003

After write

PC

0x00

xx

Data meory




Instruction ld 0x21,#20 (machine code 75 21 14)• The execution of this instruction is identical to that of the previous instruction.• PC is incremented to 0x0006 after the execution of this instruction.

Instruction ld ptr,#0x2000 (machine code 90 20 00)Step 1Processor X places the PC value (0x06) on the program memory address bus and makesrequest to read the program memory. Figure 1.7 shows the opcode read cycle.Step 2The opcode returned from location at 0x06 is 0x90 and PC is incremented to 0x07.Step 3The opcode 0x90 indicates that processor X should access program memory to fetch the16-bit value stored after the opcode byte. Processor performs two more read cycles fromprogram memory and places these two bytes in the ptr register. PC is incremented to 0x09.




752000752114902000

5403

E0

70020520D5210A

Program memory Address bus

CPU

Program memory data bus

0x90

0x0006

Figure 1.7 Instruction 3—opcode read cycle

0x0006

Before read

PC

0x0007

After read

PC

Instruction ld A,@ptr (machine code E0)Step 1Processor X places the PC value (0x09) on the program memory address bus and requeststo read the program memory. At the end of this step, PC is incremented to 0x0A.




Step 2The opcode (0xE0) returned in Step 1 requires the processor to perform a read operationUsing the address stored in ptr register. Processor X places the contents of ptr registeron the data memory address bus and request a read operation.Step 3Data memory returns the byte in data memory pointed to by ptr register. This byte is placed in A.

xxxxxxxxxxxxxxxxxx

xxxx

xx

xxxxxxxx

Data memory Address bus

CPU

Data memory data bus

[ptr]

Figure 1.8 Instruction 4—data memory read cycle

xx

Data meory

Mem[[ptr]]

[ptr]: contents of ptr

Mem[[ptr]]: contents of memory location pointed to by ptr




Instruction and A,#0x03 (machine code 54 03)Step 1Processor X places the PC value on the program memory address bus to request a read.After this step is completed, PC is incremented to 0x0B.Step 2The opcode byte (0x54) returned in Step 1 requires the processor X to perform anotherread operation from program memory.Step 3Processor X places the PC value on program memory address bus and request to performa read operation. PC is incremented to 0x0C after this step.Step 4Program memory returns the value 0x03 to the processor.Step 5The processor X then performs an AND operation on the contents of A and the value 0x03and places the result in A




Instruction bnz next (machine code is 70 02)Step 1Processor X places the PC value (0x0C) on the program memory address bus and performsa read operation. After this step, PC is incremented to 0x0D.Step 2The opcode (0x70) returned in Step 1 requires processor X to performs another read tofetch the branch offset. Step 3Processor X places the value PC (0x0D) on the program memory address bus and performsa read. After this step the program memory returns the value 0x02 to the processor. PCis incremented to 0x0E.Step 4Processor checks whether the A value is zero and decides whether branch should betaken. If A contains a nonzero value, the next instruction will be skipped.




Instruction inc 0x20 (machine code 05 20)Step 1Processor X places the PC contents (0x0E) on the program memory address bus and Performs a read operation. At the end of the read operation, PC is incremented to 0x0F.Step 2The returned opcode (0x05) requires processor X to performs another read to fetch an8-bit address from program memory.Step 3Processor X places the contents of PC on the program memory address bus to requestanother read from program memory. PC is incremented to 0x10Step 4Processor X places the value 0x20 on the data memory address bus and requests a read.The returned value is placed in MDR register.Step 5Processor X adds one to the MDR register.Step 6Processor X places the contents of MDR on data memory data bus and 0x20 on the addressbus and requests a write operation. At the end the value in MDR register is written into data memory location at 0x20.




Instruction dbnz 0x21, loop (machine code is D5 21 0A)Step 1Processor X places the contents of PC on the program memory address bus and requestsa read operation. At the end of this step PC is incremented to 0x11.Step 2The opcode (0xD5) returned in step 1 request processor X to perform two more read operation to fetch a byte of data memory address and a byte of branch offset fromprogram memory. At the end of these two read operations, PC is incremented to 0x13.Step 3Processor places the value of 0x21 on the data memory address bus to perform a read.At the end of this read, the contents of data memory location at 0x21 is returned in MDR.Step 4Processor decrements the contents of MDR by 1 and then places this result on the data memory data bus. At the same time, it also places the value of 0x21 on the data memoryaddress bus and requests a write operation.Step 5If the value stored in MDR is not zero, processor X adds 0x0A to the PC and places the sumback in PC (this causes a branch). Otherwise, PC is not changed.




• 16-bit CPU• 64 KB memory space (also supports expanded memory up to 1 MB through a 16-KB window)• 0 KB to 4KB of EEPROM• 2KB to 14KB of on-chip SRAM• 32 KB to 512KB flash memory• Sophisticated timer functions that include: input capture, output compare, pulse accumulators, real-time interrupt, and COP timer• Serial communication interfaces: SCI, SPI, CAN, BDLC• Background debug mode (BDM)• 10-bit A/D converter• Instructions for supporting fuzzy logic function

The HCS12 Features




The HCS12 CPU Registers

7 00 7A B15 0D

8-bit accumulator A and Bor16-bit double accumulator D

15 0X

15 0Y

Index register X

Index register Y

15 0SP Stack pointer

15 0PC Program counter

Condition code registerCarryOverflowZeroNegativeI Interrupt maskHalf-Carry (from bit 3)X Interrupt MaskStop Disable

Figure 1.10 HCS12 CPU registers.

S X H I N Z V C




The HCS12 Addressing Modes• A HCS12 instruction consists of one or two bytes of opcode and zero to five bytes of

operand addressing information.

• Opcode bytes specify the operation to be performed by the CPU. The first byte of a two-

byte opcode is always $18.

• Addressing modes specify the operand to be operated on.

• The addressing mode may specify a value, a register, or a memory location to be used as

an operand.




Table 1.2P M68HC12 addressing mode summaryAddressing mode Source format Abbre. Description

Inherent

Immediate

Direct

ExtendedRelative

Indexed(5-bit offset)Indexed(pre-decrement)Indexed(pre-increment)Indexed(post-decrement)Indexed(post-increment)Indexed(accumulator offset)Indexed(9-bit offset)Indexed(16-bit offset)Indexed-Indirect(16-bit offset)Indexed-Indirect(D accumulatoroffset)

INST (no externally supplied operands)INST #opr8iorINST #opr16iINST opr8a

INST opr16aINST rel8orINST rel16INST oprx5,xysp

INST oprx3,-xys

INST oprx3,+xys

INST oprx3,xys-

INST oprx3,xys+

INST abd,xysp

INST oprx9,xysp

INST oprx16,xysp

INST [oprx16,xysp]

INST [D,xysp]

INH

IMM

DIR

EXT

REL

IDX

IDX

IDX

IDX

IDX

IDX

IDX1

IDX2

[IDX2]

[D,IDX]

Operands (if any) are in CPU registers

Operand is included in instruction stream. 8- or 16-bit size implied by context

Operand is the lower 8 bits of an address in the range $0000-$00FFOperand is a 16-bit addressAn 8-bit or 16-bit relative offset from the current PC is supplied in the instruction

5-bit signed constant offset from x,y,sp, or pc

Auto pre-decrement x, y, or sp by 1 ~ 8

Auto pre-increment x, y, or sp by 1 ~ 8

Auto post-decrement x, y, or sp by 1 ~ 8

Auto post-increment x, y, or sp by 1 ~ 8

Indexed with 8-bit (A or B) or 16-bit (D) accumulator offset from x, y, sp, or pc9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte)16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes)Pointer to operand is found at 16-bit constant offset from (x, y, sp, or pc)Pointer to operand is found at x, y, sp, or pc plus the vlaue in D




Inherent Mode

- Instructions that use this mode do not uses extra bytes to specify operands because

the instructions either do not need operands or all operands are CPU registers.

- Operands are implied by the opcode.

- Examples

NOP

INX

DECA




Immediate Mode

- Operands for instructions that use immediate mode are included in the instruction.

- CPU does not access memory for operands.

- For example,

LDAA #$55

LDX #$1000

Direct Mode

- This mode can only specify memory locations in the range of 0 - 255.

- This mode uses only one byte to specify the operand address.

- Examples,

LDAA $20

LDAB $40




Extended Mode

- This mode uses a 16-bit value to specify memory address is in the instruction.

- For example,

LDAA $4000 ; A ← [$4000]

LDX $FE60 ; X ← [$FE60]:[$FE61]

Relative Mode

- Used only by branch instructions.

- Short and long conditional branch instructions use exclusively relative mode.

- BRCLR and BRSET instructions can also use relative mode to specify branch target.

- A short branch instructions consists of an 8-bit opcode and a signed 8-bit offset. The

short relative mode can specify a range of -128 ~ +127.

- A long branch instruction consists of an 8-bit opcode and a signed 16-bit offset. The

range of the long relative mode is from -32768 ~ +32767.

- A programmer uses a symbol to specify the branch target and the assembler will figure

out the actual branch offset (distance) from the instruction that follows branch

instruction.




- For example,

minus …

…

bmi minus

…

Indexed Mode

- This mode uses the sum of an index register (X, Y, PC, or SP) and an offset to specify the

address of an operand.

- The offset can be a 5-bit, 9-bit, and 16-bit signed value or the value in accumulator A,

B, or D.

- Automatic pre- or post-increment or pre- or post-decrement by -8 to +8 are options.

- PC can be used as the index register for all but auto-increment or auto-decrement mode.

- Indirect indexing with 16-bit offset or accumulator D as the offset is supported.




5-bit Constant Offset Indexed Addressing

- The base index register can be X, Y, SP, or PC.

- The range of the offset is from -16 to +15.

- Examples,

ldaa 0,X

stab -8,0



- The range of the offset is from -256 to +255.

- Examples,

ldaa $FF,X

ldab -20,Y






- This mode allows access any location in the 64-KB range.

- Examples,

ldaa 2000,X

staa 4000,Y

16-bit Constant Indirect Indexed Addressing

- A 16-bit offset is added to the base index register to form the address of a memory

location that contains a pointer to the memory location affected by the instruction.

- The square brackets distinguish this addressing mode from the 16-bit constant offset

indexing. For example,

ldaa [10,X]

staa [20,Y]




Auto Pre/Post Decrement/Increment Indexed Addressing

- The base index register can be X, Y, or SP.

- The index register can be incremented or decremented by an integer value either

before or after indexing taking place.

- The index register retains the changed value after indexing.

- The value to be incremented or decrement is in the ranges -8 thru -1 or 1 thru 8.

- The value need to be related to the size of the operand or the current instruction.

- Examples,

staa 1,-SP ; decrement SP by 1 and then store the contents of A in the location

; pointed to by SP and

staa 1,SP- ; store the contents of A in the location pointed by SP and then

; decrement SP by 1

ldx 2,+SP

ldx 2,SP+




Accumulator Offset Indexed Addressing

- The effective address of the operand is the sum of the accumulator and the base index

register.

- The base register can be X, Y, SP, or PC.

- The accumulator can be the 8-bit A or B or the 16-bit accumulator D.

- For example,

ldaa B,X

stab B,Y

ldy D,X




Accumulator D Indirect Indexed Addressing

- The value in D is added to the value in the base index register to form the address of

the memory location that contains the address to the memory location affected by the

instruction.

- The square brackets distinguish this addressing mode from accumulator D offset

indexing. For example,

jmp [D,PC]

go1 dc.w target1

go2 dc.w target2

go3 dc.w target3

…

target1 …

.

target2 …

.

target3 …




HCS12 Instruction Examples

The LOAD and STORE Instructions

- The LOAD instruction copies the contents of a memory location or places an immediate

value into an accumulator or a CPU register.

- STORE instructions save the contents of a CPU register into a memory location.

- N and Z flags of the CCR register are automatically updated and the V flag is cleared.

- All except for the relative mode can be used to select the memory location or value to

be loaded into an accumulator or CPU register.

- All except for the relative and immediate modes can be used to select memory location

to store contents of the CPU register. For example,

ldaa 0,X

staa $20

stx $8000

ldd #100




Table 1.4 Load and store instructions

Mnemonic

Store Instructions

Mnemonic

Function

Load ALoad BLoad DLoad SPLoad index register XLoad index register YLoad effective address into SPLoad effective address into X Load efective address into Y

Operation

A [opr]B [opr]A:B [opr]:[opr+1]SP [opr]:[opr+1]X [opr]:[opr+1]Y [opr]:[opr+1] SP effective address X effective addressY effective address

Function Operation

Store A in a memory locationStore B in a memory locationStore D in a memory locationStore SP in a memory locationStore X in a memory locationStore Y in a memory location

m[opr] [A]m[opr] [B]m[opr]:m[opr+1] [A]:[B]m[opr]:m[opr+1] [SP]m[opr]:m[opr+1] [X]m[opr]:m[opr+1] [Y]

Load Instructions

ldaa <opr>ldab <opr>ldd <opr>lds <opr>ldx <opr>ldy <opr>leas <opr>leax <opr>leay <opr>

staa <opr>stab <opr>std <opr>sts <opr>stx <opr>sty <opr>




Transfer and Exchange Instructions

- Transfer instructions copy the contents of a CPU register or accumulator into another

CPU register or accumulator.

- TFR is the universal transfer instruction, but other mnemonics are accepted for

compatibility with the 68HC11.

- The TAB and TBA instructions affect the N, Z, and V condition code bits.

- The TFR instruction does not affect any condition code bits. For example,

TFR D,X ; [D] X

TFR A,B ; [A] B

TFR A,X ; sign-extended of[A] X ; A is signed extended to 16-bit and assigned to X

TFR X,A ; X[7:0] A ; lower 8 bits copied to A




- The EXG instruction exchanges the contents of a pair of registers or accumulators. For example,exg A, B

exg D,Xexg A,X ; A X[7:0], X $00:[A]exg X,B ; X $00:[B], B X[7:0]

- The SEX instruction sign-extend an 8-bit two’s complement number into a 16-bit number so that it can be used in 16-bit signed operations. For example, SEX A,X




Move Instructions

- These instructions move data bytes or words from a source to a destination in memory.

- Six combinations of immediate, extended, and index addressing modes are allowed to

specify the source and destination addresses:

IMM EXT, IMM IDX, EXT EXT,

EXT IDX, IDX EXT, IDX IDX

- For example,

movb $100,$800

movw 0,X, 0,Y

Transfer InstructionsTable 1.6 Move instructions

Mnemonic

movb <src>, <dest>movw <src>, <dest>

Function

Move byte (8-bit)Move word (16-bit)

Operation

dest [src]dest [src]




Add and Subtract Instructions

- These instructions perform fundamental arithmetic operations.

- The destinations of these instructions are always a CPU register or accumulator.

- There are two-operand and three-operand versions of these instructions.

- Three-operand ADD or SUB instructions always include the C flag as one of the

operand.

- Three-operand ADD or SUB instructions are used to perform multi-precision addition

or subtraction.

- For example,

adda $1000 ; A [A] + [$1000]

adca $1000 ; A [A] + [$1000] + C

suba $1002 ; A [A] + [$1002]

sbca $1000 ; A [A] - [$1000] - C




Table 1.7 Add and subtract instructions

abaabxabyadca <opr>adcb <opr>adda <opr>addb <opr>addd <opr>

MnemonicAdd B to AAdd B to XAdd B to YAdd with carry to AAdd with carry to BAdd without carry to AAdd without carry to BAdd without carry to D

A [A] + [B]X [X] + [B]Y [Y] + [B]A [A] + [opr] + CB [B] + [opr] + CA [A] + [opr]B [B] + [opr]D [D] + [opr]

Function Operation

Mnemonic Function OperationSubtract Instructions

sbasbca <opr>sbcb <opr>suba <opr>subb <opr>subd <opr>

Subtract B from ASubtract with borrow from ASubtract with borrow from BSubtract memory from ASubtract memory from BSubtract memory from D

A [A] - [B]A [A] - [opr] - CB [B] - [opr] - CA [A] - [opr]B [B] - [opr]D [D] - [opr]

Add Instructions




Instruction Execution Cycle

- One or more read cycles to fetch instruction opcode bytes and addressing information.

- One or more read cycles to fetch the memory operand(s) (optional).

- Perform the operation specified by the opcode.

- One or more write cycles to write back the result to either a register or a memory

- location (optional).

Instruction Queue

- The HCS12 executes one instruction at a time and many instructions take several clock

cycles to complete.

- When the CPU is performing the operation, it does not need to access memory.

- The HCS12 pre-fetches instructions when the CPU is not accessing memory to speedup

the instruction execution process.

- There are two 16-bit queue stages and one 16-bit buffer. Unless buffering is required,

program information is first queued in stage 1, and then advanced to stage 2 for

execution.

Chapter 01

Documents

huang transparency

delmar cengage learning

memory devices

program instructions

operands of instructions

instruction execution

machine instruction

memory component interface