Chap. 3 Basic Concepts
Jan 11, 2016
Chap. 3 Basic Concepts
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Basic Concepts
Lexical Conventions Data Types System Tasks and Compiler Directives Summary
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Lexical Conventions - I
Whitespace Blank space (\b) Tabs (\t) Newlines (\n)
Comments //: single line /* … */ : multiple line
Operators Unary: ~、 ! Binary: +、 -、 && Ternary: a = b ? c : d;
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Lexical Conventions - II Number Specification
Sized numbers: <size>’<base format><number> 4’b1111 12’habc 16’d255
Unsized numbers 23456 ‘hc3 ‘o21
X (unknown) and Z (high impedance) 12’h13x 6’hx 32’bz
Negative numbers -8’d3
Underscore characters and Question marks 12’b1111_0000_1010 equals to 12’b111100001010 4’b10?? equals to 4’b10zz
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Lexical Conventions - III
String “Hello Verilog World” “a/b”
Identifiers and Keywords reg value; input clk;
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Basic Concepts
Lexical Conventions Data Types System Tasks and Compiler Directives Summary
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Data Types
Value set and strength Nets Registers Vectors Integer、 Real and Time Register Data Types Arrays Memories Parameters Strings
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Value Set and Strength
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a, b, c are wires (nets).
Nets
Declare a physical wire Keyword: wire、 wand、 wor、 tri、 trior、
trireg wire a; wire b, c; wire d = 1’b0;
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Registers
Storage element for data Do not equal to “hardware register” Similar to variables in C
reg reset;initial begin reset = 1’b1; #100 reset = 1’b0;end
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Vectors - I
wire and register can be defined as “vector” form
format [high#:low#] or [low#:high#]
wre a;wire [7:0] bus;wire [31:0] busA, busB, busC;reg clock;reg [0:40] virtual_addr;
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Vectors - II
Subset of vector Partial bits of vector
busA[7]Bus[2:0]Virtual_addr[0:1]
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Vectors - III
Fixed width subset [<starting_bit>+:width] or [<starting_bit>-:width]
reg [255:0] data1;reg [0:255] data2;reg [7:0] byte;
byte = data1[31-:8]; // data1[31:24]byte = data1[24+:8]; // data1[31:24]byte = data2[31-:8]; // data2[24:31]byte = data2[24+:8]; // data2[24:31]
for (j=0; j<=31; j=j+1) // [7:0], [15:8]…[255:248] byte = data[(j*8)+:8];
data1[(byteNum*8)+:8] = 8’b0;
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Integer, Real, and Time Register Data Types – I Integer can represent “signed” number
Real
integer counter;initial counter = -1;
real dalta;initial begin delta = 4e10; delta = 2.13;endinteger i;initial i = delta; // rounded value of 2.13
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Integer, Real, and Time Register Data Types – II Time
Storing simulation time
time save_sim_time;initial save_sim_time = $time;
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Arrays - I
Type: integer, register, time, real, or vector. Dimension: no limit, but dimension must be c
onstant Format
<array_name>[<subscript>]integer count[0:7];reg bool[31:0];time chk_point[1:100];reg [4:0] port_id[0:7];integer matrix[4:0][0:255];reg [63:0] array_4d [15:0][7:0][7:0][255:0];wire [7:0] w_array2 [5:0];wire w_array1[7:0][5:0];
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Array - II
count[5] = 0;chk_point[100] = 0;port_id[3] = 0;matrix[1][0] = 33559;araay_4d[0][0][0][0][15:0] = 0;fffport_id = 0; // error usagematrix[1] = 0; // error usage
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Memories
Array of register
reg mem1bit [0:1023];reg [7:0] membyte [0:1023];
membyte[511]
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Parameters
Define a constant
Can be re-defined at topper level using “defparam”
localparam (Verilog 2001 new feature) Can not be re-defined by “defparam”
parameter port_id = 5;parameter cache_line_width = 256;parameter signed [15:0] WIDTH;
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Strings
Can be assigned to register
reg [8*18:1] string_value;initial string_value = “Hello Verilog World”;
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表 3-3 特殊字元
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Basic Concepts
Lexical Conventions Data Types System Tasks and Compiler Directives Summary
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System Tasks
Displaying information Monitoring information Stopping and finishing
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Displaying information - I
$display (p1, p2, p3,…, pn); Like “printf” in C Format specification list
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Displaying information - II
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Displaying information - III
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Displaying information - IV
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Monitoring Information
$monitor(p1,p2,…, pn); Monitor signal change and output the change
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Stopping and finishing
$stop: stop simulation and enter interactive mode to debug
$finish: end of simulation
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Compiler Directives
`define Define text macro, like #define in C
`include Include the context of another file, like #include in
C
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Usage of `define
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Usage of `include
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Basic Concepts
Lexical Conventions Data Types System Tasks and Compiler Directives Summary
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Summary
Verilog is similar to C Lexical conventions Data Types
Value set, wire, register, vector, integer, real, time, array, memory, parameter, string…
System Tasks $display, $monitor, $stop, $finish
Compiler Directives `define and `include