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S HRINKING PROCESS TECHNOLOGIES andincreasing design sizes have led to highly com-plex, billion-transistor integrated circuits. Testingthese complex ICs to weed out defective partshas become a major challenge. To reduce designand manufacturing costs, testing must be quickand effective. The time it takes to test an ICdepends on test data volume. The rapidly increasing number of transistors in ICs hasspurred enormous growth in test data volume.Techniques that decrease test data volume andtesting time are necessary to increase productioncapacity and reduce test cost.

The latest system-on-a-chip designs integratemultiple ICs (microprocessors, memories,

DSPs, and I/O controllers) on a single piece ofsilicon. SOCs consist of several reusableembedded intellectual-property (IP) cores pro-vided by third-party vendors and stitched intodesigns by system integrators. Testing all thesecircuits when they are embedded in a singledevice is far more difficult than testing themseparately. Achieving satisfactory SOC test qual-ity at an acceptable cost and with minimal

effect on the production schedule is alsobecoming increasingly difcult. High transistor counts and aggressive clock frequenciesrequire expensive automatic test equipment(ATE). More important, they introduce manyproblems into test development and manufac-turing test that decrease product quality andincrease cost and time to market.

ATE costs have been rising steeply. A tester that can accurately test todays complex ICs costsseveral million dollars. According to the 1999

International Technology Roadmap for Semi- conductors (http://public.itrs.net/Files/1999_SIA_Roadmap/Home.htm), the cost of a high-speedtester will exceed $20 million by 2010, and thecost of testing an IC with conventional methodswill exceed fabrication cost. Conventional direct-probe testing methods have become inadequateand are no longer commercially practical. Theincreasing ratio of internal node count to exter-nal pin count makes most chip nodes inaccessi-ble from system I/O pins, so controlling andobserving these nodes and exercising the numer-ous internal states in the circuit under test is dif-cult. ATE I/O channel capacity, speed,accuracy, and data memory are limited.

Therefore, design and test engineers need newtechniques for decreasing data volume.Test resource partitioning offers a promising

solution to these problems by moving some testresources from ATE to chip. Our new TRPapproach, based on test data compression andon-chip decompression, reduces test data vol-ume, decreases testing time, and uses slower testers without decreasing test quality.

Test Resource Partitioningfor SOCs

International Test Conference

80

A new test-resource-partitioning approach, based

on test data compression and on-chip

decompression, reduces data volume, decreases

testing time, and accommodates slower (less

expensive) testers without decreasing test quality.

Anshuman Chandra and Krishnendu ChakrabartyDuke University

0740-7475/01/$10.00 2001 IEEE IEEE Design & Test of Computers


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OverviewThere are three main TRP techniques:

Test set compaction . This technique reducestest data volume by compacting the partial-ly specified test cubes generated by auto-

matic test pattern generation (ATPG)algorithms. It requires no additional hard-ware investment. The test set is compactedthrough dynamic or static compaction pro-cedures. 1,2 However, test set compactionresults in the application of fewer patterns tothe SOC. Because every modeled fault is thusdetected by fewer patterns, this approachcan reduce unmodeled-fault coverage. 3

Built-in self-test . BIST, an alternative to ATE-based external testing, offers several advan-tages: It lets precomputed test sets beembedded in test sequences generated byon-chip hardware, supports test reuse andat-speed testing, and protects intellectualproperty. Although BIST is now extensivelyused for memory testing, it is not as commonfor logic testing. This is particularly true for nonscan and partial-scan designs in whichtest vectors cannot be reordered and apply-ing pseudorandom vectors can lead to seri-ous bus contention problems during testing.Moreover, BIST can be applied to SOCdesigns only if the IP cores are BIST-ready.Because most currently available IP coresare not BIST-ready, BIST insertion in SOCscontaining these circuits is expensive andrequires considerable redesign.

Test data compression . Another way toreduce test data volume is through data com-pression techniques such as statistical, run-length, Golomb, and frequency-directedrun-length (FDR) coding. 4-7These techniques

compress precomputed test set T D, providedby the core vendor, into the much smaller test set T E, which is stored in ATE memory.Figure 1 shows a TRP scheme using test datacompression. An on-chip decoder performspattern decompression to generate T D fromT E during pattern application. Compressingdifference-vector sequence T diff determinedfrom T D decreases test set size and reducestesting time.5-6 Figure 2 shows test architec-tures based on T D and T diff and cyclical scanregisters. However, using T diff and CSRs is notalways necessary. Directly encoding T D canalso achieve signicant compression.

Our TRP approach uses the third technique,which reduces test data volume more than testset compaction and is less expensive than BIST.

Run-length codesTo encode SOC test data, we first decom-

pose it into either xed-length or variable-lengthblocks. We then assign each block a code

81SeptemberOctober 2001

Test head

A T E

m e m o r y

Smallermemory

Lowerbandwidth

Test access mechanism

CPU I/OcontrollerDSPcore

Memory LegacycoreEmbedded

RAM

Decoder

Figure 1. TRP scheme for testing a SOC by storing encoded test

data in ATE memory and decoding it with on-chip decoders.

T E T D

Core under test

Internal scan chainDecoder

T E T diff T D

Decoder

Core under test

Internal scan chain

CSR

(a) (b)

Figure 2. Decompression architectures using precomputed test set T D (a) and a cyclical scan register (CSR) and

difference-vector test set T diff (b).


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word, also of either fixed or variable length.Assigning a fixed-length code word to fixed-length data blocks doesnt lead to significantcompression, so we must consider variable-to-fixed-length and variable-to-variable-lengthencoding.

Variable-to-xed-length: conventional run-length coding

The rst step in encoding test set T D is to gen-erate a fully specied test set with long runs of0s followed by a single 1. Run-length codes canbe used to compress both difference-vector sequence T diff and T D. LetT D = {t 1, t 2, t 3, , t n} bethe (ordered) precomputed test set. A straight-forward heuristic procedure determines theordering. 6 We say that T diff = {d 1, d 2, , d n} = {t 1, t 1

t 2, t 2 t 3, , t n1 t n}, where a bitwise exclu-sive-or operation is carried out between pat-terns t i and t i +1. If uncompacted test set T D isused for compression, all the dont-care bits inT D are mapped to 0s to obtain a fully specied

test set before compression.The next step is to select block size b. Onceb is determined, the runs of 0s are mapped togroups of size M + 1 = 2b. The length of thelongest run of 0s determines the number ofgroups. The set of run lengths {0, 1, 2,, M 1}and a run of M 0s form group A1; the set { M , M + 1, M + 2,, 2 M 1} and a run of 2 M 0s formgroup A2; and so on. In general, the set of run

lengths {(k 1) M , (k 1) M + 1, (k 1) M + 2,,kM 1} and a run of kM comprise group A k. Thecode word size for the kth group is k( M + 1).Table 1 shows the encoding.

Variable-to-variable-length:

Golomb codingThe rst step in the encoding procedure is to

select Golomb code parameter m. For certaindistributions of the input data stream ( T diff, in our case), group size m can be optimally deter-mined. For example, if the input data stream israndom with 0-probability p, then m should bechosen such that pm 0.5. However, becausethe difference vectors for precomputed test setsdo not satisfy the randomness assumption, thebest value of m for test data compression mustbe determined experimentally.

Once group size m is determined, the runsof 0s in the precomputed test set are mappedto groups of size m (each group correspondingto a run length). The length of the longest runof 0s in the precomputed test set determines thenumber of groups. The set of run lengths {0, 1,2, , m 1} forms group A1; the set {m, m + 1,m + 2,, 2m 1} forms group A2; and so on. Ingeneral, the set of run lengths {( k 1)m, (k 1)m + 1, (k 1)m + 2, , km 1} comprisesgroup Ak.

To each group A k, we assign a group prexof (k 1) 1s followed by a 0. We denote this by1(k1)0. Ifm is determined to be a power of 2(that is, m = 2 N ), each group contains 2 N mem-bers, and a sequence (a tail) of log 2(m) bitsuniquely identies each member in the group.Thus, the nal code word for run length L thatbelongs to group A k is composed of twopartsa group prefix and a tail. The prefix is1(k1)0, and the tail is a sequence of log 2(m)bits. Thus, (k 1) = ( L mod m)that is, k = ( Lmod m) + 1. Table 2 shows an example of

Golomb encoding.

Variable-to-variable length: FDR codingThe need for FDR coding arises from the dis-

tribution of runs of 0s in typical test sets. We con-ducted a series of experiments on the largebenchmark circuits from the InternationalSymposium on Circuits and Systems (ISCAS) andstudied the distribution of runs of 0s in T diff


82 IEEE Design & Test of Computers

Table 1. An example of conventional run-length

encoding for block size b = 3.

Group Run length Code word

A1 0 000

1 001

2 0103 011

4 100

5 101

6 110

7 111

A2 8 111000

9 111001

10 111010

11 111011


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obtained from complete single stuck-at test setsfor these circuits. Figure 3 illustrates this distribu-tion for benchmark s9234. We found that the dis-tributions were similar for other circuits test sets.

Figure 3 shows that the frequency of runs of0s of length l

is high for 0 l 20,is very low for l 20, anddecreases rapidly with decreasing l evenwithin the range 0 l 20.

If we use conventional run-length codingwith block size b for compressing such test sets,every run of l 0s, 0 l 2b1, is mapped to a b-bit code word. This is clearly inefcient for thelarge number of short runs of 0s. Likewise, if weuse Golomb coding with code parameter m , arun of l 0s is mapped to a code word with l /m+ 1 + log2(m) bits. This is also inefficient for short runs of 0s. Clearly, test data compressionis more efficient if the more frequently occur-ring runs of 0s are mapped to shorter codewords. This leads us to the notion of FDR codes.

FDR code is constructed as follows: The runsof 0s are divided into groups A 1, A2, A3, , Ak,where k is determined by length l max of longestrun (2 k 3 l max 2k+1 3). Also, a run of length l is mapped to group A j , where j = log2(l + 3) 1 .The i th groups size equals 2 i that is, Ai contains2i members. Each code word consists of twopartsa group prex and a tail. The group pre-x identies the group to which the run belongs,and the tail identies the groups members. Table3 shows an example of FDR encoding.

FDR code has the following properties:

For any code word, prefix and tail are ofequal length. For example, they are each onebit long for A1, two bits long for A2, and so on.The length of the prex for group A i equals i .

For example, the prefix is 2 bits long for group A2.For any code word, the prex is identical tothe binary representation of the run lengthcorresponding to the groups first element.For example, run-length 8 is mapped togroup A3, and this groups first element isrun-length 6. Hence, the prefix of the codeword for run-length 8 is 110.


Table 2. An example of Golomb encoding for group size m = 4.

Group Run length Group prex Tail Code word

A1 0 0 00 000

1 01 001

2 10 010

3 11 011A2 4 10 00 1000

5 01 1001

6 10 1010

7 11 1011

A3 8 110 00 11000

9 01 11001

10 10 11010

11 11 11011

900800700600500400300200100

0

F r e q u e n c y o

f r u n s

1 11 21 31 41 51 61 71 81 91Length of runs of 0s

Figure 3. Distribution of runs of 0s for ISCAS benchmark circuit

s9234.

Table 3. An example of FDR encoding.

Group Run length Group prex Tail Code word

A1 0 0 0 00

1 1 01

A2 2 10 00 1000

3 01 1001

4 10 1010

5 11 1011

A3 6 110 000 110000

7 001 1100018 010 110010

9 011 110011

10 100 110100

11 101 110101

12 110 110110

13 111 110111


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Code word size increases by 2 bits (1 bit for the prex and 1 bit for the tail) as we movefrom group Ai to group Ai +1.

Run lengths are also mapped to groups inconventional run-length and Golomb coding. Inrun-length coding with block size b, the groups

are of equal size, each containing 2b

elements.The number of code bits to which runs of 0s aremapped increases by b bits as we move fromone group to another. On the other hand, inGolomb coding, the group size increases as theruns of 0s growthat is, Ai is smaller than A i +1.However, tails for Golomb code words in dif-ferent groups are of equal length (log 2(m),where m is the code parameter), and the prex

increases by only 1 bit as we move from onegroup to another. Hence, Golomb coding is lesseffective when the runs of 0s spread far from aneffective range determined by m.

Figure 4 compares the three codes, showingthe number of bits per code word for different-

length runs of 0s. Conventional run-length codesperformance is worse than that of Golomb codewhen run-length l exceeds 7. Golomb codes per-formance is worse than that of FDR code for l 24. FDR code outperforms the other two types for runs of lengths 0 and 1. Since these runs fre-quencies are very high for precomputed test sets(Figure 3), FDR codes outperform run-length andGolomb codes for SOC test data compression.

Test data compression anddecompression

Although the on-chip decoder designs aresimilar for the three codes weve described, wediscuss only the Golomb decoder in this article.The decoder is simple, scalable, and indepen-dent of the core under test and the precomput-ed test set. Moreover, because it is small, it doesnot introduce signicant hardware overhead.

The decoder decompresses encoded test setT E and outputs T diff. The exclusive-or gate and theCSR generate test patterns from the differencevectors. A counter of log 2(m) bits and a nite-state machine can efciently implement thedecoder. Figure 5 shows the decoders block dia-gram. The input to the FSM is bit_in, and enablesignal en is used to input the bit whenever thedecoder is ready. Signal inc increments thecounter, and rs indicates that the counter has n-ished counting. Signal out is the decoder output,and v indicates when the output is valid.

The decoder operates as follows:

When the input is 1, the counter counts upto m. Signal en is low while the counter is

busy counting and enables the input at theend of m cycles to accept another bit. Thedecoder outputs m 0s during this operationand makes v high.When the input is 0, the FSM starts decodingthe input code words tail. The number ofoutput 0s depends on the binary value of tailbits. The en and v signals synchronize thedecoders input and output operations.



0 20 40 60 80

Length of runs of 0s

0

10

20

30

N u m

b e r o

f c o

d e w o r d

b i t s

Conventional run-length code (block size b = 3)Golomb code (code parameter m = 4)FDR code

Figure 4. Comparison of code word size (bits) for different run

lengths for FDR code, Golomb code, and conventional run-length

code.

inc

rs

v out

bit_in

en

clk

i = log 2(m)

FSMi -bit

counter

Figure 5. Block diagram of the decoder used for decompression.


6/12

Figure 6 shows the FSM state diagram corre-sponding to the decoder for m = 4. States S0 toS3 and S4 to S8 correspond to prefix and taildecoding, respectively. We synthesized the FSMusing the Synopsys Design Compiler to accessthe decoders hardware overhead. The synthe-

sized circuit contains only four ip-ops and 34combinational gates. For a circuit whose testset is compressed using m = 4, the logic shownin the gate-level schematic is the only addi-tional hardware required other than thecounter. Thus, the decoder is independent ofnot only the core under test but also its pre-computed test set. The amount of extra logicrequired for decompression is small and can beimplemented easilyin contrast to the run-length decoder, which is not scalable andbecomes increasingly complex for higher val-ues of block length b.

Test application timeHere, we analyze the testing time for a single

scan chain using Golomb coding with the testarchitecture shown in Figure 2. The Golombdecoders state diagram indicates that

each 1 in the prefix takes m cycles for decoding,each separator 0 takes one cycle, andthe tail takes a maximum of m cycles and aminimum of = log2(m) + 1 cycles.

We let nC be the total number of bits in T E,and r the number of 1s in T diff. T E contains r tailsand r separator 0s, and the number of prex 1sin T E equals nC r [1 + log2(m)]. Therefore, max-imum and minimum testing times T max and T min,measured by the number of cycles, are

T max = {nC r [1 + log2(m)]}m + r + mr = mnC r [mlog2(m) 1]

T min = {nC r [1 + log2(m)]}m + r + r = mnC rm[1 + log2(m)] (1 + )

Therefore, the difference between T max andT min is

T = T max T min= r [m log2(m) 1]

A major advantage of Golomb coding is thaton-chip decoding can be carried out at scanclock frequency f scan while T E is fed to the coreunder test with external clock frequency f ext > 0

T n r m m m R

m T m r m r m R

m T mR m R m T R m m

N C j j j

m

C j j

m

j j

m

C

C

1 21

21 1

2

2

1 1

1

1

= + ( )[ ]{ }( )+ +( )

= ( ) + +( )

= ( )+= ( )[ ]

=

= =

, log

log

log

log



S8

1/0111

S0 S1

S4

S3S2

S5

0/0101

1/11110/1101

S6 S7

S9

0/10011/1011

0/1001 1/1011

-/10-0 -/10-0

-/10-0 -/10-0

-/11-0

1/0111

0/0101

clk

data_in

clk_stop

v in

data_out

v out

SOCchannel 1 2 3 1 2 34

data_in/clk_stop, v in, data_out, v out

T C = 1010110011011 core 1

core 2core 3core 4

(a)

(b)

Figure 9. State diagram (a) and timing diagram (b) for the SOC channel selector FSM ( m = 4).


10/12

because nC,max >> r max and T C >> R .Consider a hypothetical example of four

cores with an encoded test data size equal tonC,1 = 40,nC,2 = 60,nC,3 = 80,nC,4 = 100, and r 1 = 4,r 2 = 6,r 3 = 8, and r 4 = 10. Therefore, nC,max = 100,r max = 10,m = 4, R = 28, and T C = 280. Finally,

T NI T I = 4[(280 100) (1 + 2)(28 10)] = 504.This analysis shows that the interleaving archi-tecture reduces testing time and increases ATEchannel bandwidth.

We developed a Verilog model of the FSMfor m = 4 and simulated it using T C =1010110011011. We also synthesized the gate-level circuit of the channel selector FSM withthe Synopsys Design Compiler. It contains onlyfour flip-flops and 17 gates. Thus, additionalhardware overhead is small.

Experimental resultsWe performed TRP on the large ISCAS

benchmark circuits. We considered full-scancircuits for the proposed compression anddecompression schemes. For full-scan circuits,we reordered patterns to achieve higher com-pression. For all full-scan circuits, we consid-ered a single scan chain. We computed thecompression percentage as C P = ( T D T E / T D ) 100, where T D is the test set size

and T E is the encoded test set size.For our rst experiment, we used difference-

vector sequences ( T diff) obtained from partiallyspecied test sets (test cubes). Table 4 presentsresults for test cubes obtained using dynamiccompaction with the Mintest ATPG program. 9

The table compares the fully compacted Mintesttest sets with the compression obtained fromFDR, Golomb, and conventional run-length cod-ing. The table lists precomputed (original) testset sizes (T D), encoded test set sizes ( T E), andsmallest ATPG-compacted (Mintest) test setsizes. We used a Sun Ultra 10 workstation with

a 333-MHz processor and 256 Mbytes of DRAM.Table 4 shows that FDR codes provide bet-ter compression than Golomb and conven-tional run-length codes in all cases. (Golombcode results reported here are better than thosereported in an earlier publication 6 because weused an improved pattern-reordering heuristicfor these experiments.) For circuit s38417, theincrease for FDR codes was as much as 7% over

Golomb codes. In all but one case, the encod-ed test set ( T E) size is much smaller than that ofthe Mintest-compacted test set.

The test cubes we used for s35932 werealready highly compacted, so we didnt obtainhigh compression for this circuit. Nevertheless,in contrast to FDR codes, Golomb codes pro-vided insignicant compression, and run-lengthcodes provided no compression for this circuit.On average, the compression obtained withFDR codes was 7.49% higher than that obtainedwith Golomb codes and 19.56% higher thanthat obtained with conventional run-length

codes. Test data compression always leads toencoded test sets smaller than ATPG-compact-ed test sets. 6 Moreover, test data compressiondecreases testing time by several orders of mag-nitude, 10 and substantially reduces power con-sumption during scan testing.

Table 5 demonstrates that using test cubesT D (with all the dont-care bits mapped to 0s)also yields high compression. The advantage


0-/1-00

0-/00-1

--/0--0

1-/00-1

--/0--0

--/11-1

0-/0--0

0-/1--0

--/0--0

1-/10-1

1-/0011

--/1-00

S0

S1

S4

S3

S2

S5 S6

S9 S7

S8

1-/0011

-0/0011

-1/1-00

0-/1--0

--/00-1

S10 S11

bit_in, re/en, out, inc, v

Additional states

Figure 10. Modied state diagram of the

decoder FSM equalizing tail and prex

decoding cycles.


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of using T D for compression is that the decom-pression architecture for on-chip pattern gen-eration doesnt require a separate CSR. For circuits with long scan chains, equally longadditional CSRs increase hardware overheadsignificantly. Therefore, compressing T D togenerate the encoded test set not only yieldssmaller test sets but also reduces hardwareoverhead.

Table 6 shows that Golomb coding lets us usea slower tester without incurring a time penalty.In comparison with external testing using ATPG-compacted patterns, we achieved the same test-ing time using a much slower tester.

Overall, our experimental results for the ISCASbenchmarks show that the compression tech-nique is very efcient for full-scan circuits andthat ATPG compaction is not always necessary tosave ATE memory and reduce testing time.

T EST DATA COMPRESSION offers a solution to

the TRP problem for SOC designs. We are cur-rently working on reduced-pin-count-testing(RPCT) and BIST techniques using test datacompression.

AcknowledgmentsThis research was supported in part by

National Science Foundation grant CCR-9875324and in part by an Intel equipment grant.



Table 4. Compression obtained using various T diff sequences.

Run-length Golomb FDR T E size Mintest

T D size compression compression compression with FDR test set

Circuit (bits) (%) for b = 3 (%) (%) (bits) size (bits)

s5378 23,754 44.49 53.73 61.32 9,188 20,758

s9234 39,273 49.63 59.85 60.63 15,460 25,935s13207 165,200 58.75 84.33 87.67 20,368 163,100

s15850 76,986 52.15 66.55 71.95 21,590 57,434

s35932 28,208 None 2.27 25.74 20,946 19,393

s38417 164,736 46.82 58.08 65.35 57,066 113,152

s38584 199,104 48.52 59.61 64.67 70,328 161,040

Table 5. Compression obtained using T D.

Run-length Golomb FDR T E size Mintest

T D size compression compression compression with FDR test set

Circuit (bits) (%) for b = 3 (%) (%) (bits) size (bits)

s5378 23,754 35.72 37.11 48.02 12,346 20,758

s9234 39,273 42.12 45.25 43.59 22,152 25,935

s13207 165,200 56.83 79.74 81.30 30,880 163,100

s15850 76,986 47.98 62.82 66.22 26,000 57,434

s35932 28,208 None None 19.37 22,744 19,393

s38417 164,736 32.53 28.37 43.26 93,466 113,152

s38584 199,104 42.21 57.17 60.91 77,812 161,040

Table 6. Comparison between external clock frequency f ext ,

required for Golomb-coded test data, and external clockfrequency f ext , required for external testing with ATPG-compacted patterns (for the same testing time).

Circuit m r n C pn f ext /f exts9234 4 5,039 22,250 25,935 1.93

s13207 16 6,716 41,658 163,100 9.90

s15850 4 8,702 40,717 57,434 2.25

s38417 4 20,165 92,054 113,152 1.99

s38584 4 23,320 104,111 161,040 2.54


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Architectures Based on Golomb Codes, IEEE

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Anshuman Chandra is aPhD candidate in electricaland computer engineering atDuke University. His researchinterests include VLSI design,

digital testing, and computerarchitecture. Chandra has a BE in electrical engi-neering from the University of Roorkee, Roorkee,India, and an MS in electrical and computer engi-neering from Duke University. He is a studentmember of the IEEE and ACM SIGDA.

Krishnendu Chakrabartyis an assistant professor ofelectrical and computer engi-neering at Duke University.His research interests in-clude system-on-a-chip test-

ing, embedded real-time operating systems,distributed sensor networks, and architecturaloptimization of microelectrofluidic systems.Chakrabarty has a BTech from the Indian Insti-tute of Technology, Kharagpur, and an MSE anda PhD from the University of Michigan, Ann Arbor,all in computer science and engineering. He is asenior member of the IEEE and a member of theACM SIGDA and Sigma Xi. He is the vice chair oftechnical activities in the IEEE Computer Soci-etys Test Technology Technical Council.

Direct questions or comments about this arti-cle to Anshuman Chandra, Duke University,Dept. of Electrical and Computer Engineering,130 Hudson Hall, Box 90291, Durham, NC27708; [email protected].

For further information on this or any other com-

puting topic, please visit our Digital Library athttp://computer.org/publications/dlib.


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