Challenges in IoT, Automotive and Power …...FlowCAD om 21 FlowCAD ConfidentialFlowCAD (Deutschland) FlowCAD (Schweiz) Mozartstrasse Hintermättlistrasse2 85622 Feldkirchen bei München

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Challenges in IoT, Automotive and Power

Electronics Designs

Simon Zubler

31. Mai 2016, Embedded Computing Conference

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Herausforderungen

• Mehr Funktionen

• Anpassbarkeit der Produkte

• Parallele Entwicklung (HW, SW)

• Änderungen am Produkt

• Zunehmende Komplexität

• Time to Market

• Mehr Projekte

• Gleichbleibende Ressourcen

• Konkurrenz

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Trial and Error

• Zeitverlust

• Kosten

Design Create Prototype Measure/Test

Fix issues

Release

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Abhilfen

• Time to Market verkürzen

• Plattformentwicklung

• Änderungsmanagement

• Virtual Prototyping

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Virtual Prototyping

• Simulation über den gesamten Entwicklungsprozess

• Ermöglicht Innovationen

• Zeit sparen

• Kosten sparen

Simulation of design concept

Simulation of

preliminary designs

Simulation of final design

Create prototype

Verification Release

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Virtual Prototyping

• Physische Tests auf ein Minimum reduzieren

– Szenarien virtuell testen

• Funktionale Simulation von kompletten Systemen

– Während der Entwurfsphase

– Toleranzen (Werte, Timing)

• Thermisches Verhalten von Baugruppen

– Eigenerwärmung

– Kühlkonzept

• Luft- und Kriechstrecken

– Leiterplatte

– Gehäuse

• Leiterplattenentwurf

– Impedanzen und Kopplung, Resonanzen und Abstrahlung

– Energieversorgung, Stromdichte, Kondensatoren

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Luft- und Kriechstreckenanalyse mit NEXTRA

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Thermische Simulation mit 6SigmaET

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PSpice virtual prototyping PCB systems

PSpice® Analog Behavioral

PSpice Functional Block Defined in C

PSpice SPICE Macro-Model

Cadence, the Cadence logo, Virtuoso, MMSIM and PSpice are registered trademarks of Cadence

Design Systems, Inc. All other trademarks are the property of their respective owners.

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PSpice Models

Algorithmic Models (Matlab / C/C++)

System Models (SystemC)

Digital Models with IO/Timing/Constraint

Digital Functional Models

PSpice Behavioral Models

Compact Device Models

Model Abstractions

Architectural

Functional

Behavioral

Gate Level

Circuit Level

Physical Implementation

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IoT Design with PSpice Io

T

Te

stb

en

ch

Ps Vp(t)

DOUT

DIN Pr Vr(t) DAC

ADC Sensor [pressure => Vp(t)]

Regulator Δ pressure <=Vt(t)]

PSpice Mixed Signal

Controller Virtual Platform

RTL

Tra

nsa

cto

r

Hardware SystemC Testbench to

Represent IoT Environment

HIL

Hardware

in Loop

I/O

, T

imin

g &

Constr

ain

t M

odels

Minimal Modeling Effort

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Power Aware SI Analyse mit Sigrity

Current will take the way with least

resistance

• DC: ohm Resistance

• AC: Impedance

Forward and return current build a

circuit. Loops and stubs create

antennas and cause EMI issues.

AC

DC

AC

Layer stack up

with

Reference plane

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Signal Integrity Issues

VH

VL

Multi-Crossing Error

VH

VL

5V

GND

Overshoot / Undershoot

VH

VL

Oscillation

VH

VL

Threshold Error

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SI-Problems are hard to “see”

• Let’s just look at two trace segments on a 6-layer PCB

• We see:

– 2 trace segments

– Same width

– Same impedance

– Different trace length

• Where is the problem?

trace9047 trace9048

trace9048

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What about the return path (reference planes)

• Trace9047 – 1 uniform impedance section

• Trace9048: – 4 different impedance sections

• No ideal plane layers! – Directly above and below

– Impedance discontinuities

• Does this matter?

– Depends

trace9048

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ERC – Trace coupling

• Trace9047 is one uniform

impedance section

• Trace9047 broken into 5

sections based on trace

coupling

– two section with no coupling

(1 & 5)

– two sections 2-line coupling

(2 & 4)

– one section 3-line coupling

(3)

1

2

3

3

4

5

1 2

3 4

5

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Graphical overlay on layout

Easy to locate source of trouble

• Impedance

• Coupling

Impedance Overlay Layout view

Ref. disconn.

due to

conjoined via

anti-pads

Reference discontinuities

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Coupling Coefficient Plot

• Diagram shows coupling

– Critical segments are in upper region

– Cross probing to see layout location

– Solution: Change layout with more spacing

Reference

discontinuitie

s

Double click for cross probing

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Typical Applications

• Screen board and identify worst case for further

analysis

• Investigate SI impact of design rule violations and

trade-offs

• Find out how to fix SI problems shown in SRC

simulation

• ERC is used to locate the problem

• Compare against ERC/SRC results with

– Known-good design

– Reference design

– Part of the design that has been fully analyzed

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FlowCAD Professional Services

• Workshops

– http://www.flowcad.ch/de/news/events

– 14. Juni 2016: Sigrity ERC/SRC

• Trainings

– http://www.flowcad.ch/de/support-training/training

• Consulting

– http://www.flowcad.ch/de/services/consulting

• Auftragssimulation

– http://www.flowcad.ch/de/services

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FlowCAD Confidential

FlowCAD (Deutschland)

Mozartstrasse 2

85622 Feldkirchen bei München

Tel: +49 (89) 4563-7770

Fax:+49 (89) 4563-7790

[email protected]

FlowCAD (Schweiz)

Hintermättlistrasse 1

5506 Mägenwil

Tel: +41 (0) 56 485 91 91

Fax: +41 (0) 56 485 91 95

[email protected]

FlowCAD (Polen)

ulica Sasiedzka 2A

80-298 Gdansk

Tel: +48 58 342 75 94

Fax. +48 58 342 70 60

[email protected]

Für weitere Fragen und Informationen stehen wir gerne zur Verfügung

• Please don‘t hesitate to contact us

Kontakt zu FlowCAD / contact us

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