Challenge for Analog Circuit Testing in Mixed-Signal SoC

Challenge for Analog Circuit Testing

in Mixed-Signal SoC

Haruo Kobayashi Professor, Gunma University

[email protected]

Dec. 16, 2016

Contents

1. Introduction

2. Review of Analog Circuit Testing

in Mixed-Signal SoC

3. Research Topics

4. Challenges & Conclusion

1. Introduction

Cost and Quality for Test Cost

● Analog portion continues to be

difficult part of SoC test.

● Concept of “cost” and “quality” makes

“issues and challenges of

analog circuit testing in mixed-signal SoC”

clear and logical.

● LSI testing technology

reduces cost and improves quality

simultaneously.

2. Review of Analog Circuit Testing

in Mixed-Signal SoC

Management Strategy

● Strategy 1 :

Use low cost ATE and develop analog

BIST/BOST to make testing cost lower.

● Strategy 2 :

Use high-end mixed-signal ATE

as well as its associated services & know how.

Fast time-to-market & no BIST

can make profits much more than testing cost.

ATE: Automatic Test Equipment

BIST: Built-In Self-Test, BOST: Built-Out Self-Testy

Save or Earn

Low Cost Testing

Ideal : No testing

● Design guarantee

● 100% chips work well

Reality :

● Low cost ATE

● Short testing time

● Multi-site testing

● Minimum or no chip area penalty for BIST

● Extensive usage of BOST

A penny saved is a penny earned.

Test and Measurement are different

● Production Test : 100% Engineering

Decision of “Go” or “No Go”

For example, it can be performance comparison

between DUT and “Golden Device”.

● LSI testing is manufacturing engineering.

● Measurement : 50% Science, 50% Engineering

Accurate performance evaluation of circuit

Measurement can be costly, but testing should be at low cost.

DUT: Device Under Test

Analog BIST

● BIST for digital : Successful

BIST for analog : Not very successful

Challenging research

● Digital test : Functionality Easy

Analog test : Functionality & Quality Hard

● In many cases

- Analog BIST depends on circuit.

- No general method like scan path in digital.

- One BIST, for one parameter testing

Analog: parametric fault as well as fatal fault.

Prof. A. Chatterjee

Specification-based Test Alternative Test Defect-based Test

RF / High-Speed IO / Power Device Testing

● RF / HSIO / Power testing is different

from analog testing technology.

● These testing technologies are

other challenging areas.

● RF testing items examples:

- EVM test

- System level testing, GSM/EDGE

- AM/PM distortion

- Jitter, Phase noise

Robust Design and Testing

Robust design makes its testing difficult.

● Feedback suppresses

parameter variation effects.

● Self-calibration and redundancy

hide defects in DUT.

● Secure DUT is difficult to test.

+

R1 R2

Robust design (yield enhancement) and testing cost reduction

are trade-off.

ATE for Mixed-Signal Testing

● Analog part is costly for development.

● Analog BIST is also beneficial

for mixed-signal ATE manufacturer

● ATE must be designed with today’s technology

for tomorrow’s higher performance chip testing.

Interleaved ADC used in ATE

to realize very high sampling rate

with today’s ADCs

Low Cost ATE

● Digital ATE

- No analog option such as

Arbitrary Waveform Generator: AWG

- Input/output are mainly digital.

● Replacement of analog ATE with digital ATE

- Multi-site testing becomes possible.

- Still short testing time is important.

● Secondhand ATE, In-house ATE

● ATE with well balanced modular hardware

and software

Cooperation among Engineers

● Collaboration is important

- Circuit designer

- LSI testing engineer

- ATE manufacturer engineer

- Management

- LSI testing researcher in academia

● Strong background of analog circuit design

as well as LSI testing are required

for analog testing research.

3. Research Topics

Collaboration with Socionext Inc.,

STARC and other related industries

Phase Noise Test with ΔΣ TDC

BOST solution

TDC BOSTs for Timing Signal Testing

BOST solution

[2] R. Jiang, H. Kobayashi, Y. Ozawa, R. Shiota, K. Hatayama, et. al.,

“Successive Approximation Time-to-Digital Converter with Vernier-level Resolution”,

IEEE International Mixed-Signal Testing Workshop, Catalunya, Spain (July 4-6, 2016).

On-chip Jitter Measurement Circuit

BIST solution

DFT for SAR ADC Linearity

BIST Solution

[4]

Low IMD3 2-Tone Signal Generation with AWG for Communication Application ADC Testing

Low Cost ATE

Multi-tone Curve Fitting Algorithm for Communication Application ADC

Algorithm

Complex Multi-Bandpass ΔΣ Modulator for I-Q Signal Generation

ATE for Mixed-Signal Testing

Time Interleaved ADC in ATE System ATE for Mixed-Signal Testing

4. Challenges & Conclusion

Challenges of Analog Testing

● Use all aspects of technologies

- Circuit technique

- Cooperation among BIST, BOST & ATE

as well as software & network

- Signal processing algorithm

- Use resources in SOC

such as μP core, memory, ADC/DAC

There is no science without measurement.

There is no production without test

No royal road to analog testing

Explicit Analysis of Channel Mismatch Effectsin Time-Interleaved ADC Systems

N.Kurosawa, K.Maruyama, H.Kobayashi,

H.Sugawara and K.Kobayashi yGunma University, Japan y Teratec Corp. Japan

発表内容

1. 研究の目的

2. インターリーブADCの原理と問題点

3. ミスマッチが独立して存在する場合の影響

4. ミスマッチが同時に存在する場合の影響

5. 帯域ミスマッチの影響

6. まとめ1

1.研究の目的

2

研究の目的

インターリーブ・アーキテクチャを用いて

最高速のADCを実現する場合の、システム上の問題の理論解析を行う。

3

2.インターリーブADCの原理と問題点

4

高速・高精度ADCの構成

² 高速ADCの構成± 大部分の回路が比較的低い周波数のクロックで動作± 周波数の高い信号の発生が不要± 周波数の高い信号が不要± タイミングの問題が少ない (例:タイミングスキュー)

² 高精度ADCの構成± 高精度回路が不要± 大きなプロセス変動を許容± 低ノイズ回路・デバイスが不要例: デルタ・シグマADC

¦ サブミクロンCMOSのアナログCMOS回路!高精度回路が不要!低ノイズ回路が不要

5

マルチプロセッサ構成

² デジタルの世界では、マルチプロセッサ構成は非常に一般的± 多くの低性能プロセッサ± 高性能を実現

² 問題点± ソフトウエア開発の負担が重い± マルチプロセッサの性能 ¿ プロセッサ１個のM倍の性能

M：プロセッサ数

6

インターリーブADCの原理と問題点

² M個のADCのインターリーブでM倍のサンプリングレートを実現± マルチプロセッサ構成の観点から、非常に効果的± サンプリングレートの高いADCに適している

² チャネル間ミスマッチによってS/Nが低下通常キャリブレーションが必要

7

アナログ回路システムのミスマッチ

² 回路レベルのミスマッチ例:差動ペアのオフセットVos

(Vos)rms / 1pW L

² システムレベルのミスマッチ例:インターリーブADCのチャネル間のミスマッチ

8

3.ミスマッチが独立して

存在する場合の影響

9

チャネル間ミスマッチの影響

- オフセットミスマッチの影響

10

オフセットミスマッチのモデル

11

オフセットミスマッチの時間領域での影響

² パターンノイズ± ほぼ入力周波数と独立± 加算的ノイズ± fs=M周期

fs :サンプリング周波数M :チャンネル数

² 4チャンネルADCのシミュレーション± 正弦波入力

ADCシステムの出力とエラー

12

オフセットミスマッチの周波数領域での影響

² パターンノイズの周波数± fnoise = k £ fs=M

k = 1; 2; 3; ¢ ¢ ¢fs :サンプリング周波数M :チャンネル数

² 4チャンネルADCのシミュレーション± 8192点FFT

ADC出力のパワースペクトラム

13

オフセットミスマッチのS/Nへの影響

² 4チャンネル6ビットADCのシミュレーション

² オフセットミスマッチ：S/Nは入力周波数に独立ノイズレベルは入力振幅に独立

ADCシステムのS/N

14


- ゲインミスマッチの影響

15

ゲインミスマッチのモデル

16

ゲインミスマッチの時間領域での影響

² パターンノイズ± 入力正弦波のピークでエラー最大± 乗算的ノイズ (AMノイズ)



17

ゲインミスマッチの周波数領域での影響

² パターンノイズの周波数± fnoise = fin § k £ fs=M

k = 1; 2; 3; ¢ ¢ ¢fs :サンプリング周波数fin :入力周波数M :チャンネル数

² 4チャンネルADCのシミュレーション± 8192点FFT


18

ゲインミスマッチのS/Nへの影響


² ゲインミスマッチ：S/Nは入力周波数に独立

入力振幅に独立


19


- タイミングスキューの影響

20

タイミングスキューのモデル

21

タイミングスキューの出力への影響

22

タイミングスキューの時間領域での影響

² パターンノイズ± 入力正弦波のゼロ交差

(スルーレート最大)付近で最大のエラー

± ゲインミスマッチとは逆± PMノイズ



23

タイミングスキューの周波数領域での影響

² パターンノイズの周波数± fnoise = fin § k £ fs=M

k = 1; 2; 3; ¢ ¢ ¢fs :サンプリング周波数fin :入力周波数M :チャンネル数

± ゲインミスマッチの場合と同じ² 4チャンネルADCのシミュレーション

± 8192点FFT


24

タイミングスキューのS/Nへの影響


² タイミングスキュー：S/Nは± 入力周波数が高くなると共に低下

± 入力振幅に独立


25

4.ミスマッチが同時に

存在する場合の影響

26

ミスマッチが同時に存在する場合の影響

- 2チャンネルADC

27

2ch ADCに複数のミスマッチが同時に存在する場合のモデル

Vin(t) = A cos (2¼fint)Vout(nTs)

=

8<: AG1 cos f2¼fin (nTs + ±t1)g+os1 (n : odd)AG2 cos f2¼fin (nTs + ±t2)g+os2 (n : even)

=

8>><>>:AG (1 ¡ ®) cos

½2¼fin

µnTs ¡ ±t

2

¶¾+oscm¡osdiff (n : odd)

AG (1 + ®) cos½2¼fin

µnTs + ±t

2

¶¾+oscm+osdiff (n : even)

(n = 0; §1; §2; ¢ ¢ ¢)

28

2ch ADCに複数のミスマッチが同時に存在する場合の出力

Vout(nTs) = As cos (2¼finnTs + µs)

+An cos

8<:2¼

0@¡fin +1

2fs

1A nTs + µn

9=;+ oscm + osdiff cos

8<:2¼

0@1

2fs

1A nTs

9=;

As = AGr

cos2 (¼fin±t) + ®2 sin2 (¼fin±t)

An = AGr

®2 cos2 (¼fin±t) + sin2 (¼fin±t)

µs = arctan f® tan (¼fin±t)gµn = arctan ftan (¼fin±t) =®g

29

2ch ADCに複数のミスマッチが同時に存在する場合の出力のパワースペクトラム

30

解析式と数値計算の結果が一致

+解析式の正当性を確認

31

2ch ADCに複数のミスマッチが同時に存在する場合のSNRの低下

32

ミスマッチが同時に存在する場合の影響


33

4ch ADCに複数のミスマッチが同時に存在する場合のモデル

Vin(t) = A cos(2¼fint)Vout(nTs) =8>>>>><>>>>>:

AG1 cos f2¼fin (nTs + ±t1)g + os1 (n = 4m)AG2 cos f2¼fin (nTs + ±t2)g + os2 (n = 4m + 1)AG3 cos f2¼fin (nTs + ±t3)g + os3 (n = 4m + 2)AG4 cos f2¼fin (nTs + ±t4)g + os4 (n = 4m + 3)

(m = 0; §1; §2; ¢ ¢ ¢)34

4ch ADCに複数のミスマッチが同時に存在する場合の出力

Vout(nTs) =

rA2

sc + A2ss cos

(2¼finnTs ¡ arctan

ÃAss

Asc

!)

+

rA2

n1c + A2n1s cos

8<:2¼

Ãfin +

1

4fs

!nTs ¡ arctan

0@An1s

An1c

1A9=;+

rA2

n2c + A2n2s cos

8<:2¼

Ãfin +

1

2fs

!nTs ¡ arctan

0@An2s

An2c

1A9=;+

rA2

n3c + A2n3s cos

8<:2¼

Ãfin +

3

4fs

!nTs ¡ arctan

0@An3s

An3c

1A9=;+

1

4(os1 ¡ os2 + os3 ¡ os4) cos

(2¼

Ã1

2fs

!nTs

)

+1

2

r(os1¡os3)2+(os2¡os4)2 cos

8<:2¼

Ã1

4fs

!nTs¡arctan

0@os2¡os4

os1¡os3

1A9=;+

1

4(os1 + os2 + os3 + os4)

35

4ch ADCに複数のミスマッチが同時に存在する場合の出力のパワースペクトラム

36

解析式と数値計算の結果が一致

+解析式の正当性を確認

37

4ch ADCに複数のミスマッチが同時に存在する場合のSNRの低下

38

5.帯域ミスマッチの影響

39

ADCの一次遅れ系近似

H (j2¼f) =1

1 + jfin=fc

ゲイン jH (j2¼f) j = 1=

r1 + (fin=fc)

2

位相 6 H (j2¼f) = ¡ arctan (fin=fc)

Vin(t) = cos (2¼fint)のとき

Voutk(nTs) = Gk cos (2¼finnTs + µk)

40

帯域ミスマッチの影響


41

2ch ADCに帯域のミスマッチが存在する場合のモデル

Vin(t) = A cos (2¼fint)Vout(nTs)

=

8<: A=q

1 + (fin=fc1)2 cosf2¼finnTs¡arctan (fin=fc1)g (n : odd)

A=q

1 + (fin=fc2)2 cosf2¼finnTs¡arctan (fin=fc2)g (n : even)

=

(AG1 cos (2¼finnTs + µ1) (n : odd)AG2 cos (2¼finnTs + µ2) (n : even)

(n = 0; §1; §2; ¢ ¢ ¢)

² 帯域のミスマッチ± ゲインと位相のミスマッチ± ゲインミスマッチとタイミングスキューに相似± ゲイン,位相は周波数の関数

42

2ch ADCに帯域のミスマッチが存在する場合の出力

Vout(nTs) = As cos (2¼finnTs + µs)

+An cos

(2¼

Ã¡fin +

1

2fs

!nTs + µn

)

As =1

2A

rG2

c cos2 (µd) + G2d sin2 (µd)

An =1

2A

rG2

c sin2 (µd) + G2d cos2 (µd)

µs =arctan

8<:Gc sin (µc) cos (µd) + Gd cos (µc) sin (µd)

Gc cos (µc) cos (µd) ¡ Gd sin (µc) sin (µd)

9=;µn =¡ arctan

8<:Gc cos (µc) sin (µd) + Gd sin (µc) cos (µd)

Gc sin (µc) sin (µd) ¡ Gd cos (µc) cos (µd)

9=;Gc = G1 + G2 ; Gd = G1 ¡ G2

µc = (µ1 + µ2) =2 ; µd = (µ1 ¡ µ2) =2

43

2ch ADCに帯域のミスマッチが存在する場合の出力のパワースペクトラム

44

解析式と

Spiceシミュレーション結果が一致+

解析式の正当性を確認

45

2ch ADCに帯域のミスマッチが存在する場合のSNRの低下

fm:平均カットオフ周波数

46

帯域ミスマッチの影響


47

4ch ADCに帯域のミスマッチが存在する場合のモデル

Vin(t) = A cos (2¼fint)Vout(nTs) =8>>>>><>>>>>:

G1 cos (2¼finnTs + µ1) (n = 4m)G2 cos (2¼finnTs + µ2) (n = 4m + 1)G3 cos (2¼finnTs + µ3) (n = 4m + 2)G4 cos (2¼finnTs + µ4) (n = 4m + 3)

(m = 0; §1; §2; ¢ ¢ ¢)

48

4ch ADCに帯域のミスマッチが存在する場合の出力

Vout(nTs) =

rA2

sc + A2ss cos

(2¼finnTs ¡ arctan

ÃAss

Asc

!)

+

rA2

n1c + A2n1s cos

8<:2¼

Ãfin +

1

4fs

!nTs ¡ arctan

0@An1s

An1c

1A9=;+

rA2

n2c + A2n2s cos

8<:2¼

Ãfin +

1

2fs

!nTs ¡ arctan

0@An2s

An2c

1A9=;+

rA2

n3c + A2n3s cos

8<:2¼

Ãfin +

3

4fs

!nTs ¡ arctan

0@An3s

An3c

1A9=;Asc; Ass; An1c; An1s; An2c; An2s; An3c; An3sは

fin; fc1; fc2; fc3; fc4の関数

49

4ch ADCに帯域のミスマッチが存在する場合の出力のパワースペクトラム

50

解析式と

Spiceシミュレーション結果が一致+

解析式の正当性を確認

51

6.まとめ

52

研究成果

インターリーブADCのミスマッチの影響について

² 複数のミスマッチが同時に存在する場合の解析式を導出² 帯域のミスマッチが存在する場合の解析式を導出² 実際のアプリケーションの80%以上をカバーする

2チャンネルと4チャンネルについて解析

53

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 48, NO. 3, MARCH 2001 261

Explicit Analysis of Channel Mismatch Effects inTime-Interleaved ADC Systems

Naoki Kurosawa, Haruo Kobayashi, Member, IEEE, Kaoru Maruyama, Hidetake Sugawara, and Kensuke Kobayashi

Abstract—A time-interleaved A–D converter (ADC) system isan effective way to implement a high-sampling-rate ADC withrelatively slow circuits. In the system, several channel ADCsoperate at interleaved sampling times as if they were effectively asingle ADC operating at a much higher sampling rate. However,mismatches such as offset, gain mismatches among channel ADCsas well as timing skew of the clocks distributed to them degradeS/Nof the ADC system as a whole. This paper analyzes the channelmismatch effects in the time-interleaved ADC system. Previousanalysis showed the effect for each mismatchindividually, howeverin this paper we deriveexplicit formulas for the mismatch effectswhen all of offset, gain and timing mismatches exist together. Wehave clarified that the gain and timing mismatch effects interactwith each other but the offset mismatch effect is independent fromthem, and this can be seen clearly in frequency domain. We alsodiscuss the bandwidth mismatch effect. The derived formulas canbe used for calibration algorithms to compensate for the channelmismatch effects.

Index Terms—A–D converter, analog circuit, calibration,channel mismatch, interleave, track/hold circuit.

I. INTRODUCTION

E LECTRONIC devices are continuously getting faster andaccordingly, the need for instruments such as digitizing

oscilloscopes and large scale integrated (LSI) circuit testers tomeasure their performance is growing. A–D converters (ADCs)incorporated in such instruments have to operate at a very highsampling rate. This paper studies theoretical issues of a time-in-terleaved ADC system where several channel ADCs operate atinterleaved sampling times as if they were effectively a singleADC operating at a much higher sampling rate [1]–[7]. Fig. 1shows such an ADC system where each channel ADCsADC ADC ADC operates with one of phase

clocks , respectively. The samplingrate of the ADC as a whole is times the channel samplingrate. This time-interleaved ADC system is an effective wayto implement a high-sampling-rate ADC with relatively slowcircuits, and is widely used. Ideally, characteristics of channelADCs should be identical and clock skew should be zero.However, in reality there are mismatches such as offset, gainmismatches among channel ADCs as well as timing skew ofthe clocks distributed to them, which cause so-calledpatternnoise and significantly degradeS/N (effective bits) of the

Manuscript received June 13, 2000; revised October 11, 2000. This paper wasrecommended by Associate Editor G. Palumbo.

N. Kurosawa, H. Kobayashi, K. Maruyama, and H. Sugawara are with the De-partment of Electronic Engineering, Gunma University, Kiryu 376-8515, Japan(e-mail: [email protected]).

K. Kobayashi is with Teratec Corporation, Tokyo 168–8501, Japan.Publisher Item Identifier S 1057-7122(01)02200-0.

Fig. 1. Time-interleaved ADC system.

ADC system as a whole. Hence calibration often has to beincorporated to ensure uniformity among the characteristicsof the channels. It is important to clarify the issues of theinterleaved ADC architecture for designing the system. Thischannel mismatch in the interleaved ADC system may be calledassystem level mismatchor module level mismatch, while, forexample, a random offset voltage in a CMOS differential paircircuit due to device size and threshold voltage mismatchesmay be called ascircuit level mismatch.

This paper first reviews interleaving issues, the effects ofoffset, gain and timing mismatchesindividually [4]–[11]. Then,we will deriveexplicit formulas for the mismatch effects whenall of offset, gain and timing mismatches exist together, andshow that the gain and timing mismatch effects interact eachother but the offset mismatch effect is independent from them.We also analyze the bandwidth mismatch effect. The derivedformulas can be used for calibration algorithms to compensatefor the channel mismatch effects. In this paper, we concentrateon two-channel and four-channel interleaved systems becausethey cover most of the practical applications. Eight-channel orothers may be sometimes used in practical situation, and theextension of the results here to an interleaved system of otherchannels is also possible.

Hereafter, we will use following notations:number of channel ADCs in the ADC system;pattern noise frequency of the ADC output;input frequency applied to the ADC system;sampling frequency of the ADC system;sampling frequency of each channel ADC.

II. I NDIVIDUAL CHANNEL MISMATCH EFFECTS

This section reviews the effects of offset, gain and timing mis-matchesindividually in interleaved ADC systems [4]–[11].

1057–7122/01$10.00 © 2001 IEEE

262 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 48, NO. 3, MARCH 2001

Fig. 2 Offset mismatch effect. (a) Offset mismatch model.V os represents the offset ofkth channel(k = 1; 2; � � � ; M). (b) ADC output and error signals intime domain for a sinusoidal input. (c) ADC output power spectrum.

A. Offset Mismatch Effects

Suppose that the offsets of each channel are different and theother characteristics are identical (Fig. 2). This mismatch causesfixed pattern noisein the ADC system. For a dc input, eachchannel may produce a different output code and the period ofthis error signal is . The pattern noise is almost indepen-dent of the input signal in time and frequency domains, and itis additive noise in time domain while in frequency domain itcauses noise peaks at

The S/N degradation of the ADC system (total pattern-noisepower) due to the offset mismatch is constant regardless of theinput frequency and amplitude (Fig. 3).

B. Gain Mismatch Effects

Suppose that the gains of each channel are different and theother characteristics are identical (Fig. 4). If a sinusoidal input

Fig. 3. Simulation results ofS/Nversusf of a four-channel 6-bit interleavedADC system in offset, gain and timing mismatch cases.

KUROSAWA et al.: EXPLICIT ANALYSIS OF CHANNEL MISMATCH EFFECTS IN TIME-INTERLEAVED ADC SYSTEMS 263

Fig. 4. Gain mismatch effect. (a) Gain mismatch model.G represents the gain ofkth channel(k = 1; 2; . . . ; M). (b) ADC output and error signals in timedomain for a sinusoidal input. (c) ADC output power spectrum.

signal is applied to the system, the largest difference in channeloutputs occurs at the peaks of the sine wave. As with the offsetmismatch case, the basic error occurs with a period of butthe magnitude of the error is modulated by the input frequency

. Thus, the pattern noise due to gain mismatch is multiplica-tive in time domain—which is like amplitude modulation (AM)noise—while noise spectrum peaks are at

depends on (Fig. 4) while theS/Ndegradation of theADC system due to the gain mismatch is independent of(Fig. 3). Also, note that in the offset mismatch case, theS/Ndegradation (noise power) is independent of the amplitude of theinput but in the gain mismatch case, it depends on the amplitude.

C. Clock Timing Error Effects

There are two kinds of timing errors in an interleaved ADCsystem, clock skew (systematic error) and clock jitter (randomerror). Clock jitter effects are unavoidable in any ADC system

but the interleaved architecture also suffers from clock skeweffects. Suppose that the clocks haveskews (Fig. 5). This skew causes noise inthe ADC system, and in the time domain the largest error oc-curs when the input signal has the largest slew rate, or crosseszero, which is like phase modulation (PM) noise (Fig. 6). Theenvelope of the error signal is the largest at the zero-crossingswith a period of . It is shifted by 90 deg compared to thegain mismatch case. In the frequency domain, as with the gainmismatch case, the basic error occurs with a period of andthe magnitude of the error is modulated by the input frequency

. The noise spectrum peaks are at

Note, thatS/Ndegrades as increases (Fig. 3).Remark: In offset and gain mismatch cases, the signal power

at the output keeps constant asincreases. On the other hand,in the timing skew case, the signal power at the output decreasesas increases, while the total power of the signal and the errorat the output keeps constant.


Fig. 5. Clock skew: (a) Ideal clock timing. (b) Clock timing with skews ofdt ; dt ; . . . ; dt . (c) Timing skew causes error for the sampled data.

Fig. 6. Timing skew effect. (a) Timing skew model.dt represents the skew ofkth clock(k = 1; 2; . . . ; M). (b) ADC output and error signals in time domainfor a sinusoidal input. (c) ADC output power spectrum.

III. COMBINED CHANNEL MISMATCH EFFECTS

In this section, we will deriveexplicit formulas for the mis-match effects when all of offset, gain and timing mismatchesexist together, and show that the gain and timing mismatch ef-fects interact each other but the offset mismatch effect is inde-pendent of them.

A. Two-channel Interleaved ADC

First, we consider a two-channel interleaved ADC system.Fig. 7 shows its configuration where each of two-channel ADCs(ADC , ADC ) operates with one of two-phase clocks (,with a period of ), respectively. The sampling rate (, where

) of the ADC as a whole is twice the channel samplingrate. However, as mentioned before, this interleaved ADC


Fig. 7. Two-channel time-interleaved ADC system.

system suffers from channel mismatch effects [8], [9], [11]:gain mismatch, offset mismatch and timing mismatch. Ideally,ADC and ADC should be identical. However, in reality, theirgains and offsets may be different from each other, and alsothe sampling timings may deviate from and . Let thegains of ADC , ADC be , respectively, and their offsetsbe , respectively. Also, let the sampling timing devia-tions from for ADC and for ADC be , respec-tively. Suppose that the input to the ADC is a sinusoidal signal

. Then, the output of the two-channelinterleaved system is given as follows:

odd

even.(1)

Let

(2)

Without loss of generality, we choose the timing reference sothat . Then, we obtain the following:

(3)

where

Remark:

1) given by (3) has four frequency components;the frequency of the first term in (3) is , that of thesecond term is , the third one is 0 (dc) andthe fourth one is . In other words, the first termcorresponds to signal while the second term is due to gainand timing mismatches and the third term is caused by theaverage offset of ADCand ADC while the fourth termis caused by offset mismatch.

2) Equation (3) that we have newly derived considers thegain, offset and timing mismatches together and hence

Fig. 8. Simulation result of a two-channel time-interleaved ADC system withchannel mismatches which verifies the correctness of our derived equation (3).8192-point FFT was performed withA = 1, G = 1, f =f = 997=8192,gain mismatch of� = 0:03, timing mismatch of�t = 2:0 � 10 , averageoffset ofos = 2:0� 10 , and offset mismatch ofos = 9:0� 10 in(1) and (2).

Fig. 9. Simulation result of SNR of a two-channel interleaved ADC systemwith gain mismatch(�) and timing skew(�t) based on (3).

this is a very general result. However, in previous refer-ences [5], [6], [8]–[11] each channel mismatch effect ininterleaved ADC systems is discussed only individually.

3) From (3) we see that the effects of gain and timing mis-match interact each other while the offset mismatch effectis independent.

4) Numerical simulations show that (1) and (3) match ex-actly; in both cases, the power at dc is47.959 dB, thepower and phase at are 0.017 038 dB, 0.107 82 deg,those at are 23.1736 dB, 64.439 deg andthose at are 54.8945 dB, 0.0 deg with the simula-tion conditions in the caption of Fig. 8, where the simu-lated power spectrum is shown.

5) Fig. 9 shows numerical simulation result for the SNR dueto gain mismatch and timing skew which would be usefulfor designing a two-channel interleaved system. In Fig. 9,the horizontal axis indicates timing skew normalizedby the input frequency , and the vertical axis shows the


Fig. 10. Four-channel time-interleaved ADC system.

SNR of the two-channel interleaved ADC system with aparameter of gain mismatch. For example we can see inFig. 9 that gain matching better than 0.1% is required toobtain SNR better than 54 dB for .Note that the offset mismatch effect is not included inFig. 9, however, it is independent of gain and timing mis-match effects and it can be simply added to them.

Fact 1: The total power of the signal and noise at thewhole system output is given by

Proof: See Appendix III.

B. Four-channel Interleaved ADC

Next, we consider a four-channel interleaved ADC system,and Fig. 10 shows its configuration. Similarly, let the gains ofADC , ADC , ADC , ADC be , , , , respectively,and their offsets be , , , , respectively. Also, letthe sampling timing deviations be , , , respectively.Suppose that the input to the ADC is a sinusoidal signal

. Then, the output of the four-channel interleavedsystem is given as follows:

(4)

where , and let

(5)

where

Without loss of generality, we choose the timing reference sothat

Then, we obtain the following:

(6)

where

and , , , , , , , are definedin Appendix I.

Remark:

1) Similar arguments described in two-channel case arevalid for the four-channel case.

2) Numerical simulation shows that (4) and (6) match ex-actly; in both cases, the power at dc is -66.021[dB], thepower and phase at are 0.041 198 [dB], 0.092 319 9[deg], those at are 27.164 [dB], 73.792[deg], those at are 52.041 [dB], 0.0 [deg], thoseat are 21.945 [dB], 80.336 [deg], those at

are 28.296 [dB], 84.706 [deg] and thoseat are 56.478 [dB], 0.0 [deg] with the simulationconditions in the caption of Fig. 11, where the simulatedpower spectrum is shown.

3) Fig. 12 shows numerical simulation result for the SNRdue to the gain mismatch and timing skew which wouldbe useful for designing a four-channel interleaved system,as similar to Fig. 9 in two-channel case.


Proof: See Appendix III

IV. BANDWIDTH MISMATCH EFFECT

In this section, we will introduce a rather new problem,band-width mismatch, in an interleaved ADC or an interleaved sam-pling system, and then we will derive the explicit formulas forits effects. Many electrical circuits can be approximated by a


Fig. 11. Simulation result of a four-channel time-interleaved ADC systemwith channel mismatches which verifies the correctness of our derived equation(6). 8192-point FFT was performed withA = 1,G = 1, f =f = 499=8192,gain mismatches of (� = 0:03, � = �0:02,� = 0:0 and� = �0:01),timing mismatches of (�t = 5:0 � 10 , �t = �2:0� 10 , �t = 0:0and�t = �3:0 � 10 ), and offset mismatches of (os = 2:0 � 10 ,os = 1:0� 10 , os = �3:0� 10 andos = 1:0� 10 ) in eqs. (4)and (5).

Fig. 12. Simulation result of SNR of a four-channel interleaved ADC systemwith gain mismatch (gain deviation of� = (� + � + � + � )=4) and

timing skew (timing skew deviation of� = (�t + �t + �t + �t )=4)based on equation (6).

first-order system (Fig. 13). A typical example is an open-looptrack/hold circuit in track mode, where the ON-resistance of thesampling switch and the hold capacitor constitute a first-orderRC circuit. Here we assume thatth channel ADC is approxi-mated by a first-order system and its bandwidth is given by,which can be mismatched among channels while there are nomismatches of offset, dc gain and timing discussed in the pre-vious sections. (The reader may argue that the approximationof an ADC to a first-order system might be too inaccurate, how-ever, for a track/hold circuit in track mode this approximationis very reasonable and hence the discussion in this section isapplicable at least to interleaved sampling systems which con-sist of an array of track/hold circuits.) Setting the dc gain of

Fig. 13. Bandwidth mismatch model. (a) Approximation of an ADC to thefirst-order system. (b) Bandwidth mismatch model in two-channel case.

each channel to one, without loss of generality, and then the fre-quency transfer function of th channel is given by

and for the input of , the outputof th channel is given by

where

(7)

(8)

We see that the mismatch of the bandwidthamong channels( ) causes and mismatches. Note thatand are functions of the input frequency as well as thebandwidth , and also note that when , and

. Then, we will call the mismatch of asac gain mis-matchand also the mismatch of asac phase mismatch. Re-mark that the ac gain mismatch is different from the gain mis-match discussed in Sections II and III in that ac gain mismatchdepends on but the gain mismatch discussed before does not.Also, note that the ac phase mismatch due to the bandwidth mis-match is anonlinearfunction of the input frequency whilethe phase mismatch due to the timing skew is itslinear function.

A. Two-Channel Interleaved ADC

We consider a two-channel interleaved ADC system,where the bandwidth of each channel is given byand respectively [Fig. 13(b)]. Then, when an input of

is applied, the output of the interleavedsystem is given by

odd

even(9)

where , , and are defined in (7) and (8). Then we canobtain the following formulas:

(10)


Fig. 14. Simulation result of a two-channel time-interleaved ADC system withbandwidth mismatch which verifies the correctness of our derived equation (10).HereA = 1, f =f = 3200=(8192�), f =f = 3000=(8192�),f =f =997=8192 are used, and 8192-point FFT is performed.

where

Also, SNR due to the bandwith mismatch is given by

SNR dB

Remark:

1) Numerical simulation shows that (9) and (10) matchexactly; in both cases the power and phase atare

2.8844 [dB], 44.127 [deg] and that atis 35.852 [dB], 1.7165 [deg]. with the simulationconditions in the caption of Fig. 14, where the simulatedpower spectrum is shown.

2) Fig. 15 shows numerical simulation result for SNR versusdue to the bandwidth mismatch,

which would be useful for the designer to know how muchbandwidth mismatch is tolerable for a specified SNR.Note that our simulation shows that SNR does not dependon .



Fig. 15. Simulation result of SNR of a two-channel interleaved ADC systemwith bandwidth mismatch based on (10). Here,f = (f + f )=2 (averagecut-off frequency) and� = jf � f j=2 (cut-off frequency deviationbetween two channels).f =f = 997=8192 is used and 8192-point FFT isperformed.

B. Four-channel Interleaved ADC

Next, we consider a four-channel interleaved ADCsystem, where the bandwidth of each channel is given by

, and respectively. Then when the input ofis applied, the output of the

interleaved system is given by

(11)

where

and , , , , , , and are defined in (7) and (8).Then, we can obtain the following formulas:

(12)

where


Fig. 16. Simulation result of a four-channel time-interleaved ADC systemwith bandwidth mismatch which verifies the correctness of our derivedequation. (12). Here,A = 1, f =f = 1575=(8192�), f =f =1600=(8192�), f =f = 1550=(8192�), f =f = 1525=(8192�),f =f = 499=8192 are used, and 8192-point FFT is performed.

Fig. 17. Simulation result of SNR of a four-channel interleaved ADC systemwith bandwidth mismatch based on (12). Here we consider the case thatf < f < f < f andf � f = f � f = f � f . In thegraphf = (f + f + f + f )=4 (average cut-off frequency) and� = (f � f ) + (f � f ) + (f � f ) + (f � f ) )=4(cut-off frequency deviation among four channels). 8192-point FFT isperformed, andf =f = 997=8192 is used.

and and aredefined in Appendix II. The SNR is given by

SNR dB

Remark:

1) Numerical simulation shows that (11) and (12) matchexactly; in both cases, the power and phase atare

3.0260 [dB], 0.004 601 13 [deg], those atare 43.980 [dB], 26.670 [deg], those atare 80.880 [dB], 0.202 41[deg] and those at

are 43.979 [dB], 63.540 [deg] with the simula-tion conditions in the caption of Fig. 16, where the simu-lated power spectrum is shown.

2) Fig. 17 shows numerical simulation result for SNR versus(cut-off frequency deviation among four channels)/(av-erage cut-off frequency) due to the bandwidth mismatch,which would be useful for the designer to know how muchbandwidth mismatch is tolerable for a specified SNR.Note that our simulation shows that SNR does not dependon .



V. CONCLUSION

We have analyzed the channel mismatch effects in the time-interleaved ADC system, and derivedexplicit formulas for themismatch effects whenall of offset, gain and timing mismatchesexist together. We have clarified that the gain and timing mis-match effects interact with each other but the offset mismatcheffect is independent of them. Also, we discussed the band-width mismatch effect (ac mismatch effect). We have shownseveral graphs calculated from these formulas, which are usefulfor the designer to know how much mismatch is tolerable fora specified SNR. Finally, we remark that we are investigatingthe following as on-going projects for the time-interleaved ADCsystem:

• Combined channel mismatch effects for all four of offset,gain, timing and bandwidth.

• Channel linearity mismatch effects.[12]• Algorithms to measure mismatch values and compensate

for them.

APPENDIX I

This appendix gives definitions of , , , ,, , , and used in Section III-B.


where

APPENDIX II

This appendix gives definitions of , , , ,, , and used in Section IV-B.

where

APPENDIX III

This appendix gives brief proofs of Facts 1, 2, 3 and 4.Proof of Fact 1: It follows from (3) that the total output

power is given by

Proof of Fact 2: It follows from (6) that the total outputpower is given by




ACKNOWLEDGMENT

The authors would like to thank T. Komuro, H. Sakayori, A.Minegishi and K. Wilkinson for valuable discussions.

REFERENCES

[1] C. Schiller and P. Byrne, “An 4 GHz 8b ADC system,”IEEE J. Solid-State Circuits, vol. 26, pp. 1781–1789, Dec. 1991.

[2] M. McTigue and P. J. Byrne, “An 8-Gigasample-per-second 8-bit dataacquisition system for a sampling digital oscilloscope,”Hewlett-PackardJ., pp. 11–13, 1993.

[3] K. Poulton, K. L. Knudsen, J. Kerley, J. Kang, J. Tani, E. Cornish, and M.VanGrouw, “An 8-GSa/s 8-bit ADC system,” inTech. Dig. VLSI CircuitsSymp., Kyoto, June 1997, pp. 23–24.

[4] C. S. G. Conroy, D. W. Cline, and P. R. Gray, “An 8b 85MS/s parallelpipeline A/D converter in1 �m CMOS,” IEEE J. Solid-State Circuits,vol. 28, pp. 447–455, April 1993.

[5] K. C. Dyer, D. Fu, S. H. Lewis, and P. J. Hurst, “An analog backgroundcalibration technique for time-interleaved analog-to-digital converters,”IEEE J. Solid-State Circuits, vol. 33, pp. 1912–1919, Dec. 1998.

[6] D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, “A digital backgroundcalibration technique for time-interleaved analog-to-digital converters,”IEEE J. Solid-State Circuits, vol. 33, pp. 1904–1911, Dec. 1998.

[7] W. C. Black Jr. and D. A. Hodges, “Time interleaved converter arrays,”IEEE J. Solid-State Circuits, vol. 15, pp. 1022–1029, Dec. 1980.

[8] H. Kobayashi, M. Morimura, K. Kobayashi, and Y. Onaya, “Aperturejitter effects on wideband sampling systems,” inProc. IEEE Instrumen-tation and Measurement Tech. Conf., Venice, May 1999, pp. 880–885.

[9] Y.-C. Jeng, “Digital spectra of nonuniformly sampled signals: Funda-mentals and high-speed waveform digitizers,”IEEE Trans. Instrum.Meas., vol. 37, pp. 245–251, June 1988.

[10] A. Petraglia and S. K. Mitra, “Analysis of mismatch effects among A/Dconverters in a time-interleaved waveform digitizers,”IEEE Trans. In-strum. Meas., vol. 40, pp. 831–835, Oct. 1991.

[11] A. Montijo and K. Rush, “Accuracy in interleaved ADC system,”Hewlett-Packard J., pp. 38–46, 1993.

[12] N. Kurosawa, H. Kobayashi, and K. Kobayashi, “Channel linerity mis-match effects in time-interleaved ADC systems,” inProc. Int. Symp. Cir-cuits and Systems, Sydney, Australia, to be published.

Naoki Kurosawa received the B.S. degree inelectronic engineering from Gunma University,Kiryu, Japan, in 2000, and is currently pursuing theM.S. degree in electronic engineering in the sameuniversity.

His research interests include analog integratedcircuit design.

Haruo Kobayashi (S’88–M’89) received the B.S.and M.S. degrees in information physics fromUniversity of Tokyo, Japan, in 1980 and 1982, re-spectively, the M.S. degree in electrical engineeringfrom University of California, Los Angeles, in 1989,and the Dr. Eng. degree in electrical engineeringfrom Waseda University, Tokyo, Japan, in 1995.

He joined Yokogawa Electric Corporation, Tokyo,Japan in 1982, where he was engaged in the researchand development related to measuring instrumentsand mini-supercomputers. In 1997, he joined Gunma

University, Kiryu, Japan, and presently is an Associate Professor in theElectronic Engineering Department there. He was also an Adjunct Lecturer atWaseda University from 1994 to 1997. His research interests include analogand digital integrated circuit design and signal processing algorithms.

Dr. Kobayashi is a recipient of the 1994 Best Paper Award from the JapaneseNeural Network Society.

Kaoru Maruyama received the B.S. and M.S. de-grees in electronic engineering from Gunma Univer-sity, Kiryu, Japan, in 1998 and 2000, respectively.

In 2000, he joined Matsushita Systems and Tech-nology Company, Ltd. Kawasaki, Japan. His researchinterests include analog integrated circuit design andsignal processing algorithms.

Hidetake Sugawara received the B.S. degree inelectronic engineering from Gunma UniversityKiryu, Japan, in 1999, and is currently pursuing theM.S. degree in electronic engineering at the sameUniversity.

His research interests include ADC testing andanalog integrated circuit design.

Kensuke Kobayashi received the B.S. degree inelectronic engineering from the University of Tokyo,Japan, in 1971.

In 1971 he joined the IWATSU Electric CompanyLtd., Tokyo, Japan, where he was engaged indesigning wideband sampling oscilloscopes. Since1993, he has been developing fast-sampling-rateand wideband data acquisition systems in TeratecCorporation.

Digital Compensation

for Timing Mismatches

in Interleaved ADCs

R. Yi, Minghui Wu, K. Asami, H. Kobayashi

R. Khatami, A. Katayama, K. Katoh

Gunma University Advantest Corporation Tsuruoka National College of Tech.

IEEE Asian Test Symposium, Yilan, Taiwan (Nov. 2013)

Kobayashi. Lab @ Gunma_University

Contents

• Research Background and Objective

• Time Interleaved ADC System

• Proposed Calibration System

• Simulation Results

• Extension to 4ch Interleaved ADCs

• Conclusion

2


Contents






• Conclusion

3


Research Background & Objective

4

Background

Objective

High-speed sampling time-interleaved ADC for ATE system Timing skew Big issue

Error compensation of timing skew effects

Analog method + Digital method Conventional

Full digital method Proposal

High accuracy, Stable, Reliable

ATE System


Contents






• Conclusion

5


6

Time

Analog input Digital output

・・・

ADC1 S/H1

CLK1

ADC2 S/H2

CLK2

S/HM

CLKM

ADCM

CLKM

CLK1

CLK2

・・・

Timing skew dt

Principle of Time-Interleaved ADC

M times sampling rate with M-channel ADCs

High-speed sampling


2-channel Interleaved ADC

7

CLK1 reference

CLK2 delayed by half period

2 times sampling rate

Analog

input

Digital

output

ADC1 S/H1

CLK1

ADC2 S/H2

CLK2

Time

CLK’

CLK1

CLK2

Timing skew Δt


Timing Error in Sampling

8

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

Δt Δt Timing skew

Output error due to timing skew

Ideal clock

Actual clock

Ideal sampling points

Actual sampling points

Timing error (horizontal error)

Sampled voltage error (vertical error)


Input Frequency & Output

9

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

Δt Δt

Timing skew

Input freq.

Output error

Low freq.

High freq.

As input frequency increases, timing skew problem becomes serious in interleaved ADC.


Contents






• Conclusion

10


Proposed Calibration System

11

● Full digital ● Timing Skew Detection - Cross-correlation of two channel ADC outputs ● Timing Skew Effect Compensation - Delay linear digital filter ● Calibration Control - Successive approximation algorithm - Foreground calibration


Timing Skew Detection

Cross-Correlation

12

Cross-

Correlation Similarity

dtgftgf )()())(( *　

m

mngnfmgf ][][))(( *　

Continuous-time signal

Discrete-time signal

The similarity of two time series signals f, g



Correlation of R(0)and R(1)

13

][nf

][][ tTnfng

CH1 ADC output:

CH2 ADC output:

lag 0,

lag 1,

n

nn

ff tTnfnfn

RR ][][1

lim]0[)0(

n

nn

ff tTnfnfn

TRR ][][1

lim]2[)1(

Timing skew t



Cross-Correlation without Timing Skew

14

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

CLK2

CLK1

a’

b’

Ts/2 Ts/2

-3 -2 -1 0 1 2 3 40

0.2

0.4

0.6

0.8

1

Lag

Sim

ilarit

yR(0)=R(1) Δt=0

R(0) R(1)



Cross-Correlation with Timing Skew

15

-3 -2 -1 0 1 2 3 40

0.2

0.4

0.6

0.8

1

Lag

Sim

ilarit

y

R(0)>R(1) Δt<0

R(0)<R(1) Δt>0

-1 0 1 2 3 4 5 6 7-1.5

-1

-0.5

0

0.5

1

1.5

CLK2

CLK1

a

b Ts/2-Δt Ts/2+Δt

cross-correlation

value

Sign of Δt (Δt >0 or Δt <0)

Magnitude of |Δt|

R(0) R(1)


0.031 0.060.005

0.01

0.015

0.02

0.025

Sim

ilarit

y D

iffe

ren

ce

Frequency(kHz)


Calibration Input Frequency & Correlation Sensitivity

16

Frequency Difference

between R(0) and R(1)

Δt=-0.02Ts

-1 0 1 20.6

0.62

0.64

0.66

0.68

0.7

0.72

0.74

0.76

0.78

0.8

Lag

Sim

ila

rit

y

-1 0 1 20.8

0.82

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

Lag

Sim

ila

rit

y

R(0) R(1)

R(0) R(1)



Calibration Input Signal & Correlation Sensitivity

17

-0.1 -0.05 0 0.05 0.1

-0.1

-0.05

0

0.05

0.1

Timing Skew

Sim

ilarit

y D

iffe

ren

ce

Sin

wave

3 tone signals

● 3-tone is more sensitive than 1-tone.

● For 3-tone, minimize random phase and crest factor


Timing Skew Effect Compensation

Linear Phase Delay Digital Filter

18

Conventional Linear-Phase Digital Filter :

Group delay time resolution Ts/2

Proposed Linear-Phase Delay Digital Filter [1]：

Arbitrary small time resolution τ

Linear phase maintain time-domain waveform

Analog

Input F(t)

F(t−𝝉)

𝛕

[1] K. Asami, et. al., “Timing Skew Compensation Technique using Digital Filter with Novel Linear Phase Condition,” IEEE International Test Conference (Nov. 2010).



Ideal Filter

19

1.0

∠H(jω)

ω π

Ts

−π

Ts

H(jω)

ω

h(t)=1

Ts

sinc πt

Ts

t

Ts

-5 -4 -3 -2 -1 0 1 2 3 4 5

Inverse Fourier Transform

Impulse response Frequency response



Time Shift of Ideal Filter

20

Impulse response

τ

Ts

t

Ts

-5 -4 -3 -2 -1 0 1 2 3 4 5

g(t) = h(t− τ)

=1

Ts

sinc πt− τ

Ts

no change on amplitude property

Frequency response

∠G(jω)

ω π

Ts

−π

Ts

G(jω)

ω

∠G(jω) = −ωτ

Fourier transform

Linear phase is maintained. Impulse response is time-shifted by, τ



Delay Digital Filter Coefficients

21

Ideal delay filter

τ

Ts

t

Ts

-5 -4 -3 -2 -1 0 1 2 3 4 5

h(t) = sinc πk ∙ Ts− τ

Ts

δ

k

t− k ∙ Ts

FIR(Finite Impulse Response)

Filter

IIR(Infinite Impulse Response)

Filter

Time-shift

h(t) = sinc πk ∙ Ts

Ts

δ

k

t− k ∙ Ts

t

Ts

-5 -4 -3 -2 -1 0 1 2 3 4 5



Design of Linear-Phase Delay Digital Filter

22

convolution

window function

t

Ts

FIR filter

t

Ts

Ideal delay filter

t

Ts

Linear phase Digital Delay Filter


Calibration Control

Proposed System

23

4τ

ADC2

ADC1

controller

2τ τ

-4τ -2τ -τ

Correlation calculation

D1

D2

CLK1

CLK2

compare the

correlation value of

the lag 1 and lag 0

R(0)<R(1)

Δt>0

delay CH1 4τ

delay CH2 -4τ

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

compare the


the lag 1 and lag 0

R(0)>R(1)

Δt<0

delay CH1 -2τ

delay CH2 2τ

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

Vin

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

compare the


the lag 1 and lag 0

R(0)<R(1)

Δt>0

delay CH1 τ

delay CH2 -τ

Delay 4τ Digital Filter

R(0) R(1)


24

4τ

ADC2

ADC1

controller

2τ τ

-4τ -2τ -τ

Vin

D1

D2

CLK1

CLK2

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

before calibration

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

after calibration

Correlation Calculation

Calibration Control

Calibration Done

Binary-search, successive approximation

R(0) R(1) R(0) R(1)


Contents






• Conclusion

25


Simulation Results (1)

26

timing skew

filter tap

window function

τ

+ 0.02 Ts

21

Blackman

0.001 Ts

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ilarit

y-1 0 1 2

0.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

Confirm the performance of

timing skew calibration

0 10 20 30 40 50 60 70 80 90 100-5

-4

-3

-2

-1

0

1

2

3

4

5

3-tone Input signal Before timing skew calibration

After step1 calibration After step2 calibration After step3 calibration

R(0) R(1) R(0) R(1) R(0) R(1)

R(0) R(1)


Simulation Results (2)

27

timing skew

filter tap

window function

τ

- 0.01 Ts

21

Blackman

0.001 Ts

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ilarit

y-1 0 1 2

0.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

-1 0 1 20.55

0.6

0.65

0.7

0.75

Lag

Sim

ila

rit

y

Confirm the performance of

timing skew calibration

0 10 20 30 40 50 60 70 80 90 100-5

-4

-3

-2

-1

0

1

2

3

4

5

3-tone Input signal Before skew calibration

After step1 calibration After step2 calibration After step3 calibration

R(0) R(1)

R(0) R(1) R(0) R(1)

R(0) R(1)


Power Spectrum of Interleaved ADC Output

without/with Timing Skew

28

0 Fs/2-100

-80

-60

-40

-20

0

Normalized frequency

Pow

er

[dB

]

0 Fs/2-100

-80

-60

-40

-20

0

Normalized frequencyPow

er

[dB

]

3-tone signal without skew

Signal Spurious Signal

3-tone signal with skew


Power spectrum before/after Calibration

29

After skew calibration Before skew calibration

0 Fs/2-100

-80

-60

-40

-20

0


Pow

er

[dB

]

0 Fs/2-100

-80

-60

-40

-20

0

Normalized frequencyPow

er

[dB

]

Spurious components are reduced by proposed calibration

Signal Spurious Signal Spurious


Contents






• Conclusion

30


4-Channel Case Extension Method

33

-2 -1 0 1 2 30.5

0.6

0.7

0.8

0.9

Lag

Sim

ilarit

y

-1 0 10.9

0.905

0.91

0.915

0.92

0.925

Lag

Sim

ilarit

y

-2 -1 0 1 2 30.5

0.6

0.7

0.8

Lag

Sim

ilarit

y

-1 0 10.9

0.905

0.91

0.915

0.92

0.925

Lag

Sim

ilarit

y

Before

calibration

After

calibration

Ch1/ch3 calibration Ch2 calibration Ch4 calibration

-2 -1 0 1 20.9

0.905

0.91

0.915

0.92

0.925

Lag

Sim

ilarit

y

-2 -1 0 1 20.9

0.905

0.91

0.915

0.92

0.925

LagS

imil

arit

y

R(0) R(1) CH1/2

CH1/4 R(0)

CH3/4 R(1) CH3/2


Simulation Results - Power Spectrum

34

Before calibration After calibration

0 Fs/2-100

-80

-60

-40

-20

0


Pow

er [

dB]

0 Fs/2-100

-80

-60

-40

-20

0


Pow

er [

dB]

Signal Spurious Signal Spurious


Contents






• Conclusion

35


Conclusion

36

Proposal of timing skew calibration in interleaved ADC ● Full digital ● Timing Skew Detection - Cross-correlation of two channel ADC outputs - Effective for high frequency, multi-tone input ● Timing Skew Effect Compensation - Delay linear–phase digital filter ● Calibration Control - Successive approximation algorithm - Foreground calibration ● Verified with MATLAB simulation

in 2-channel, 4-channel cases.


Presented by呉明輝（Minghui Wu）

37


38

Challenge for Analog Circuit Testing in Mixed-Signal SoC

Documents