A NOVEL ARCHITECTURE FOR SUPPLY-REGULATED VOLTAGE-CONTROLLED OSCILLATORS A Thesis Presented in Partial F ulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State Universit y By Anu Chakravarty, B. E. Electrical & Computer Engineering Graduate Program ***** The Ohio State Universit y 2010 Thesis Committee: Professor Mohammed Ismail, Adviser Professor Waleed Khalil
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A NOVEL ARCHITECTURE FOR SUPPLY-REGULATED VOLTAGE-CONTROLLED OSCILLATORS
A Thesis
Presented in Partial Fulfillment of the Requirements for the
Degree Master of Science in the
Graduate School of The Ohio State University
By
Anu Chakravarty, B. E.
Electrical & Computer Engineering Graduate Program
The Maneatis and Wilson and Moon, architectures are further discussed in detail
in chapter 3.
1.3 Thesis Outline
The next chapter deals with general oscillator theory, explaining different oscillator
types and parameters.
The second chapter describes the proposed novel voltage-controlled oscillator ar-
chitecture. The simulation results are also presented in this chapter.
Chapter three discusses the Maneatis architecture, its variations and the Wilson
and Moon architecture in detail.
Chapter four compares the simulation results of the new VCO with those achieved
with existing architectures developed to reduce supply noise rejection.
Finally, Chapter 5 reviews the principal contributions of this thesis and includes
a number of suggestions for future work using the ideas presented herein.
8
CHAPTER 2
OSCILLATOR THEORY
Oscillators have been essential components since Edwin Armstrong discovered
the heterodyne principle, wherein they effect frequency translation by multiplying the
oscillators signal with other input signals. Since then oscillators have been an integral
part of many electronic systems. Their applications range from clock generation to
carrier synthesis, and are one of the most challenging blocks in the design of a PLL.
This theoretical chapter deals with the design of CMOS oscillators, more specifi-
cally voltage-controlled oscillators (VCOs) [7], [8]. It discusses the criteria that must
be fulfilled by a circuit to produce oscillations, introduces the two main types of os-
cillators, the ring oscillator and the LC-oscillator. It further discusses the methods
of varying the oscillators output frequency and finally lists some of the important
performance metrics used to evaluate oscillators.
2.1 Criteria for Oscillation
A simple oscillator produces a periodic output, usually a voltage signal. The
oscillator circuit has no input however it sustains an output indefinitely. This is
possible only if the overall feedback becomes positive in an amplifier. Thus, the
9
behavior of oscillators can be modeled as a feedback system as shown in Figure 2-
1. In the block diagram, block A represents an amplifier and block β represents a
Figure 2.1: Block diagram of a feedback system
feedback network that is connected from the output of the amplifier to its input.
The two conditions that are necessary but not sufficient to make a circuit oscillate
are defined as the ”Barkhausen Criteria”. When using the notations of the model in
Figure 2-1, this criteria can be given as
Aβ = 1 (2.1)
The criteria can be divided into two parts, i.e, the magnitude criterion and the phase
criterion.
2.1.1 Magnitude Criterion
The magnitude criterion for oscillation states that the gain Aβ of the oscillator
loop must be equal to one during standard operation. In practice the loop gain has
to be larger than one for the oscillator to begin to oscillate and for the oscillation am-
plitude to grow. The amplitude will eventually saturate due to device nonlinearities,
reducing the loop gain to one and providing a signal with stable amplitude.
10
2.1.2 Phase Criterion
The phase criterion for oscillation states that the phase shift of the oscillator loop
must be zero or a multiple of 2π. This means that the signals with the same phase
are summed at some point in the oscillator. If the phase shift was an odd multiple of
π, then the signals would have opposite phases and would cancel each other out. In
that case there will be no oscillation.
2.2 Types of Oscillators
2.2.1 Ring Oscillators
Ring Oscillators are a subset of the class of delay based oscillators wherein one
or more delay elements are connected in feedback configuration. A ring oscillator
consists of a number of gain stages in a loop. Figure 2-2 shows the schematic of a
three stage inverter ring oscillator. The oscillation frequency fo of the oscillator can
Figure 2.2: Ring Oscillator
11
be calculated as:
fo =1
3(T1 + T2)(2.2)
where T1 is the delay of the rising edge and T2 is the delay of the falling edge. The
delay varies with change in bias current or supply voltage and hence changes the
frequency of oscillation.
Delay based oscillators have poor phase noise-performance compared to resonator
based oscillators. However, since delay based oscillators do not need an inductor to
operate, they can be implemented using small chip area. Ring oscillators also have
another advantage of high tuning-range. Ring oscillators have a major disadvantage
though, i.e, they are highly susceptive to supply noise, which effects the delay of each
stage and hence the frequency of oscillation.
Thus, in thesis, we discuss a new approach to build the ring oscillator such that it
is completely insensitive to power supply noise. This architecture uses the differential
implementation of delay stages, which help cancel out common-mode noise. Differen-
tial implementations also may use even number of delay cells by simply configuring
one cell such that it does not invert. This flexibility demonstrates another advantage
of differential circuits over single-ended counterparts.
2.2.2 LC-Oscillators
LC-oscillator belongs to the class of resonator based oscillators, which are the most
common topology in radio applications. In resonator based oscillators, the oscillation
frequency is determined by a resonance circuit such as an LC-tank. An amplifier
compensates for the loss in the resonance circuit and keeps a sustained oscillator.
12
Figure 2-3 shows an LC-VCO. Due to the differential architecture and relatively
good phase noise it is one of the most popular oscillator configurations used in fully
differential integrated RF CMOS applications. The LC-VCO contains two major
Figure 2.3: Differential CMOS LC Oscillator
parts, the passive LC tank which determines the frequency of oscillation and the
active devices that compensate the loss in the tank. The LC tank contains an inductor
(L) and capacitor (C). The oscillator will oscillate at a frequency where the reactance
of the inductor cancels the reactance of the capacitor.
The oscillation frequency is given by the equation:
fo =1√LC
(2.3)
In order to vary the frequency of oscillation, the capacitor is often implemented using a
voltage-controlled capacitor (varactor) or an array of digitally controllable capacitors,
13
or a combination of both. The other ways of tuning the frequency are varying the
inductance using MEMS or by changing the bias current.
The LC-VCO is highly insensitive to supply noise fluctuations since the frequency
is a function of discrete components L and C only. However, this thesis intends to
develop delay stage architectures for ring VCOs such that the oscillation frequency is
independent of supply noise fluctuations.
2.3 Voltage-controlled Oscillators
Applications such as clock recovery and clock synthesis, require the oscillators to
be ”tunable”. Tunability means that the output frequency must be a function of
some control input, usually voltage. This voltage could be for example the output of
the loop filter in an analog PLL. In an ideal voltage-controlled oscillator, the output
frequency is a linear function of its control voltage.
ωOUT = ωO +KV COVCONT (2.4)
Where ωOUT represents the intercept corresponding to VCONT = 0 and KV CO denotes
Figure 2.4: Definition of a VCO
14
the ”gain” or ”sensitivity” of the circuit (expresses in rad/s/V). The achievable range,
ω2 − ω1 is called the ”tuning range” as shown in Figure 2-4.
2.4 Oscillator Parameters
Some of the important performance metrics of the voltage-controlled oscillator
are discussed below. These parameters help select the best oscillator for a particular
application.
Oscillation frequency
The oscillation frequency f0 or the fundamental frequency of an oscillator is defined
as the frequency at which the main peak in the oscillator’s output spectrum is located.
Frequency tuning range
The tuning range of an oscillator is defined as the distance between the lowest
and highest output frequencies that the oscillator can produce.
Tuning − range = fmax − fmin (2.5)
Tuning voltage or tuning current range
The tuning voltage(or current) range refers to the range of acceptable voltages (or
currents) that can be applied to the tuning circuitry of an oscillator.
Frequency tuning curve
The frequency tuning curve is a graphic representation of what happens to the
oscillators output frequency as the tuning voltage(or current) is swept through the
acceptable range. It is usually desirable that the tuning curve is monotonic.
15
Phase noise
Phase noise is a measure of the frequency stability of an oscillator. It is defined as
the output signal power at a certain offset fm from the carrier frequency f0 and the
power of the carrier, both within a 1-Hz bandwidth. It is usually given in dBc/Hz.
L(fm) = 10log(P (fm)
P (f0)) (2.6)
Pushing figure
The pushing figure of an oscillator gives the dependence of the output frequency
on the supply volatge. It is usually given in MHz/V.
Pushing − figure =∆f
VSUPmax − VSUPmin
(2.7)
Pulling Figure
The pulling figure indicates how dependent the oscillator’s output frequency is on
the value of load impedance.
Pulling − figure =∆f
RLOADmax −RLOADmin
(2.8)
16
CHAPTER 3
PREVIOUS WORK
3.1 Maneatis Delay Cell
The voltage-controlled oscillator architecture proposed by Maneatis uses a differ-
ential buffer stage with symmetric load elements and self-biased replica feedback, to
have high supply noise immunity, while operating at low supply voltages. In this ar-
chitecture, digital calibration is not employed to achieve supply rejection, unlike the
architecture proposed in this thesis in chapter 3. The concept is that, high supply re-
jection can be achieved with high output impedances. This can be done by cascoding
the load impedances in the delay stages. However, since cascoding is incompatible
with low-voltage circuit design, Maneatis proposes the use of a current source bias
circuit, thus enabling the buffer stages to have high supply rejection without cascod-
ing. Symmetric load elements are also used in the buffer stages to enable supply noise
cancellation.
Differential buffer stage
The buffer stage used, is based on an NMOS source-coupled pair with symmetric
load elements and a dynamically biased NMOS current source as shown in Figure
17
Figure 3.1: Differential buffer stage with MOS symmetric load elements [1], [2], [3]
3-1. The bias voltage of the simple NMOS cell continuously adjusts itself to provide
a supply independent bias current. Since, the output swing is referenced to the top
supply, the current source helps isolate the buffer from the supply and hence, helps
achieve constant buffer delay.
The load elements are composed of symmetric loads i.e, a diode connected PMOS
device in shunt with an equally sized biased PMOS device. These loads are called
symmetric loads because their I-V characteristics is symmetric about the center of the
voltage swing as shown in Figure 3-2. The control voltage, VCTRL biases the PMOS
device and helps generate the bias voltage for the NMOS current source and hence
controls the delay of the buffer stage.
Current source bias circuit
The current source bias circuit as shown in Figure 3-3, helps set the current
through a simple NMOS current source in the buffer delay stage to provide the correct
18
Figure 3.2: Symmetric load I-V characteristics, dashed lines show the effective resis-tance of the loads and highlights the symmetry of the I-V characteristics [1]
symmetric load swing limits and also helps adjust the NMOS current source bias so
that the current is held constant and independent of supply voltage. The current
source bias circuit uses replica of half the buffer stage and a single-stage differential
amplifier. The amplifier adjusts the current output of the NMOS current source so
that the voltage at the output of the replicated load element is equal to the control
voltage. This helps set the correct swing limits for the symmetric load.
3.1.1 Implementation
The maneatis delay cell with symmetric loads and replica-feedback bias generator
was implemented in cadence 130-nm. The VCO circuit was modified by shorting the
differential pair tail nodes of the delay cells. This enables their tail node voltage to be
more or less constant and closer to that generated by the bias generator. Simplified
schematic of the voltage-controlled oscillator is shown in this section Figure 3-4, and
the full schematics can be seen in Appendix-A.
19
Figure 3.3: Self-biased replica-feedback current source bias circuit for the differentialbuffer stage [1]
3.2 Wilson and Moon Calibration Technique - Sub-banding
The self-calibration technique used by Wilson and Moon [4] enables the design
of low-noise frequency synthesizers without compromising on the frequency range
of operation. Since the output frequency of an oscillator covers a wide range of
frequencies for a limited range of input voltage, the gain of the VCO is high. This
leads to hight output jitter and phase noise.
The digital calibration technique is used to make a programmable VCO , which
covers a wide range of frequencies while keeping a low control voltage to output
frequency gain (KV CO). This helps reduce the phase noise and output jitter consid-
erably.
The digital word is generated using a self-calibration algorithm. The process vari-
ations are also compensated for by the self-calibration technique. This sub-banding
20
Figure 3.4: Maneatis VCO
21
technique can also be incorporated in the proposed design to reduce th oscillator gain
KV CO and further improve the noise sensitivity.
3.2.1 VCO Design
The VCO is made up of a voltage-to-current converter (V-I), current multiplier
(IX) and current-controlled oscillator (ICO) as shown in Figure 3-5. The VCOs L-
Figure 3.5: Voltage-controlled oscillator - Wilson and Moon [4]
bit programmability is attained by the current multiplier, which controls the current
flowing into the the ICO. The operating range of the VCO is distributed into 2L
modes. This concept is illustrated in Figure 3-6. One of the operating modes is
chosen using the L-bit control word depending on the desired frequency of operation.
This results in a small output frequency to control voltage transfer function and thus
provides low sensitivity to noise.
22
Figure 3.6: 2L operating modes of VCO [4]
3.2.2 Implementation
The V-I converter, current multiplier and ICO were implemented in cadence 130-
nm, and a five bit control word was used to provide sub-banding. Simplified schemat-
ics of these blocks are shown in this section, and the full schematics can be shown in
Appendix-A. The complete block diagram of the VCO is shown in Figure 3-7. The
building blocks are further discussed in detail in the following subsections.
V-I Converter
The V-I converter consists of a n-channel and a p-channel differential pair as
shown in Figure 3-8. One side of each of the differential pairs is connected VRF which
is equal to half the supply voltage. The other transistor’s gate is connected to VRF or
VLF , based on the output of the comparator. The current from the two pairs depends
23
Figure 3.7: Voltage-controlled oscillator - Wilson and Moon
24
on the voltages VRF or VLF , and finally the summation of the two currents is applied
to the current multiplier.
Figure 3.8: Voltage-current converter
Current Multiplier
The current multiplier is implemented with binary weighted transistors, as shown
in Figure 3-9. The control word used is five bits. The maximum current output of
the multiplier is 31 times the input current.
ICO
The ICO is implemented using three delay stages in cascade. The first stage also
consists of a half-replica buffer to generate the control voltage VCTRL, applied to the
25
Figure 3.9: Current multiplier
gates of the PMOS loads of the following delay stages. The circuit diagram for the
delay stages are shown in Figure 3-10 and Figure 3-11.
3.2.3 Simulation Results
A five bit control word was used to generate 32 operating modes. The multiplied
current for each of these modes was generated using the current multiplier and the
resulting frequency of operation was measured with varying control voltage VCTRL.
VCTRL was varied from 0 to 1.2 volts and the resulting oscillator gain was calculated
for each operating mode. Without sub-banding the KV CO of the VCO would have
been (5.618 GHz - 2.9586 GHz )/1.2 Volts , i.e, 2.216 GHz/V. However, by using the
sub-banding technique the KV CO has been reduced to a few hundred megahertz. This
reduction in the oscillation gain helps reduce the output jitter and reduces the phase
noise of the VCO. The results with sub-banding are shown in the following excel sheet
Figure 3-12. The effect of supply noise on frequency was also reduced considerably,
26
Figure 3.10: ICO - delay stage 1
Figure 3.11: ICO - delay stage 2
27
L
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4.0
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52
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2.6
62
4
Figure 3.12: Reduction in KV CO due to sub-banding
28
as shown below in Table 3.1. However, even better supply rejection is acheived using
the proposed architecture as discussed in Chapter 4.
[1] J. G. Maneatis and M. A. Horowitz, “Precise Delay Generation Using CoupledOscillators,” IEEE Journal of Solid-State Circuits, Vol. 28 , No. 12, December1993.
[2] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multilpier Clock Generator PLL,”IEEE Journal of Solid-State Circuits, Vol. 38 , No. 11, November 2003.
[3] J. Carnes, I. Vytyaz, P. K. Hanumolu, K. Mayaram, and U.-K. Moon, “Designand Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells,”IEEE International Conference on Electronics, Circuits and Systems, 2007.
[4] W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOSSelf-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-state Circuits,Vol.35, No.10, October 2000.
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