Ch2 the Well

8/14/2019 Ch2 the Well

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Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition

By R. Jacob Baker, Copyright Wiley-IEEE

ChipFlip chip

on its sideand enlarge

p-type substrate (p+)

p-type epi layer (p-)

n-well

Usually, wewill not show

the epitaxiallayer. Many

processes don't usethe epi layer.

MOSFETs are not shown.

The top (layout) and side (cross-sectional) view of a die.Figure 2.1

n-well

p-substrate

n-well

p-substrate

Resistor leads

Shows parasiticdiode

Substrateconnection

The n-well can be used as a resistor.Figure 2.2




(a) Unprocessed wafer

For cross section,

cut along dottedline

(c) Grow oxide (glass or SiO ) on wafer.2

p-type

Oxide

p-type

OxideresistPhoto-

A B

(d) Deposit photoresist

(e) Mask made resulting from layout.

Top view

Side view

A B

p-type

OxideresistPhoto-

Mask

(f) Placement of the mask over the wafer.

Mask (reticle)

p-type

OxideresistPhoto-

(g) Exposing photoresist.

p-type

OxideresistPhoto-

(h) Developing exposed photoresist.

(i) Etching oxide to expose wafer.

p-type

Oxide

resistPhoto-

(j) Removal of photoresist.

p-type

Oxide

p-type

(b) Cross-sectional view of (a)

A B

Generic sequence of events used in photo patterning.Figure 2.3

A BA B

A B

Ultraviolet light





p-substrate

Top of the wafer after oxidation

Top of the wafer before oxidation

How growing oxide consumes silicon.Figure 2.4

oxSi

SiO2

Diffusion of donor atoms

(a) Diffusion of donor atoms

p-type

Resist

Start of diffusion into the wafer

(c) After resist removal

p-type

n-well

(d) Angled view of n-well

(b) After diffusion

p-type

Resist

n-well

p-type

Formation of the n-well.Figure 2.5





n-well

10

p-substrate

Cross section

shown below

Layout and cross-sectional view of a 10 by 10 (drawn) n-well.Figure 2.6

10

n-well

p-substrate

Cross section

shown below

n-well

Spacing

Width Width

Parasitic npn bipolar transistor

Figure 2.7 Sample design rules for the n-well.

Design rules: width of the n-well must be at

least 6 while spacing

should be at least 9.





t

W L

A

B

L W A B

Layout view

Calculation of the resistance of a rectangular block of material.Figure 2.8

1

2 3

Layout (top view)

A

B

(a) (b)

A

B

(a) Calculating the resistance of a corner section and (b) layout to avoid corners.Figure 2.9

FOX FOX FOX

n-well

p-substrate

Metal Metal

p+ field implant

n+ field implant

Cross-sectional view of n-well showing field implant. The fieldFigure 2.10

n+ n+

implantation is sometimes called the "channel stop implant."

n+ active implant





Figure 2.11 An electron moving to the conduction band, leaving

behind a hole in the valence band.

electron

hole E v

E c

E g

(a) Intrinsic silicon (b) p-type silicon (c) n-type silicon

p-type n-type

Figure 2.12 The Fermi energy levels in various structures.

(d) A pn-junction diode

E v

E c E fn

E v E v

E c E c

E i

E fp

E c

E v

E v

E f

E c

q ⋅ V bi

E i E i





Cathode, K Anode, A

Depletion region formation in a pn junction.Figure 2.13

+

+

+

+

+

+

+

p-type n-type

Depletion

region

Two plates of a capacitor

V D

p-substrate

n-well

Bottom capacitance Sidewall capacitance

A pn junction on the bottom and sides of the junction.Figure 2.14

V d

1.12 pF

Diode depletion capacitance against diode reverse voltage.Figure 2.15

0

C j, diode depletion capacitance

V D, diode voltage

C j0, zero-bias depletion capacitance





p-type n-type

Minority carriers

Metal contact Storage or diffusion capacitance

Charge distribution in a forward-biased diode.Figure 2.16

R

time

I

I0.7

Diode current

Diode voltage

Diode reverse recovery test circuit.Figure 2.17

t 1 t 2

V F

V R

V F − 0.7

R

V R − 0.7

RV R

t 3

+10

10

1k

Figure 2.18 Circuit used in Ex. 2.4 to demonstrate simulation of adiode's reverse recovery time.

V D I D

V IN



Table 2.1 SPICE parameters related to diode.

Name SPICE

I S IS Saturation current

RS RS Series resistance

n N Emission coefficient

V bd BV Breakdown voltage

I bd IBV Current which flows during V bd

C j0 CJ0 Zero-bias pn junction capacitance

V bi VJ Built-in potential

m M Grading coefficient

τT TT Carrier transit time







Figure 2.19 The simulation results for Ex. 2.4.

RC time is

V D

V IN

I D (mA)

t s

≈ 1k ⋅ 1 p = 1 ns

I D (mA)

n-well

p-type

Pulse in Pulse out

Substrate tied to the lowest potential in the circuit, in this case ground

R determined by the sheet resistanceof the n-well

C determined by the

depletion capacitanceof the n-well

Substrate connection

Input Output

R

C

(a)

(b)

(a) Parasitic resistance and capacitance of the n-well and (b) schematic symbol.Figure 2.20





R

C input pulse

in out

time0

Input pulse

Delay time

Rise time

0

Figure 2.21 Rise and delay times in an RC circuit.

Output pulse

t d = 0.7 RC t r = 2.2 RC

0.9V pulse0.5V pulse

0.1V pulse

V pulse

0 to V pulse

in out

Figure 2.22 Calculating the delay through a distributed RC delay.

A B C R square R square R square R square

C square C square C square C square

Figure 2.23 SPICE simulations showing the delay through an n-well

resistor.

in

out

time22 ns

*** Figure 2.23 CMOS: Circuit Design,Layout, and Simulation ***.controldestroy allrunplot vin vout.endc.tran 100p 100n

O1 Vin 0 Vout 0 TRCRload Vout 0 1GVin vin 0 DC 0 pulse 0 1 5n 0.model TRC ltra R=5k C=5f len=50.end





Figure 2.24 The different possible wells used in a bulk CMOS process.

n-well

p-substrate

(a) n-well process

p-well

n-substrate

(b) p-well process

n-well

p- or n-substrate (lightly doped)

(c) Twin-well process p-well

n-well2

p-substrate (lightly doped)

(d) Triple-well process p-well

n-well1 using p-substrate





Figure 2.25 Layouts showing the MOSIS design rules for the n-well.

n-well n-well n-well

p-well

1.31.2

1.41.1

Figure 2.26 SEM image showing the cross-section of a CMOS memory chip.

deep n-well

p-substrate

p-well





Cross-section

Cross-section

Figure 2.27 Layout used in problem 2.1.

Figure 2.28 Layout of an n-well resistor using a serpentine pattern.





10 k 1 V

1 mV

n-well

Substrate

Figure 2.29 Treating the diode as a capacitor. See Problem 2.7.

vout

vin

Ch2 the Well

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