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C H A P T E R 14

CMOS Digital Logic Circuits

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I n t r o d u c t i o n

CMOS is by far the most popular technology for the implementationof digital systems.The small size, ease of fabrication, and low power

consumption of MOSFET enable extremely high levels of integration ofboth logic and memory circuit.

Digital electronics normally based on logic circuits. These circuitscomposed oflogic gates depend on pulses of electricity to make thecircuit work.

A logic gate performs a logical operation on one or more logic inputsand produces a single logic output. The logic normally performed isBoolean logic and is mostcommonly found in digital circuits.

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Figure 14.1 A logic inverter operating from a dc supply VDD.

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Figure 14.3 Voltage transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the fourparameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

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N o i se M a r g i n s ( 1)

The noise margin is an indicator of the ability to reject noise for alogic-circuit family and it is defined as

Typical voltage transfer characteristic(VTC) of a logic inverter

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Figure 14.6The VTC of an ideal inverter.

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Figure 14.7

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Figure 14.8 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of theCMOS inverter that we shall study in Section 14.2.

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Figure 14.9

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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.

Figure 14.10The resistively loaded MOS inverter and its VTC (Example 14.1).

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Figure 14.11 (a) Enhancement-load MOS inverter; (b) load curve; (c) construction to determine VTC; (d) the VTC.

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14.1.6 Power Dissipation

Edissipation=CVDD2-1/2CVDD

2

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Pow er D i ssi p a t i o n

For power dissipation

The need to minimize the power dissipation is motivated by the

desire to pack an ever-increasing number of gates on a chip. It should be kept as low as possible, particularly for portable,battery-operated equipment.

2 types of power dissipation in a logic gate.

Static power dissipation: it refers to dissipation in the absence of

switching action. Dynamic power dissipation occurs only when the gate is

switched. For an inverter operated from a power supply VDD, anddriving a load capacitance C, the dynamic power dissipation is

The advanced chip operated at VDD ~1V with 100 milliontransistors packed produces more than 100 W dynamic powerdissipation when the operation frequency is above 1 GHz.

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Figure 14.13 An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are definedas indicated.

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Pr o p a g a t i o n D el a y

The dynamic performance of a logic-circuit family is characterizedby the propagation delayof its basic inverter.

Figure 14.15 Definitions of propagation delays and transition times of the logic inverter.

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Del a y -Pow er Pr o d u ct

High speed performance combined with low power dissipation isalways desirable. However, the 2 requirements are often in conflict.

Delay-Power product (DP) is a figure-of-merit for comparing logiccircuit families and itdefines as

The unit of DP isjoules!The lower DP figure of a logic family, the

more effective it is.

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Si l i co n A r ea a n d F a n - I n / Fa n -Ou t

For Si area consideration, smaller area requirement enables thefabrication of a large number of gates per chip. There are 3 ways to

reduce the area:Through advances in processing technology.

Through circuit-design techniques.

Through careful chip layout.

For fan-in of a gate, it is the number of its inputs.

For fan-out, it is the maximum number of similar gates that a gatecan drive while maintaining guaranteed specifications. Increasing thefan-out of the inverter will reduce VOH and hence NMH (example 5.10).

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D i g i t a l I C Tech n o l o g i es an dL o g i c-Ci r cu i t F am i l y

Members of each family are made with the same technology, have a

similar circuitstructure, and exhibit the same basic features.

Technologies

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CM OS Tech n o l og y (1)

CMOS has replaced NMOS, a dominant device employed in theearly days of VLSI, because of the much lower power dissipation.

CMOS has also replaced bipolar (BJ T) in digital systemdue to

CMOS logic circuits dissipate much less power than bipolar ones

and thus more circuits can be packed on a chip.

The high impedance of the MOS transistors allows the designer to

use charge storage as a means for temporary storage of information.

The feature size of the MOS transistors has decreased dramatically

and permits very tight circuitpacking.

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B i p o l a r T ech n o l o g y

2 logic-circuit families based on BJ T areTTL and ECL.

The new version of TTL (transistor-transistor logic) operates BJ T in

non-saturating mode and therefore enjoys a higher speed theconventional one. However, the application of TTL declines with theadventof VLSI era.

ECL (emitter-coupled logic) is the fastest logic among commerciallyavailable logic-circuit families. ECL is also used in VLSI circuit design ifhigh speed is required and the designer is willing to accepthigh powerdissipation and increased Si area.

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Figure 14.17The CMOS inverter.

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Figure 14.18

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Ci r cu i t St r u ct u r e o f A CM OS I n v er t er

The inverter can be represented by a pair of switches operated incomplementary fashion.

Each switch is modeled by a finite on resistance, which is thesource-drain resistance of the respective transistor.

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Figure 14.19

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Figure 6.29. Ip andIn as a function ofVout. The intercepts ofIp andIn(circled) represent the steady-state operation points of the CMOSinverter.11The curves are labeled by the input voltages: 0 =Vin0

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Figure 6.30.

Transfer curve of aCMOS inverter.11

Points labeled A, B, C,and D correspond to

those points labeled inFig. 29.

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M a t ch i n g o f D ev i ces

The termmatchingindicates the following conditions for QN and QP

Matching of QN and QP provides equal transconductance

equal current-driving capability inboth pull-up and pull down directions

equal propagation delays for tPLH and tPHL.

symmetrical transfer characteristic

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Figure 14.20The voltage-transfer characteristic of the CMOS inverter whenQN andQP are matched.

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St a t i c Oper a t i o n o f A CM OS I n v er t et r

The symmetry of VTC results inequal noise margins.

(14.58),

r=(Kp/Kn)0.5 (14.59)

The voltage transfer characteristic of the CMOS inverter formatched QN and QP is shown below.

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Figure 14.21

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Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalentcircuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges throughQN.

Vo: Vdd -> 0.5 Vdd

Sat -> triode

A calculation in

complex and details

can obtain

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Dy n am i c Op er a t i o n o f A CM OS I n v er t er

A simple approximate but exact method for analyzing the dynamicoperationof a CMOS inverter.

(14.64)

Vtn~ 0.2 VDD

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Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

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Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 andQ2, which is driving a similar inverterformed byQ3 andQ4.

What contributes to the capacitor between the output node and

ground?

Internal capacitance from QN and QP.

Interconnect wire between inverter outputnode and the input of next stage.

Input capacitance of load gates.

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Figure 14.25The Miller multiplication of the feedback capacitanceCgd1.

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Figure 14.26The current in the CMOS inverter versus the input voltage.

Ipeak is at Vi= 0.5 Vdd, while both Qn and Qp are in Sat

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Figure 14.27 Representation of a three-input CMOS logic gate. The PUNcomprises PMOS transistors, and the PDN comprises NMOS transistors.

Ba i sc St r u ct u r e o f CM OS

L og i c -Ga t e Sr u ct u r e

A CMOS logic circuit is in effect an extension of the CMOS inverter.The CMOS logic gate consists of 2 networks: pull-down network (PDN)and pull-up network (PUN).

The PDN will conduct for all inputcombinations that require a low outputand then pull the output down to ground

Synthesizing PDN can be done by

ExpressingY

The input combinations that call for ahigh output will cause the PUN toconductand pull the outputup to VDD.

Synthesizing PUN can be done byexpressing Y.

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Figure 14.28 Examples of pull-down networks.

Ex am p l es o f Pu l l -D ow n N et w o r k s

usual and alternative circuitsymbols

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Figure 14.29 Examples of pull-up networks.

Exam p l es o f Pu l l -U p Netw o r k s

usual and alternative circuitsymbols

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T h e Tw o -I n p u t N OR Ga t e

How to realize the two-inputNOR function Y=A+B ?

Y=A+B =A B Y=A+B

Figure 14.31 A two-input CMOS NOR gate.

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Figure 14.32 A two-input CMOS NAND gate.

A Com p l ex Ga t e

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Figure 14.33 CMOS realization of a complex gate.

A Com p l ex Ga t e

Note that PDN and PUN are dual

networks: where a series branchexists in one, a parallel branch existsin the other.

Duality can be always be used forPUN or PDN, however, the 2

networks are NOT necessarily duals.

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Th e Excl u si v e-OR Fu n ct i on (1)

Exclusive-OR gates output a "high" (1) logic level if the inputs are atdifferent logic levels, either 0 and 1 or 1 and 0. Conversely, they outputa "low" (0) logic level if the inputs are at the same logic levels.

The Exclusive-OR (sometimes called XOR) gate has both a symboland a truth table pattern that is unique:

Source: Lessons in Electric Circuits-Volume 4- Digital

Th e Excl u si v e OR Fun ct i o n ( 2 )

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Th e Excl u si v e-OR Fun ct i o n ( 2 )

How to realize the gate with more complex function Y=A B +A B ?

If Y is not a function of the

complemented variablesonly, additional invertersare required.

The type of exclusive-ORrequires 12 transistors for

realization.

Figure 14.34 Realization of the exclusive-OR (XOR) function: (a)The PUN synthesized directly from the expression in Eq. (14.86).(b)The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (14.87).Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the

PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 14.33).

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Sum m a r y o f t h e Sy n t h esi zed M et h o d

The PDN can be most directly synthesized by expressingY as afunction of the un-complemented variables. If complementedvariables appear, additional inverterwill be required.

The PUN can be most directly synthesized by expressingY as afunction of the complemented variables. If un-complementedvariables appear, additional inverterwill be required.

The PDN can be obtained from PUN (and vice versa) using duality

property.

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D eM o r g an s Ther o r em

A mathematician named DeMorgan developed a pair of importantrules regarding group complementation in Boolean algebra.

Example


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Som e Boo l ean Ru l es f o r Sim p l i f i ca t i o n ( 1)


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Som e Boo l ea n Ru l es f o r Sim p l i f i ca t i o n ( 2 )


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T r an si st o r Si z i n g ( 1)

The W/L ratios for all devices are usually selected to provide thegate with current-driving capability equal to thatof a basic inverter.

The PDN (PUN) should be able to provide a capacitor discharging(charging) current at leastequal to that of an NMOS (PMOS) transistorwith W/L=n (W/L=p). This will guarantee a worst-case gate delay equalto that of the basic inverter.

For a basic inverter design, n is usually 1.5~2 and, for a matched

design, p =(n / p) n.

The derivation of equivalentW/L ratio is based on the on resistance.

For transistors connected in series,

For transistors connected in parallel,

T r a n si st o r Si zi n g ( 2 )

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a s st o S g ( )

Proper sizing of a 4-input NOR and NAND gate. The NOR gate willrequire much larger area than the NAND gate. This is why NANDgates are preferred for implementing combinational logic functions inCMOS.

Figure 14.35 Proper transistor sizing for a four-input NOR gate. Notethat n and p denote the W/L ratios ofQN andQP, respectively, of the

basic inverter.Figure 14.36 Proper transistor sizing for a four-input NAND gate. Note that nand p denote the W/L ratios ofQN andQP , respectively, of the basic inverter.

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T r a n si st o r Si zi n g ( 3 )

How to provide the proper transistor W/L for the following case?

n2n

2n2n

3p

3p

3p1.5p

Figure 14.37 Circuit for Example 14.7.

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E f f ect o f Fan -I n a n d Fan -Ou t o n

Pr o p a g a t i o n D el a y

Each additional input to a CMOS gate requires two additionaltransistors, one NMOS and one PMOS. The additional transistorsresult in

Chip area increase

Total effective capacitance

per gate increase

Propagationdelay increases

(also for increased fan-out)

Thus tp will increase with fan-in, a fact that imposes a practical limit onthe fan-in of the NAND gate is about 4. Boolean function with gates ofno more than 4 input is preferred.

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Figure 14.38The MOSFET channel length has been reduced by a factor of 2every about 5 years. This phenomenon, known as Moores law is continuing.

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Figure 14.39

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Figure 14.40

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Figure 14.41

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Figure 14.42

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Figure 14.43

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Figure 14.44The power-supply line in a deep submicron IC has non-zero resistance. The IR dropsalong the VDD line cause the voltages delivered to various circuits to differ.

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Figure 14.45The interconnect (wire) between two circuit blocks, A and B, on

an IC chip has finite resistance and a capacitance to ground.

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Table 14.3 Summary of Important Characteristics of the CMOS Logic Inverter

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Table 14.3 (Continued)

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Figure 10.38 Capture schematic of the CMOS inverter in Example 10.5.

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Figure 10.39 Inputoutput voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with mp/mn = 1 andmp/mn = 4.

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Figure 10.40 (a) Output voltage, and(b) supply current versus input voltage for the CMOS inverter in Example 10.5 with mp/mn = 1 andmp/mn = 4.

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Figure 10.41 Transient response of the CMOS inverter in Example 10.5 with mp/mn = 1 andmp/mn = 4.

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