Centro de Informática – UFPE Pernambuco, Brazil Heracles Project
Jan 05, 2016
Centro de Informática – UFPEPernambuco, Brazil
Heracles Project
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Motivation
• Medical Analysis– Defects in the retina, EEG, ECG,
EMG, EOG, ...
• Digital processing of signals
• Astronomy
• Vibration Analysis of musical instruments
• Geology– Measure and analyze seismic waves
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The Problem
• Signal and spectrum analyzer
Comunication
ProcessingCapture of the
signal Exhibition of the results
Comunication
Signal
Measure, visualize and analyze signals .
Examine the spectral composition of the waveforms
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The Solution
Signal
Data [7..0]
Data Capture
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Analogical signal Digital signal
Data Capture
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A/D Converter restrictions
• The A/D converter ADC0804– Convert signals with
amplitude between 0 and 5 volts.
• Addition of a displacement: used to dislocate the signal to the voltage positive axis
– Frequency of conversion • 9kHz.
• Low-pass filter– Cutoff frequency: 3kHz.
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• Allows deal with low amplitude signals
– Amplification of 6 times
– Assist the conversion of the signals• Low amplitude signals make difficult the conversion by the
A/D converter.
Amplifier
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Routing
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The Solution
Signal
Data [7..0]
Data Capture
Trigger Run/StopLevel[7..0] FFTButtonTrigger Mode[1..0] Sec/Div[2..0] Horizontal Volt/Div[2..0]Position[7..0] Reset
Data [7..0]
Control
Data [7..0]
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The Control
• Code in SystemC• 541 code lines
• Functionalities of a signal and spectrum analyzer• Time base and vertical sensibility adjust• Trigger mode (normal, single e automatic)• Trigger level • Trigger slope • FFT
• Use of the Cynthesizer to behavioral synthesis• SystemC• Little time to develop• Some tips to write the code to have a better area and latency• Directives to optimize area and latency without changing the
source code
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The Cynthesizer
• One tool to behavioral synthesis• Behavioral SystemC Synthesizable Verilog RTL
• Related to applications guided to algorithms that do not have predominance of conditional entries and exits
• Modules in which entries data ate processed by some known algorithm (ex.: FFT)
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Decreasing the errors
Increase the productivity
Provide the exploration of
many architectures
The Cynthesizer(1/2)
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The Cynthesizer (2/2)
Same testbench to all level of abstraction
Behavioral, SystemC RTL and Verilog RTL
SystemC/C++
System
SC_MAIN
TB Control
Area and latency optimizations without changes in the source
code
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The Optimizations
• Two ways to specified the optimizations:
– Directives• Affect some specific part of the code
– Command lines• Specified globally just to affect the whole project• Specified to a specific configuration of behavioral synthesis
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Architecture Exploration
CYN_DEFAULT_INPUT_DELAY
CYN_FLATTEN
CYN_PROTOCOL
--sched_asap--unroll_loops
--sched_aggressive_2--unroll_loops--dpopt_auto
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The Control
Latency
AreaRTL RTL with
optimizations
2467605.4 2467605.4
Behavioral
RTL RTL with optimizations
3240.00 ns 9100.00 ns
3910.00 ns
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The Solution
Signal
Data [7..0]
Data Capture
Trigger Run/StopLevel[7..0] FFTButtonTrigger Mode[1..0] Sec/Div[2..0] Horizontal Volt/Div[2..0]Position[7..0] Reset
Data [7..0]
Control
Data [7..0]
DisplayReady Data[7..0] SentData
Protocol
Data [7..0]
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Handshake Protocol
Display_ready
Data
Sent_data
Interface ready to receive data
Data sent by the FPGA
Byte sent by the FPGA
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The Solution
Signal
Data [7..0]
Data Capture
Trigger Run/StopLevel[7..0] FFTButtonTrigger Mode[1..0] Sec/Div[2..0] Horizontal Volt/Div[2..0]Position[7..0] Reset
Data [7..0]
Control
Data [7..0]
DisplayReady Data[7..0] SentData
Protocol
Data [7..0]
DisplayReady Data[7..0] SentData
DisplayReady Data[7..0] SentData
Parallel Protection
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Device Protection
• Restrict the value of the current – Protects the device from short circuit or peak currente– Buffer 74HC244N which only receives one signal (0 to 5
volts) and sent one value that the parallel support.
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The Solution
Signal
Data [7..0]
Data Capture
Trigger Run/StopLevel[7..0] FFTButtonTrigger Mode[1..0] Sec/Div[2..0] Horizontal Volt/Div[2..0]Position[7..0] Reset
Data [7..0]
Control
Data [7..0]
DisplayReady Data[7..0] SentData
Protocol
Data [7..0]
DisplayReady Data[7..0] SentData
DisplayReady Data[7..0] SentData
Parallel Protection
DisplayReady Data[7..0] SentData
GUI
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Interface
• Code in C++– 468 code lines
• EPP (Enhanced Parallel Port), the type of parallel port mode
• Protocol with the FPGA using the parallel port– Easy extension to an others ways of visualization– Possibility to write in an archive
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Interface
• Automatic mode
Volts/div
ModeInitiate
the capture
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Conclusion
• Documentation following the ipProcess
• Behavioral synthesis makes the work easier!– Optimization without change the source code
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Future Works
• Change to a better A/D Converter
• Other functionalities– Holdoff– Two channels
• Design an ASIC AMS