CE122- weeks01

8/14/2019 CE122- weeks01

1/31

Operating System CE122

Computer System OverviewWeeks 01

[email protected]

8/14/2019 CE122- weeks01

2/31

Peraturan

Kehadiran 80%

Maksimal keterlambatan 30 Menit

Quiz dilaksanakan sewaktu-waktu

2

8/14/2019 CE122- weeks01

3/31

Penilaian

UTS (10-40%)

UAS (20-40%)

Quiz (5-10%)Tugas (10-40%)

Pre -Test (0-10%)

Post-Test (0-10%)

3

8/14/2019 CE122- weeks01

4/31

Referensi

4

[Stallings2001] William Stallings. Hak Cipta

2001. Operating Systems.

Prentice Hall.

[Tanenbaum1992] Andrew S. Tanenbaum. Hak

Cipta 1992.

Modern Operating Systems. Prentice-Hall Inc..

[Silberschatz2000] Avi Silberschatz, Peter Galvin,

dan Grag Gagne. Hak Cipta 2000.

Operating Systems CONCEPTS

8/14/2019 CE122- weeks01

5/31

Visi Politeknik Telkom

Menjadi politeknik

unggulan di asiatenggara

5

8/14/2019 CE122- weeks01

6/31

Operating System Definition:

System: A group of interacting, interrelated, or

interdependent elements or parts that functiontogether as a whole to accomplish a goal.

Operating System program that manages a computers resources,

especially the allocation of those resources amongother programs. Typical resources include the central

processing unit (CPU), computer memory, filestorage, input/output (I/O) devices, and networkconnections. Management tasks include schedulingresource use to avoid conflicts and interferencebetween programs. Unlike most programs, whichcomplete a task and terminate, an operating systemruns indefinitely and terminates only when thecomputer is turned off. 6

8/14/2019 CE122- weeks01

7/31

Computer

Basic elements :

Processor : Managing computeroperation and data processing

function

Main Memory : Retain digital data usedfor data computing for some interval

time. I/O Module : Interaction devices between

user and system.

Component interconnection : structure 7

8/14/2019 CE122- weeks01

8/31

Computer - Processor

Components:

CU (Control unit) : Controlling operation.

ALU (Arithmetic logic unit) : Controllingarithmetic and logic operation.

Register : Highspeed memory used forsaving the operands from operation.

8

8/14/2019 CE122- weeks01

9/31

Top-Level Components

8/14/2019 CE122- weeks01

10/31

Processor Registers

User-visible registers

Enable programmer to minimize main-memory references by optimizing

register use

Control and status registers

Used by processor to control operating

of the processor Used by operating-system routines to

control the execution of programs

8/14/2019 CE122- weeks01

11/31

User-Visible Registers

May be referenced by machinelanguage

Available to all programs -

application programs and systemprograms

Types of registers

Data Address

Index

Segment pointer

Stack pointer

8/14/2019 CE122- weeks01

12/31

User-Visible Registers

Address Registers

Index

involves adding an index to a base value to

get an address

Segment pointer

when memory is divided into segments,memory is referenced by a segment and anoffset

Stack pointer

points to top of stack

8/14/2019 CE122- weeks01

13/31

Control and Status Registers

Program Counter (PC)

Contains the address of an instruction to befetched

Instruction Register (IR) Contains the instruction most recently fetched

Program Status Word (PSW)

condition codes

Interrupt enable/disable

Supervisor/user mode

8/14/2019 CE122- weeks01

14/31

Control and Status Registers

Condition Codes or Flags Bits set by the processor hardware as a

result of operations

Can be accessed by a program but notaltered

Examples positive result

negative result zero

Overflow

8/14/2019 CE122- weeks01

15/31

Computer - Main Memory

Register

Cache Memory

Main MemoryDisk Cache

Magnetic Disk

Magnetic Tape

15

Smaller,Faster,MoreFrequently,More Expensive

8/14/2019 CE122- weeks01

16/31

Going Down the Hierarchy

Decreasing cost per bit

Increasing capacity

Increasing access time Decreasing frequency of access of

the memory by the processor

locality of reference

8/14/2019 CE122- weeks01

17/31

Computer - Main Memory

17

Two Implemented concept.

Cache memory :

High speed.

Limited capacity.

Expensive.

Located between main memory andprocessing register.

Buffering :

Retain data that transferred from or tosecondary storage.

8/14/2019 CE122- weeks01

18/31

Cache Design

Write policy

When the memory write operation takesplace

Can occur every time block is updated

Can occur only when block is replaced

Minimizes memory operations

Leaves memory in an obsolete state

8/14/2019 CE122- weeks01

19/31

Disk Cache

A portion of main memory used as abuffer to temporarily to hold data forthe disk

Disk writes are clustered

Some data written out may bereferenced again. The data areretrieved rapidly from the softwarecache instead of slowly from disk

8/14/2019 CE122- weeks01

20/31

Cache Memory

Invisible to operating system

Increase the speed of memory

Processor speed is faster thanmemory speed

8/14/2019 CE122- weeks01

21/31

Cache Memory

8/14/2019 CE122- weeks01

22/31

Cache Memory

Contains a portion of main memory

Processor first checks cache

If not found in cache, the block ofmemory containing the neededinformation is moved to the cache

8/14/2019 CE122- weeks01

23/31

Cache/Main Memory System

8/14/2019 CE122- weeks01

24/31

Cache Design

Cache size small caches have a significant

impact on performance

Block size the unit of data exchanged between

cache and main memory hit means the information was found

in the cache larger block size more hits until

probability of using newly fetcheddata becomes less than theprobability of reusing data that has

been moved out of cache

8/14/2019 CE122- weeks01

25/31

Computer - I/O Module (1)

Classification based on data stream.

Block Oriented Device

Information saved as fixed sized block.

Write using Direct access method.

Example : disk, optical disk, tape, etc.

Character Stream Oriented Device

Information saved using character stream. Example : terminal, printer line, network

interface.

25

8/14/2019 CE122- weeks01

26/31

Computer - I/O Module (2)

Three techniques I/O devicesconnection:

Programmed I/O

Interrupt Driven I/O

Direct Memory Access

26

8/14/2019 CE122- weeks01

27/31

Programmed I/O

I/O module performs theaction, not the processor

Sets appropriate bits in theI/O status register

No interrupts occur

Processor checks statusuntil operation is complete

8/14/2019 CE122- weeks01

28/31

Interrupt-Driven I/O

Processor is interrupted whenI/O module ready to exchangedata

Processor is free to do otherwork

No needless waiting

Consumes a lot of processor

time because every word reador written passes through theprocessor

8/14/2019 CE122- weeks01

29/31

Direct Memory Access

Transfers a block ofdata directly to or frommemory

An interrupt is sentwhen the task iscomplete

The processor is onlyinvolved at thebeginning and end of

the transfer

8/14/2019 CE122- weeks01

30/31

Computer - ComponentInterconnection

Component interconnection called bus.

Connects all the internal computercomponents to the CPU and main memory.

Three types of Bus: Address Bus : bus that used to send memory

address location or port will be read/write.

Data Bus : Bidirectional transfer, can read and

write to/from memory or port.

Control Bus : Bus that used by CPU by sendingsignal to commanding memory or I/O port.

30

8/14/2019 CE122- weeks01

31/31

Any Question?

31